src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "radv_shader_helper.h"
  34 #include "nir/nir.h"
  35 #include "nir/nir_builder.h"
  36 #include "spirv/nir_spirv.h"
  37
  38 #include <llvm-c/Core.h>
  39 #include <llvm-c/TargetMachine.h>
  40 #include <llvm-c/Support.h>
  41
  42 #include "sid.h"
  43 #include "gfx9d.h"
  44 #include "ac_binary.h"
  45 #include "ac_llvm_util.h"
  46 #include "ac_nir_to_llvm.h"
  47 #include "vk_format.h"
  48 #include "util/debug.h"
  49 #include "ac_exp_param.h"
  50
  51 #include "util/string_buffer.h"
  52
  53 static const struct nir_shader_compiler_options nir_options = {
  54         .vertex_id_zero_based = true,
  55         .lower_scmp = true,
  56         .lower_flrp32 = true,
  57         .lower_flrp64 = true,
  58         .lower_device_index_to_zero = true,
  59         .lower_fsat = true,
  60         .lower_fdiv = true,
  61         .lower_sub = true,
  62         .lower_pack_snorm_2x16 = true,
  63         .lower_pack_snorm_4x8 = true,
  64         .lower_pack_unorm_2x16 = true,
  65         .lower_pack_unorm_4x8 = true,
  66         .lower_unpack_snorm_2x16 = true,
  67         .lower_unpack_snorm_4x8 = true,
  68         .lower_unpack_unorm_2x16 = true,
  69         .lower_unpack_unorm_4x8 = true,
  70         .lower_extract_byte = true,
  71         .lower_extract_word = true,
  72         .lower_ffma = true,
  73         .lower_fpow = true,
  74         .vs_inputs_dual_locations = true,
  75         .max_unroll_iterations = 32
  76 };
  77
  78 VkResult radv_CreateShaderModule(
  79         VkDevice                                    _device,
  80         const VkShaderModuleCreateInfo*             pCreateInfo,
  81         const VkAllocationCallbacks*                pAllocator,
  82         VkShaderModule*                             pShaderModule)
  83 {
  84         RADV_FROM_HANDLE(radv_device, device, _device);
  85         struct radv_shader_module *module;
  86
  87         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  88         assert(pCreateInfo->flags == 0);
  89
  90         module = vk_alloc2(&device->alloc, pAllocator,
  91                              sizeof(*module) + pCreateInfo->codeSize, 8,
  92                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  93         if (module == NULL)
  94                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
  95
  96         module->nir = NULL;
  97         module->size = pCreateInfo->codeSize;
  98         memcpy(module->data, pCreateInfo->pCode, module->size);
  99
 100         _mesa_sha1_compute(module->data, module->size, module->sha1);
 101
 102         *pShaderModule = radv_shader_module_to_handle(module);
 103
 104         return VK_SUCCESS;
 105 }
 106
 107 void radv_DestroyShaderModule(
 108         VkDevice                                    _device,
 109         VkShaderModule                              _module,
 110         const VkAllocationCallbacks*                pAllocator)
 111 {
 112         RADV_FROM_HANDLE(radv_device, device, _device);
 113         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 114
 115         if (!module)
 116                 return;
 117
 118         vk_free2(&device->alloc, pAllocator, module);
 119 }
 120
 121 void
 122 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively)
 123 {
 124         bool progress;
 125
 126         do {
 127                 progress = false;
 128
 129                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 130                 NIR_PASS_V(shader, nir_lower_pack);
 131                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 132                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 133
 134                 NIR_PASS(progress, shader, nir_copy_prop);
 135                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 136                 NIR_PASS(progress, shader, nir_opt_dce);
 137                 if (nir_opt_trivial_continues(shader)) {
 138                         progress = true;
 139                         NIR_PASS(progress, shader, nir_copy_prop);
 140                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 141                         NIR_PASS(progress, shader, nir_opt_dce);
 142                 }
 143                 NIR_PASS(progress, shader, nir_opt_if);
 144                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 145                 NIR_PASS(progress, shader, nir_opt_cse);
 146                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 147                 NIR_PASS(progress, shader, nir_opt_algebraic);
 148                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 149                 NIR_PASS(progress, shader, nir_opt_undef);
 150                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 151                 if (shader->options->max_unroll_iterations) {
 152                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 153                 }
 154         } while (progress && !optimize_conservatively);
 155
 156         NIR_PASS(progress, shader, nir_opt_shrink_load);
 157         NIR_PASS(progress, shader, nir_opt_move_load_ubo);
 158 }
 159
 160 nir_shader *
 161 radv_shader_compile_to_nir(struct radv_device *device,
 162                            struct radv_shader_module *module,
 163                            const char *entrypoint_name,
 164                            gl_shader_stage stage,
 165                            const VkSpecializationInfo *spec_info,
 166                            const VkPipelineCreateFlags flags)
 167 {
 168         nir_shader *nir;
 169         nir_function *entry_point;
 170         if (module->nir) {
 171                 /* Some things such as our meta clear/blit code will give us a NIR
 172                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 173                  * and just use the NIR shader */
 174                 nir = module->nir;
 175                 nir->options = &nir_options;
 176                 nir_validate_shader(nir);
 177
 178                 assert(exec_list_length(&nir->functions) == 1);
 179                 struct exec_node *node = exec_list_get_head(&nir->functions);
 180                 entry_point = exec_node_data(nir_function, node, node);
 181         } else {
 182                 uint32_t *spirv = (uint32_t *) module->data;
 183                 assert(module->size % 4 == 0);
 184
 185                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 186                         radv_print_spirv(spirv, module->size, stderr);
 187
 188                 uint32_t num_spec_entries = 0;
 189                 struct nir_spirv_specialization *spec_entries = NULL;
 190                 if (spec_info && spec_info->mapEntryCount > 0) {
 191                         num_spec_entries = spec_info->mapEntryCount;
 192                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 193                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 194                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 195                                 const void *data = spec_info->pData + entry.offset;
 196                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 197
 198                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 199                                 if (spec_info->dataSize == 8)
 200                                         spec_entries[i].data64 = *(const uint64_t *)data;
 201                                 else
 202                                         spec_entries[i].data32 = *(const uint32_t *)data;
 203                         }
 204                 }
 205                 const struct spirv_to_nir_options spirv_options = {
 206                         .caps = {
 207                                 .device_group = true,
 208                                 .draw_parameters = true,
 209                                 .float64 = true,
 210                                 .image_read_without_format = true,
 211                                 .image_write_without_format = true,
 212                                 .tessellation = true,
 213                                 .int64 = true,
 214                                 .multiview = true,
 215                                 .subgroup_ballot = true,
 216                                 .subgroup_basic = true,
 217                                 .subgroup_quad = true,
 218                                 .subgroup_shuffle = true,
 219                                 .subgroup_vote = true,
 220                                 .variable_pointers = true,
 221                                 .gcn_shader = true,
 222                                 .trinary_minmax = true,
 223                                 .shader_viewport_index_layer = true,
 224                                 .descriptor_array_dynamic_indexing = true,
 225                                 .runtime_descriptor_array = true,
 226                                 .stencil_export = true,
 227                                 .storage_16bit = true,
 228                         },
 229                 };
 230                 entry_point = spirv_to_nir(spirv, module->size / 4,
 231                                            spec_entries, num_spec_entries,
 232                                            stage, entrypoint_name,
 233                                            &spirv_options, &nir_options);
 234                 nir = entry_point->shader;
 235                 assert(nir->info.stage == stage);
 236                 nir_validate_shader(nir);
 237
 238                 free(spec_entries);
 239
 240                 /* We have to lower away local constant initializers right before we
 241                  * inline functions.  That way they get properly initialized at the top
 242                  * of the function and not at the top of its caller.
 243                  */
 244                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 245                 NIR_PASS_V(nir, nir_lower_returns);
 246                 NIR_PASS_V(nir, nir_inline_functions);
 247                 NIR_PASS_V(nir, nir_copy_prop);
 248
 249                 /* Pick off the single entrypoint that we want */
 250                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 251                         if (func != entry_point)
 252                                 exec_node_remove(&func->node);
 253                 }
 254                 assert(exec_list_length(&nir->functions) == 1);
 255                 entry_point->name = ralloc_strdup(entry_point, "main");
 256
 257                 /* Make sure we lower constant initializers on output variables so that
 258                  * nir_remove_dead_variables below sees the corresponding stores
 259                  */
 260                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
 261
 262                 /* Now that we've deleted all but the main function, we can go ahead and
 263                  * lower the rest of the constant initializers.
 264                  */
 265                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 266
 267                 /* Split member structs.  We do this before lower_io_to_temporaries so that
 268                  * it doesn't lower system values to temporaries by accident.
 269                  */
 270                 NIR_PASS_V(nir, nir_split_var_copies);
 271                 NIR_PASS_V(nir, nir_split_per_member_structs);
 272
 273                 NIR_PASS_V(nir, nir_remove_dead_variables,
 274                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 275
 276                 NIR_PASS_V(nir, nir_lower_system_values);
 277                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 278         }
 279
 280         /* Vulkan uses the separate-shader linking model */
 281         nir->info.separate_shader = true;
 282
 283         nir_shader_gather_info(nir, entry_point->impl);
 284
 285         static const nir_lower_tex_options tex_options = {
 286           .lower_txp = ~0,
 287         };
 288
 289         nir_lower_tex(nir, &tex_options);
 290
 291         nir_lower_vars_to_ssa(nir);
 292
 293         if (nir->info.stage == MESA_SHADER_VERTEX ||
 294             nir->info.stage == MESA_SHADER_GEOMETRY) {
 295                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 296                            nir_shader_get_entrypoint(nir), true, true);
 297         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
 298                    nir->info.stage == MESA_SHADER_FRAGMENT) {
 299                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 300                            nir_shader_get_entrypoint(nir), true, false);
 301         }
 302
 303         nir_split_var_copies(nir);
 304         nir_lower_var_copies(nir);
 305
 306         nir_lower_global_vars_to_local(nir);
 307         nir_remove_dead_variables(nir, nir_var_local);
 308         nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 309                         .subgroup_size = 64,
 310                         .ballot_bit_size = 64,
 311                         .lower_to_scalar = 1,
 312                         .lower_subgroup_masks = 1,
 313                         .lower_shuffle = 1,
 314                         .lower_shuffle_to_32bit = 1,
 315                         .lower_vote_eq_to_ballot = 1,
 316                 });
 317
 318         if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
 319                 radv_optimize_nir(nir, false);
 320
 321         /* Indirect lowering must be called after the radv_optimize_nir() loop
 322          * has been called at least once. Otherwise indirect lowering can
 323          * bloat the instruction count of the loop and cause it to be
 324          * considered too large for unrolling.
 325          */
 326         ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
 327         radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT);
 328
 329         return nir;
 330 }
 331
 332 void *
 333 radv_alloc_shader_memory(struct radv_device *device,
 334                          struct radv_shader_variant *shader)
 335 {
 336         mtx_lock(&device->shader_slab_mutex);
 337         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 338                 uint64_t offset = 0;
 339                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 340                         if (s->bo_offset - offset >= shader->code_size) {
 341                                 shader->bo = slab->bo;
 342                                 shader->bo_offset = offset;
 343                                 list_addtail(&shader->slab_list, &s->slab_list);
 344                                 mtx_unlock(&device->shader_slab_mutex);
 345                                 return slab->ptr + offset;
 346                         }
 347                         offset = align_u64(s->bo_offset + s->code_size, 256);
 348                 }
 349                 if (slab->size - offset >= shader->code_size) {
 350                         shader->bo = slab->bo;
 351                         shader->bo_offset = offset;
 352                         list_addtail(&shader->slab_list, &slab->shaders);
 353                         mtx_unlock(&device->shader_slab_mutex);
 354                         return slab->ptr + offset;
 355                 }
 356         }
 357
 358         mtx_unlock(&device->shader_slab_mutex);
 359         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 360
 361         slab->size = 256 * 1024;
 362         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 363                                              RADEON_DOMAIN_VRAM,
 364                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 365                                              (device->physical_device->cpdma_prefetch_writes_memory ?
 366                                                      0 : RADEON_FLAG_READ_ONLY));
 367         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 368         list_inithead(&slab->shaders);
 369
 370         mtx_lock(&device->shader_slab_mutex);
 371         list_add(&slab->slabs, &device->shader_slabs);
 372
 373         shader->bo = slab->bo;
 374         shader->bo_offset = 0;
 375         list_add(&shader->slab_list, &slab->shaders);
 376         mtx_unlock(&device->shader_slab_mutex);
 377         return slab->ptr;
 378 }
 379
 380 void
 381 radv_destroy_shader_slabs(struct radv_device *device)
 382 {
 383         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 384                 device->ws->buffer_destroy(slab->bo);
 385                 free(slab);
 386         }
 387         mtx_destroy(&device->shader_slab_mutex);
 388 }
 389
 390 /* For the UMR disassembler. */
 391 #define DEBUGGER_END_OF_CODE_MARKER    0xbf9f0000 /* invalid instruction */
 392 #define DEBUGGER_NUM_MARKERS           5
 393
 394 static unsigned
 395 radv_get_shader_binary_size(struct ac_shader_binary *binary)
 396 {
 397         return binary->code_size + DEBUGGER_NUM_MARKERS * 4;
 398 }
 399
 400 static void
 401 radv_fill_shader_variant(struct radv_device *device,
 402                          struct radv_shader_variant *variant,
 403                          struct ac_shader_binary *binary,
 404                          gl_shader_stage stage)
 405 {
 406         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 407         struct radv_shader_info *info = &variant->info.info;
 408         unsigned vgpr_comp_cnt = 0;
 409
 410         variant->code_size = radv_get_shader_binary_size(binary);
 411         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 412                          S_00B12C_SCRATCH_EN(scratch_enabled);
 413
 414         variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 415                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 416                 S_00B848_DX10_CLAMP(1) |
 417                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 418
 419         switch (stage) {
 420         case MESA_SHADER_TESS_EVAL:
 421                 vgpr_comp_cnt = 3;
 422                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 423                 break;
 424         case MESA_SHADER_TESS_CTRL:
 425                 if (device->physical_device->rad_info.chip_class >= GFX9) {
 426                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 427                 } else {
 428                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 429                 }
 430                 break;
 431         case MESA_SHADER_VERTEX:
 432         case MESA_SHADER_GEOMETRY:
 433                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 434                 break;
 435         case MESA_SHADER_FRAGMENT:
 436                 break;
 437         case MESA_SHADER_COMPUTE:
 438                 variant->rsrc2 |=
 439                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 440                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 441                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 442                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 443                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 444                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 445                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 446                 break;
 447         default:
 448                 unreachable("unsupported shader type");
 449                 break;
 450         }
 451
 452         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 453             stage == MESA_SHADER_GEOMETRY) {
 454                 unsigned es_type = variant->info.gs.es_type;
 455                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 456
 457                 if (es_type == MESA_SHADER_VERTEX) {
 458                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 459                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 460                         es_vgpr_comp_cnt = 3;
 461                 } else {
 462                         unreachable("invalid shader ES type");
 463                 }
 464
 465                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 466                  * VGPR[0:4] are always loaded.
 467                  */
 468                 if (info->uses_invocation_id) {
 469                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 470                 } else if (info->uses_prim_id) {
 471                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 472                 } else if (variant->info.gs.vertices_in >= 3) {
 473                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 474                 } else {
 475                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 476                 }
 477
 478                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 479                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 480                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 481         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 482                    stage == MESA_SHADER_TESS_CTRL) {
 483                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 484         } else {
 485                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 486         }
 487
 488         void *ptr = radv_alloc_shader_memory(device, variant);
 489         memcpy(ptr, binary->code, binary->code_size);
 490
 491         /* Add end-of-code markers for the UMR disassembler. */
 492        uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4;
 493        for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
 494                 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
 495
 496 }
 497
 498 static void radv_init_llvm_target()
 499 {
 500         LLVMInitializeAMDGPUTargetInfo();
 501         LLVMInitializeAMDGPUTarget();
 502         LLVMInitializeAMDGPUTargetMC();
 503         LLVMInitializeAMDGPUAsmPrinter();
 504
 505         /* For inline assembly. */
 506         LLVMInitializeAMDGPUAsmParser();
 507
 508         /* Workaround for bug in llvm 4.0 that causes image intrinsics
 509          * to disappear.
 510          * https://reviews.llvm.org/D26348
 511          *
 512          * Workaround for bug in llvm that causes the GPU to hang in presence
 513          * of nested loops because there is an exec mask issue. The proper
 514          * solution is to fix LLVM but this might require a bunch of work.
 515          * https://bugs.llvm.org/show_bug.cgi?id=37744
 516          *
 517          * "mesa" is the prefix for error messages.
 518          */
 519         const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
 520                                 "-amdgpu-skip-threshold=1" };
 521         LLVMParseCommandLineOptions(3, argv, NULL);
 522 }
 523
 524 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
 525
 526 static void radv_init_llvm_once(void)
 527 {
 528         call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
 529 }
 530
 531 static struct radv_shader_variant *
 532 shader_variant_create(struct radv_device *device,
 533                       struct radv_shader_module *module,
 534                       struct nir_shader * const *shaders,
 535                       int shader_count,
 536                       gl_shader_stage stage,
 537                       struct radv_nir_compiler_options *options,
 538                       bool gs_copy_shader,
 539                       void **code_out,
 540                       unsigned *code_size_out)
 541 {
 542         enum radeon_family chip_family = device->physical_device->rad_info.family;
 543         enum ac_target_machine_options tm_options = 0;
 544         struct radv_shader_variant *variant;
 545         struct ac_shader_binary binary;
 546         struct ac_llvm_compiler ac_llvm;
 547         bool thread_compiler;
 548         variant = calloc(1, sizeof(struct radv_shader_variant));
 549         if (!variant)
 550                 return NULL;
 551
 552         options->family = chip_family;
 553         options->chip_class = device->physical_device->rad_info.chip_class;
 554         options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
 555         options->dump_preoptir = options->dump_shader &&
 556                                  device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
 557         options->record_llvm_ir = device->keep_shader_info;
 558         options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
 559         options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
 560         options->address32_hi = device->physical_device->rad_info.address32_hi;
 561
 562         if (options->supports_spill)
 563                 tm_options |= AC_TM_SUPPORTS_SPILL;
 564         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 565                 tm_options |= AC_TM_SISCHED;
 566         if (options->check_ir)
 567                 tm_options |= AC_TM_CHECK_IR;
 568
 569         thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
 570         radv_init_llvm_once();
 571         radv_init_llvm_compiler(&ac_llvm, false,
 572                                 thread_compiler,
 573                                 chip_family, tm_options);
 574         if (gs_copy_shader) {
 575                 assert(shader_count == 1);
 576                 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
 577                                             &variant->config, &variant->info,
 578                                             options);
 579         } else {
 580                 radv_compile_nir_shader(&ac_llvm, &binary, &variant->config,
 581                                         &variant->info, shaders, shader_count,
 582                                         options);
 583         }
 584
 585         radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
 586
 587         radv_fill_shader_variant(device, variant, &binary, stage);
 588
 589         if (code_out) {
 590                 *code_out = binary.code;
 591                 *code_size_out = binary.code_size;
 592         } else
 593                 free(binary.code);
 594         free(binary.config);
 595         free(binary.rodata);
 596         free(binary.global_symbol_offsets);
 597         free(binary.relocs);
 598         variant->ref_count = 1;
 599
 600         if (device->keep_shader_info) {
 601                 variant->disasm_string = binary.disasm_string;
 602                 variant->llvm_ir_string = binary.llvm_ir_string;
 603                 if (!gs_copy_shader && !module->nir) {
 604                         variant->nir = *shaders;
 605                         variant->spirv = (uint32_t *)module->data;
 606                         variant->spirv_size = module->size;
 607                 }
 608         } else {
 609                 free(binary.disasm_string);
 610         }
 611
 612         return variant;
 613 }
 614
 615 struct radv_shader_variant *
 616 radv_shader_variant_create(struct radv_device *device,
 617                            struct radv_shader_module *module,
 618                            struct nir_shader *const *shaders,
 619                            int shader_count,
 620                            struct radv_pipeline_layout *layout,
 621                            const struct radv_shader_variant_key *key,
 622                            void **code_out,
 623                            unsigned *code_size_out)
 624 {
 625         struct radv_nir_compiler_options options = {0};
 626
 627         options.layout = layout;
 628         if (key)
 629                 options.key = *key;
 630
 631         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 632         options.supports_spill = true;
 633
 634         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 635                                      &options, false, code_out, code_size_out);
 636 }
 637
 638 struct radv_shader_variant *
 639 radv_create_gs_copy_shader(struct radv_device *device,
 640                            struct nir_shader *shader,
 641                            void **code_out,
 642                            unsigned *code_size_out,
 643                            bool multiview)
 644 {
 645         struct radv_nir_compiler_options options = {0};
 646
 647         options.key.has_multiview_view_index = multiview;
 648
 649         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 650                                      &options, true, code_out, code_size_out);
 651 }
 652
 653 void
 654 radv_shader_variant_destroy(struct radv_device *device,
 655                             struct radv_shader_variant *variant)
 656 {
 657         if (!p_atomic_dec_zero(&variant->ref_count))
 658                 return;
 659
 660         mtx_lock(&device->shader_slab_mutex);
 661         list_del(&variant->slab_list);
 662         mtx_unlock(&device->shader_slab_mutex);
 663
 664         ralloc_free(variant->nir);
 665         free(variant->disasm_string);
 666         free(variant->llvm_ir_string);
 667         free(variant);
 668 }
 669
 670 const char *
 671 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 672 {
 673         switch (stage) {
 674         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 675         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 676         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 677         case MESA_SHADER_COMPUTE: return "Compute Shader";
 678         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 679         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 680         default:
 681                 return "Unknown shader";
 682         };
 683 }
 684
 685 static void
 686 generate_shader_stats(struct radv_device *device,
 687                       struct radv_shader_variant *variant,
 688                       gl_shader_stage stage,
 689                       struct _mesa_string_buffer *buf)
 690 {
 691         unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 692         struct ac_shader_config *conf;
 693         unsigned max_simd_waves;
 694         unsigned lds_per_wave = 0;
 695
 696         max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
 697
 698         conf = &variant->config;
 699
 700         if (stage == MESA_SHADER_FRAGMENT) {
 701                 lds_per_wave = conf->lds_size * lds_increment +
 702                                align(variant->info.fs.num_interp * 48,
 703                                      lds_increment);
 704         }
 705
 706         if (conf->num_sgprs)
 707                 max_simd_waves =
 708                         MIN2(max_simd_waves,
 709                              radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
 710
 711         if (conf->num_vgprs)
 712                 max_simd_waves =
 713                         MIN2(max_simd_waves,
 714                              RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
 715
 716         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 717          * that PS can use.
 718          */
 719         if (lds_per_wave)
 720                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 721
 722         if (stage == MESA_SHADER_FRAGMENT) {
 723                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 724                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 725                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 726                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 727         }
 728
 729         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 730                                    "SGPRS: %d\n"
 731                                    "VGPRS: %d\n"
 732                                    "Spilled SGPRs: %d\n"
 733                                    "Spilled VGPRs: %d\n"
 734                                    "PrivMem VGPRS: %d\n"
 735                                    "Code Size: %d bytes\n"
 736                                    "LDS: %d blocks\n"
 737                                    "Scratch: %d bytes per wave\n"
 738                                    "Max Waves: %d\n"
 739                                    "********************\n\n\n",
 740                                    conf->num_sgprs, conf->num_vgprs,
 741                                    conf->spilled_sgprs, conf->spilled_vgprs,
 742                                    variant->info.private_mem_vgprs, variant->code_size,
 743                                    conf->lds_size, conf->scratch_bytes_per_wave,
 744                                    max_simd_waves);
 745 }
 746
 747 void
 748 radv_shader_dump_stats(struct radv_device *device,
 749                        struct radv_shader_variant *variant,
 750                        gl_shader_stage stage,
 751                        FILE *file)
 752 {
 753         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 754
 755         generate_shader_stats(device, variant, stage, buf);
 756
 757         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 758         fprintf(file, "%s", buf->buf);
 759
 760         _mesa_string_buffer_destroy(buf);
 761 }
 762
 763 VkResult
 764 radv_GetShaderInfoAMD(VkDevice _device,
 765                       VkPipeline _pipeline,
 766                       VkShaderStageFlagBits shaderStage,
 767                       VkShaderInfoTypeAMD infoType,
 768                       size_t* pInfoSize,
 769                       void* pInfo)
 770 {
 771         RADV_FROM_HANDLE(radv_device, device, _device);
 772         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 773         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 774         struct radv_shader_variant *variant = pipeline->shaders[stage];
 775         struct _mesa_string_buffer *buf;
 776         VkResult result = VK_SUCCESS;
 777
 778         /* Spec doesn't indicate what to do if the stage is invalid, so just
 779          * return no info for this. */
 780         if (!variant)
 781                 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
 782
 783         switch (infoType) {
 784         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 785                 if (!pInfo) {
 786                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 787                 } else {
 788                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 789                         struct ac_shader_config *conf = &variant->config;
 790
 791                         VkShaderStatisticsInfoAMD statistics = {};
 792                         statistics.shaderStageMask = shaderStage;
 793                         statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
 794                         statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device);
 795                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 796
 797                         if (stage == MESA_SHADER_COMPUTE) {
 798                                 unsigned *local_size = variant->nir->info.cs.local_size;
 799                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 800
 801                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 802                                                                ceil((double)workgroup_size / statistics.numPhysicalVgprs);
 803
 804                                 statistics.computeWorkGroupSize[0] = local_size[0];
 805                                 statistics.computeWorkGroupSize[1] = local_size[1];
 806                                 statistics.computeWorkGroupSize[2] = local_size[2];
 807                         } else {
 808                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 809                         }
 810
 811                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 812                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 813                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 814                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 815                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 816
 817                         size_t size = *pInfoSize;
 818                         *pInfoSize = sizeof(statistics);
 819
 820                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 821
 822                         if (size < *pInfoSize)
 823                                 result = VK_INCOMPLETE;
 824                 }
 825
 826                 break;
 827         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 828                 buf = _mesa_string_buffer_create(NULL, 1024);
 829
 830                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 831                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 832                 generate_shader_stats(device, variant, stage, buf);
 833
 834                 /* Need to include the null terminator. */
 835                 size_t length = buf->length + 1;
 836
 837                 if (!pInfo) {
 838                         *pInfoSize = length;
 839                 } else {
 840                         size_t size = *pInfoSize;
 841                         *pInfoSize = length;
 842
 843                         memcpy(pInfo, buf->buf, MIN2(size, length));
 844
 845                         if (size < length)
 846                                 result = VK_INCOMPLETE;
 847                 }
 848
 849                 _mesa_string_buffer_destroy(buf);
 850                 break;
 851         default:
 852                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 853                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 854                 break;
 855         }
 856
 857         return result;
 858 }