src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "radv_shader_helper.h"
  34 #include "nir/nir.h"
  35 #include "nir/nir_builder.h"
  36 #include "spirv/nir_spirv.h"
  37
  38 #include <llvm-c/Core.h>
  39 #include <llvm-c/TargetMachine.h>
  40 #include <llvm-c/Support.h>
  41
  42 #include "sid.h"
  43 #include "gfx9d.h"
  44 #include "ac_binary.h"
  45 #include "ac_llvm_util.h"
  46 #include "ac_nir_to_llvm.h"
  47 #include "vk_format.h"
  48 #include "util/debug.h"
  49 #include "ac_exp_param.h"
  50
  51 #include "util/string_buffer.h"
  52
  53 static const struct nir_shader_compiler_options nir_options = {
  54         .vertex_id_zero_based = true,
  55         .lower_scmp = true,
  56         .lower_flrp32 = true,
  57         .lower_flrp64 = true,
  58         .lower_device_index_to_zero = true,
  59         .lower_fsat = true,
  60         .lower_fdiv = true,
  61         .lower_sub = true,
  62         .lower_pack_snorm_2x16 = true,
  63         .lower_pack_snorm_4x8 = true,
  64         .lower_pack_unorm_2x16 = true,
  65         .lower_pack_unorm_4x8 = true,
  66         .lower_unpack_snorm_2x16 = true,
  67         .lower_unpack_snorm_4x8 = true,
  68         .lower_unpack_unorm_2x16 = true,
  69         .lower_unpack_unorm_4x8 = true,
  70         .lower_extract_byte = true,
  71         .lower_extract_word = true,
  72         .lower_ffma = true,
  73         .lower_fpow = true,
  74         .max_unroll_iterations = 32
  75 };
  76
  77 VkResult radv_CreateShaderModule(
  78         VkDevice                                    _device,
  79         const VkShaderModuleCreateInfo*             pCreateInfo,
  80         const VkAllocationCallbacks*                pAllocator,
  81         VkShaderModule*                             pShaderModule)
  82 {
  83         RADV_FROM_HANDLE(radv_device, device, _device);
  84         struct radv_shader_module *module;
  85
  86         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  87         assert(pCreateInfo->flags == 0);
  88
  89         module = vk_alloc2(&device->alloc, pAllocator,
  90                              sizeof(*module) + pCreateInfo->codeSize, 8,
  91                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  92         if (module == NULL)
  93                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
  94
  95         module->nir = NULL;
  96         module->size = pCreateInfo->codeSize;
  97         memcpy(module->data, pCreateInfo->pCode, module->size);
  98
  99         _mesa_sha1_compute(module->data, module->size, module->sha1);
 100
 101         *pShaderModule = radv_shader_module_to_handle(module);
 102
 103         return VK_SUCCESS;
 104 }
 105
 106 void radv_DestroyShaderModule(
 107         VkDevice                                    _device,
 108         VkShaderModule                              _module,
 109         const VkAllocationCallbacks*                pAllocator)
 110 {
 111         RADV_FROM_HANDLE(radv_device, device, _device);
 112         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 113
 114         if (!module)
 115                 return;
 116
 117         vk_free2(&device->alloc, pAllocator, module);
 118 }
 119
 120 void
 121 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively)
 122 {
 123         bool progress;
 124
 125         do {
 126                 progress = false;
 127
 128                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 129                 NIR_PASS_V(shader, nir_lower_pack);
 130                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 131                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 132
 133                 NIR_PASS(progress, shader, nir_copy_prop);
 134                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 135                 NIR_PASS(progress, shader, nir_opt_dce);
 136                 if (nir_opt_trivial_continues(shader)) {
 137                         progress = true;
 138                         NIR_PASS(progress, shader, nir_copy_prop);
 139                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 140                         NIR_PASS(progress, shader, nir_opt_dce);
 141                 }
 142                 NIR_PASS(progress, shader, nir_opt_if);
 143                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 144                 NIR_PASS(progress, shader, nir_opt_cse);
 145                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 146                 NIR_PASS(progress, shader, nir_opt_algebraic);
 147                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 148                 NIR_PASS(progress, shader, nir_opt_undef);
 149                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 150                 if (shader->options->max_unroll_iterations) {
 151                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 152                 }
 153         } while (progress && !optimize_conservatively);
 154
 155         NIR_PASS(progress, shader, nir_opt_shrink_load);
 156         NIR_PASS(progress, shader, nir_opt_move_load_ubo);
 157 }
 158
 159 nir_shader *
 160 radv_shader_compile_to_nir(struct radv_device *device,
 161                            struct radv_shader_module *module,
 162                            const char *entrypoint_name,
 163                            gl_shader_stage stage,
 164                            const VkSpecializationInfo *spec_info,
 165                            const VkPipelineCreateFlags flags)
 166 {
 167         nir_shader *nir;
 168         nir_function *entry_point;
 169         if (module->nir) {
 170                 /* Some things such as our meta clear/blit code will give us a NIR
 171                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 172                  * and just use the NIR shader */
 173                 nir = module->nir;
 174                 nir->options = &nir_options;
 175                 nir_validate_shader(nir);
 176
 177                 assert(exec_list_length(&nir->functions) == 1);
 178                 struct exec_node *node = exec_list_get_head(&nir->functions);
 179                 entry_point = exec_node_data(nir_function, node, node);
 180         } else {
 181                 uint32_t *spirv = (uint32_t *) module->data;
 182                 assert(module->size % 4 == 0);
 183
 184                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 185                         radv_print_spirv(spirv, module->size, stderr);
 186
 187                 uint32_t num_spec_entries = 0;
 188                 struct nir_spirv_specialization *spec_entries = NULL;
 189                 if (spec_info && spec_info->mapEntryCount > 0) {
 190                         num_spec_entries = spec_info->mapEntryCount;
 191                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 192                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 193                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 194                                 const void *data = spec_info->pData + entry.offset;
 195                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 196
 197                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 198                                 if (spec_info->dataSize == 8)
 199                                         spec_entries[i].data64 = *(const uint64_t *)data;
 200                                 else
 201                                         spec_entries[i].data32 = *(const uint32_t *)data;
 202                         }
 203                 }
 204                 const struct spirv_to_nir_options spirv_options = {
 205                         .caps = {
 206                                 .device_group = true,
 207                                 .draw_parameters = true,
 208                                 .float64 = true,
 209                                 .image_read_without_format = true,
 210                                 .image_write_without_format = true,
 211                                 .tessellation = true,
 212                                 .int64 = true,
 213                                 .int16 = true,
 214                                 .multiview = true,
 215                                 .subgroup_arithmetic = true,
 216                                 .subgroup_ballot = true,
 217                                 .subgroup_basic = true,
 218                                 .subgroup_quad = true,
 219                                 .subgroup_shuffle = true,
 220                                 .subgroup_vote = true,
 221                                 .variable_pointers = true,
 222                                 .gcn_shader = true,
 223                                 .trinary_minmax = true,
 224                                 .shader_viewport_index_layer = true,
 225                                 .descriptor_array_dynamic_indexing = true,
 226                                 .runtime_descriptor_array = true,
 227                                 .stencil_export = true,
 228                                 .storage_16bit = true,
 229                         },
 230                 };
 231                 entry_point = spirv_to_nir(spirv, module->size / 4,
 232                                            spec_entries, num_spec_entries,
 233                                            stage, entrypoint_name,
 234                                            &spirv_options, &nir_options);
 235                 nir = entry_point->shader;
 236                 assert(nir->info.stage == stage);
 237                 nir_validate_shader(nir);
 238
 239                 free(spec_entries);
 240
 241                 /* We have to lower away local constant initializers right before we
 242                  * inline functions.  That way they get properly initialized at the top
 243                  * of the function and not at the top of its caller.
 244                  */
 245                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 246                 NIR_PASS_V(nir, nir_lower_returns);
 247                 NIR_PASS_V(nir, nir_inline_functions);
 248                 NIR_PASS_V(nir, nir_copy_prop);
 249
 250                 /* Pick off the single entrypoint that we want */
 251                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 252                         if (func != entry_point)
 253                                 exec_node_remove(&func->node);
 254                 }
 255                 assert(exec_list_length(&nir->functions) == 1);
 256                 entry_point->name = ralloc_strdup(entry_point, "main");
 257
 258                 /* Make sure we lower constant initializers on output variables so that
 259                  * nir_remove_dead_variables below sees the corresponding stores
 260                  */
 261                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
 262
 263                 /* Now that we've deleted all but the main function, we can go ahead and
 264                  * lower the rest of the constant initializers.
 265                  */
 266                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 267
 268                 /* Split member structs.  We do this before lower_io_to_temporaries so that
 269                  * it doesn't lower system values to temporaries by accident.
 270                  */
 271                 NIR_PASS_V(nir, nir_split_var_copies);
 272                 NIR_PASS_V(nir, nir_split_per_member_structs);
 273
 274                 NIR_PASS_V(nir, nir_remove_dead_variables,
 275                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 276
 277                 NIR_PASS_V(nir, nir_lower_system_values);
 278                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 279         }
 280
 281         /* Vulkan uses the separate-shader linking model */
 282         nir->info.separate_shader = true;
 283
 284         nir_shader_gather_info(nir, entry_point->impl);
 285
 286         static const nir_lower_tex_options tex_options = {
 287           .lower_txp = ~0,
 288         };
 289
 290         nir_lower_tex(nir, &tex_options);
 291
 292         nir_lower_vars_to_ssa(nir);
 293
 294         if (nir->info.stage == MESA_SHADER_VERTEX ||
 295             nir->info.stage == MESA_SHADER_GEOMETRY) {
 296                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 297                            nir_shader_get_entrypoint(nir), true, true);
 298         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
 299                    nir->info.stage == MESA_SHADER_FRAGMENT) {
 300                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 301                            nir_shader_get_entrypoint(nir), true, false);
 302         }
 303
 304         nir_split_var_copies(nir);
 305         nir_lower_var_copies(nir);
 306
 307         nir_lower_global_vars_to_local(nir);
 308         nir_remove_dead_variables(nir, nir_var_local);
 309         nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 310                         .subgroup_size = 64,
 311                         .ballot_bit_size = 64,
 312                         .lower_to_scalar = 1,
 313                         .lower_subgroup_masks = 1,
 314                         .lower_shuffle = 1,
 315                         .lower_shuffle_to_32bit = 1,
 316                         .lower_vote_eq_to_ballot = 1,
 317                 });
 318
 319         if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
 320                 radv_optimize_nir(nir, false);
 321
 322         /* Indirect lowering must be called after the radv_optimize_nir() loop
 323          * has been called at least once. Otherwise indirect lowering can
 324          * bloat the instruction count of the loop and cause it to be
 325          * considered too large for unrolling.
 326          */
 327         ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
 328         radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT);
 329
 330         return nir;
 331 }
 332
 333 void *
 334 radv_alloc_shader_memory(struct radv_device *device,
 335                          struct radv_shader_variant *shader)
 336 {
 337         mtx_lock(&device->shader_slab_mutex);
 338         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 339                 uint64_t offset = 0;
 340                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 341                         if (s->bo_offset - offset >= shader->code_size) {
 342                                 shader->bo = slab->bo;
 343                                 shader->bo_offset = offset;
 344                                 list_addtail(&shader->slab_list, &s->slab_list);
 345                                 mtx_unlock(&device->shader_slab_mutex);
 346                                 return slab->ptr + offset;
 347                         }
 348                         offset = align_u64(s->bo_offset + s->code_size, 256);
 349                 }
 350                 if (slab->size - offset >= shader->code_size) {
 351                         shader->bo = slab->bo;
 352                         shader->bo_offset = offset;
 353                         list_addtail(&shader->slab_list, &slab->shaders);
 354                         mtx_unlock(&device->shader_slab_mutex);
 355                         return slab->ptr + offset;
 356                 }
 357         }
 358
 359         mtx_unlock(&device->shader_slab_mutex);
 360         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 361
 362         slab->size = 256 * 1024;
 363         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 364                                              RADEON_DOMAIN_VRAM,
 365                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 366                                              (device->physical_device->cpdma_prefetch_writes_memory ?
 367                                                      0 : RADEON_FLAG_READ_ONLY));
 368         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 369         list_inithead(&slab->shaders);
 370
 371         mtx_lock(&device->shader_slab_mutex);
 372         list_add(&slab->slabs, &device->shader_slabs);
 373
 374         shader->bo = slab->bo;
 375         shader->bo_offset = 0;
 376         list_add(&shader->slab_list, &slab->shaders);
 377         mtx_unlock(&device->shader_slab_mutex);
 378         return slab->ptr;
 379 }
 380
 381 void
 382 radv_destroy_shader_slabs(struct radv_device *device)
 383 {
 384         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 385                 device->ws->buffer_destroy(slab->bo);
 386                 free(slab);
 387         }
 388         mtx_destroy(&device->shader_slab_mutex);
 389 }
 390
 391 /* For the UMR disassembler. */
 392 #define DEBUGGER_END_OF_CODE_MARKER    0xbf9f0000 /* invalid instruction */
 393 #define DEBUGGER_NUM_MARKERS           5
 394
 395 static unsigned
 396 radv_get_shader_binary_size(struct ac_shader_binary *binary)
 397 {
 398         return binary->code_size + DEBUGGER_NUM_MARKERS * 4;
 399 }
 400
 401 static void
 402 radv_fill_shader_variant(struct radv_device *device,
 403                          struct radv_shader_variant *variant,
 404                          struct ac_shader_binary *binary,
 405                          gl_shader_stage stage)
 406 {
 407         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 408         struct radv_shader_info *info = &variant->info.info;
 409         unsigned vgpr_comp_cnt = 0;
 410
 411         variant->code_size = radv_get_shader_binary_size(binary);
 412         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 413                          S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
 414                          S_00B12C_SCRATCH_EN(scratch_enabled);
 415
 416         variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 417                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 418                 S_00B848_DX10_CLAMP(1) |
 419                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 420
 421         switch (stage) {
 422         case MESA_SHADER_TESS_EVAL:
 423                 vgpr_comp_cnt = 3;
 424                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 425                 break;
 426         case MESA_SHADER_TESS_CTRL:
 427                 if (device->physical_device->rad_info.chip_class >= GFX9) {
 428                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 429                 } else {
 430                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 431                 }
 432                 break;
 433         case MESA_SHADER_VERTEX:
 434         case MESA_SHADER_GEOMETRY:
 435                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 436                 break;
 437         case MESA_SHADER_FRAGMENT:
 438                 break;
 439         case MESA_SHADER_COMPUTE:
 440                 variant->rsrc2 |=
 441                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 442                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 443                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 444                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 445                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 446                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 447                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 448                 break;
 449         default:
 450                 unreachable("unsupported shader type");
 451                 break;
 452         }
 453
 454         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 455             stage == MESA_SHADER_GEOMETRY) {
 456                 unsigned es_type = variant->info.gs.es_type;
 457                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 458
 459                 if (es_type == MESA_SHADER_VERTEX) {
 460                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 461                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 462                         es_vgpr_comp_cnt = 3;
 463                 } else {
 464                         unreachable("invalid shader ES type");
 465                 }
 466
 467                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 468                  * VGPR[0:4] are always loaded.
 469                  */
 470                 if (info->uses_invocation_id) {
 471                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 472                 } else if (info->uses_prim_id) {
 473                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 474                 } else if (variant->info.gs.vertices_in >= 3) {
 475                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 476                 } else {
 477                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 478                 }
 479
 480                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 481                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 482                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 483         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 484                    stage == MESA_SHADER_TESS_CTRL) {
 485                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 486         } else {
 487                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 488         }
 489
 490         void *ptr = radv_alloc_shader_memory(device, variant);
 491         memcpy(ptr, binary->code, binary->code_size);
 492
 493         /* Add end-of-code markers for the UMR disassembler. */
 494        uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4;
 495        for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
 496                 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
 497
 498 }
 499
 500 static void radv_init_llvm_target()
 501 {
 502         LLVMInitializeAMDGPUTargetInfo();
 503         LLVMInitializeAMDGPUTarget();
 504         LLVMInitializeAMDGPUTargetMC();
 505         LLVMInitializeAMDGPUAsmPrinter();
 506
 507         /* For inline assembly. */
 508         LLVMInitializeAMDGPUAsmParser();
 509
 510         /* Workaround for bug in llvm 4.0 that causes image intrinsics
 511          * to disappear.
 512          * https://reviews.llvm.org/D26348
 513          *
 514          * Workaround for bug in llvm that causes the GPU to hang in presence
 515          * of nested loops because there is an exec mask issue. The proper
 516          * solution is to fix LLVM but this might require a bunch of work.
 517          * https://bugs.llvm.org/show_bug.cgi?id=37744
 518          *
 519          * "mesa" is the prefix for error messages.
 520          */
 521         const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
 522                                 "-amdgpu-skip-threshold=1" };
 523         LLVMParseCommandLineOptions(3, argv, NULL);
 524 }
 525
 526 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
 527
 528 static void radv_init_llvm_once(void)
 529 {
 530         call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
 531 }
 532
 533 static struct radv_shader_variant *
 534 shader_variant_create(struct radv_device *device,
 535                       struct radv_shader_module *module,
 536                       struct nir_shader * const *shaders,
 537                       int shader_count,
 538                       gl_shader_stage stage,
 539                       struct radv_nir_compiler_options *options,
 540                       bool gs_copy_shader,
 541                       void **code_out,
 542                       unsigned *code_size_out)
 543 {
 544         enum radeon_family chip_family = device->physical_device->rad_info.family;
 545         enum ac_target_machine_options tm_options = 0;
 546         struct radv_shader_variant *variant;
 547         struct ac_shader_binary binary;
 548         struct ac_llvm_compiler ac_llvm;
 549         bool thread_compiler;
 550         variant = calloc(1, sizeof(struct radv_shader_variant));
 551         if (!variant)
 552                 return NULL;
 553
 554         options->family = chip_family;
 555         options->chip_class = device->physical_device->rad_info.chip_class;
 556         options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
 557         options->dump_preoptir = options->dump_shader &&
 558                                  device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
 559         options->record_llvm_ir = device->keep_shader_info;
 560         options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
 561         options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
 562         options->address32_hi = device->physical_device->rad_info.address32_hi;
 563
 564         if (options->supports_spill)
 565                 tm_options |= AC_TM_SUPPORTS_SPILL;
 566         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 567                 tm_options |= AC_TM_SISCHED;
 568         if (options->check_ir)
 569                 tm_options |= AC_TM_CHECK_IR;
 570
 571         thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
 572         radv_init_llvm_once();
 573         radv_init_llvm_compiler(&ac_llvm, false,
 574                                 thread_compiler,
 575                                 chip_family, tm_options);
 576         if (gs_copy_shader) {
 577                 assert(shader_count == 1);
 578                 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
 579                                             &variant->config, &variant->info,
 580                                             options);
 581         } else {
 582                 radv_compile_nir_shader(&ac_llvm, &binary, &variant->config,
 583                                         &variant->info, shaders, shader_count,
 584                                         options);
 585         }
 586
 587         radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
 588
 589         radv_fill_shader_variant(device, variant, &binary, stage);
 590
 591         if (code_out) {
 592                 *code_out = binary.code;
 593                 *code_size_out = binary.code_size;
 594         } else
 595                 free(binary.code);
 596         free(binary.config);
 597         free(binary.rodata);
 598         free(binary.global_symbol_offsets);
 599         free(binary.relocs);
 600         variant->ref_count = 1;
 601
 602         if (device->keep_shader_info) {
 603                 variant->disasm_string = binary.disasm_string;
 604                 variant->llvm_ir_string = binary.llvm_ir_string;
 605                 if (!gs_copy_shader && !module->nir) {
 606                         variant->nir = *shaders;
 607                         variant->spirv = (uint32_t *)module->data;
 608                         variant->spirv_size = module->size;
 609                 }
 610         } else {
 611                 free(binary.disasm_string);
 612         }
 613
 614         return variant;
 615 }
 616
 617 struct radv_shader_variant *
 618 radv_shader_variant_create(struct radv_device *device,
 619                            struct radv_shader_module *module,
 620                            struct nir_shader *const *shaders,
 621                            int shader_count,
 622                            struct radv_pipeline_layout *layout,
 623                            const struct radv_shader_variant_key *key,
 624                            void **code_out,
 625                            unsigned *code_size_out)
 626 {
 627         struct radv_nir_compiler_options options = {0};
 628
 629         options.layout = layout;
 630         if (key)
 631                 options.key = *key;
 632
 633         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 634         options.supports_spill = true;
 635
 636         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 637                                      &options, false, code_out, code_size_out);
 638 }
 639
 640 struct radv_shader_variant *
 641 radv_create_gs_copy_shader(struct radv_device *device,
 642                            struct nir_shader *shader,
 643                            void **code_out,
 644                            unsigned *code_size_out,
 645                            bool multiview)
 646 {
 647         struct radv_nir_compiler_options options = {0};
 648
 649         options.key.has_multiview_view_index = multiview;
 650
 651         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 652                                      &options, true, code_out, code_size_out);
 653 }
 654
 655 void
 656 radv_shader_variant_destroy(struct radv_device *device,
 657                             struct radv_shader_variant *variant)
 658 {
 659         if (!p_atomic_dec_zero(&variant->ref_count))
 660                 return;
 661
 662         mtx_lock(&device->shader_slab_mutex);
 663         list_del(&variant->slab_list);
 664         mtx_unlock(&device->shader_slab_mutex);
 665
 666         ralloc_free(variant->nir);
 667         free(variant->disasm_string);
 668         free(variant->llvm_ir_string);
 669         free(variant);
 670 }
 671
 672 const char *
 673 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 674 {
 675         switch (stage) {
 676         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 677         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 678         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 679         case MESA_SHADER_COMPUTE: return "Compute Shader";
 680         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 681         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 682         default:
 683                 return "Unknown shader";
 684         };
 685 }
 686
 687 static void
 688 generate_shader_stats(struct radv_device *device,
 689                       struct radv_shader_variant *variant,
 690                       gl_shader_stage stage,
 691                       struct _mesa_string_buffer *buf)
 692 {
 693         unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 694         struct ac_shader_config *conf;
 695         unsigned max_simd_waves;
 696         unsigned lds_per_wave = 0;
 697
 698         max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
 699
 700         conf = &variant->config;
 701
 702         if (stage == MESA_SHADER_FRAGMENT) {
 703                 lds_per_wave = conf->lds_size * lds_increment +
 704                                align(variant->info.fs.num_interp * 48,
 705                                      lds_increment);
 706         }
 707
 708         if (conf->num_sgprs)
 709                 max_simd_waves =
 710                         MIN2(max_simd_waves,
 711                              radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
 712
 713         if (conf->num_vgprs)
 714                 max_simd_waves =
 715                         MIN2(max_simd_waves,
 716                              RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
 717
 718         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 719          * that PS can use.
 720          */
 721         if (lds_per_wave)
 722                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 723
 724         if (stage == MESA_SHADER_FRAGMENT) {
 725                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 726                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 727                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 728                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 729         }
 730
 731         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 732                                    "SGPRS: %d\n"
 733                                    "VGPRS: %d\n"
 734                                    "Spilled SGPRs: %d\n"
 735                                    "Spilled VGPRs: %d\n"
 736                                    "PrivMem VGPRS: %d\n"
 737                                    "Code Size: %d bytes\n"
 738                                    "LDS: %d blocks\n"
 739                                    "Scratch: %d bytes per wave\n"
 740                                    "Max Waves: %d\n"
 741                                    "********************\n\n\n",
 742                                    conf->num_sgprs, conf->num_vgprs,
 743                                    conf->spilled_sgprs, conf->spilled_vgprs,
 744                                    variant->info.private_mem_vgprs, variant->code_size,
 745                                    conf->lds_size, conf->scratch_bytes_per_wave,
 746                                    max_simd_waves);
 747 }
 748
 749 void
 750 radv_shader_dump_stats(struct radv_device *device,
 751                        struct radv_shader_variant *variant,
 752                        gl_shader_stage stage,
 753                        FILE *file)
 754 {
 755         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 756
 757         generate_shader_stats(device, variant, stage, buf);
 758
 759         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 760         fprintf(file, "%s", buf->buf);
 761
 762         _mesa_string_buffer_destroy(buf);
 763 }
 764
 765 VkResult
 766 radv_GetShaderInfoAMD(VkDevice _device,
 767                       VkPipeline _pipeline,
 768                       VkShaderStageFlagBits shaderStage,
 769                       VkShaderInfoTypeAMD infoType,
 770                       size_t* pInfoSize,
 771                       void* pInfo)
 772 {
 773         RADV_FROM_HANDLE(radv_device, device, _device);
 774         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 775         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 776         struct radv_shader_variant *variant = pipeline->shaders[stage];
 777         struct _mesa_string_buffer *buf;
 778         VkResult result = VK_SUCCESS;
 779
 780         /* Spec doesn't indicate what to do if the stage is invalid, so just
 781          * return no info for this. */
 782         if (!variant)
 783                 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
 784
 785         switch (infoType) {
 786         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 787                 if (!pInfo) {
 788                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 789                 } else {
 790                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 791                         struct ac_shader_config *conf = &variant->config;
 792
 793                         VkShaderStatisticsInfoAMD statistics = {};
 794                         statistics.shaderStageMask = shaderStage;
 795                         statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
 796                         statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device);
 797                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 798
 799                         if (stage == MESA_SHADER_COMPUTE) {
 800                                 unsigned *local_size = variant->nir->info.cs.local_size;
 801                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 802
 803                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 804                                                                ceil((double)workgroup_size / statistics.numPhysicalVgprs);
 805
 806                                 statistics.computeWorkGroupSize[0] = local_size[0];
 807                                 statistics.computeWorkGroupSize[1] = local_size[1];
 808                                 statistics.computeWorkGroupSize[2] = local_size[2];
 809                         } else {
 810                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 811                         }
 812
 813                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 814                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 815                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 816                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 817                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 818
 819                         size_t size = *pInfoSize;
 820                         *pInfoSize = sizeof(statistics);
 821
 822                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 823
 824                         if (size < *pInfoSize)
 825                                 result = VK_INCOMPLETE;
 826                 }
 827
 828                 break;
 829         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 830                 buf = _mesa_string_buffer_create(NULL, 1024);
 831
 832                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 833                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 834                 generate_shader_stats(device, variant, stage, buf);
 835
 836                 /* Need to include the null terminator. */
 837                 size_t length = buf->length + 1;
 838
 839                 if (!pInfo) {
 840                         *pInfoSize = length;
 841                 } else {
 842                         size_t size = *pInfoSize;
 843                         *pInfoSize = length;
 844
 845                         memcpy(pInfo, buf->buf, MIN2(size, length));
 846
 847                         if (size < length)
 848                                 result = VK_INCOMPLETE;
 849                 }
 850
 851                 _mesa_string_buffer_destroy(buf);
 852                 break;
 853         default:
 854                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 855                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 856                 break;
 857         }
 858
 859         return result;
 860 }