src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "nir/nir.h"
  34 #include "nir/nir_builder.h"
  35 #include "spirv/nir_spirv.h"
  36
  37 #include <llvm-c/Core.h>
  38 #include <llvm-c/TargetMachine.h>
  39
  40 #include "sid.h"
  41 #include "gfx9d.h"
  42 #include "ac_binary.h"
  43 #include "ac_llvm_util.h"
  44 #include "ac_nir_to_llvm.h"
  45 #include "vk_format.h"
  46 #include "util/debug.h"
  47 #include "ac_exp_param.h"
  48
  49 #include "util/string_buffer.h"
  50
  51 static const struct nir_shader_compiler_options nir_options = {
  52         .vertex_id_zero_based = true,
  53         .lower_scmp = true,
  54         .lower_flrp32 = true,
  55         .lower_flrp64 = true,
  56         .lower_device_index_to_zero = true,
  57         .lower_fsat = true,
  58         .lower_fdiv = true,
  59         .lower_sub = true,
  60         .lower_pack_snorm_2x16 = true,
  61         .lower_pack_snorm_4x8 = true,
  62         .lower_pack_unorm_2x16 = true,
  63         .lower_pack_unorm_4x8 = true,
  64         .lower_unpack_snorm_2x16 = true,
  65         .lower_unpack_snorm_4x8 = true,
  66         .lower_unpack_unorm_2x16 = true,
  67         .lower_unpack_unorm_4x8 = true,
  68         .lower_extract_byte = true,
  69         .lower_extract_word = true,
  70         .lower_ffma = true,
  71         .lower_fpow = true,
  72         .vs_inputs_dual_locations = true,
  73         .max_unroll_iterations = 32
  74 };
  75
  76 VkResult radv_CreateShaderModule(
  77         VkDevice                                    _device,
  78         const VkShaderModuleCreateInfo*             pCreateInfo,
  79         const VkAllocationCallbacks*                pAllocator,
  80         VkShaderModule*                             pShaderModule)
  81 {
  82         RADV_FROM_HANDLE(radv_device, device, _device);
  83         struct radv_shader_module *module;
  84
  85         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  86         assert(pCreateInfo->flags == 0);
  87
  88         module = vk_alloc2(&device->alloc, pAllocator,
  89                              sizeof(*module) + pCreateInfo->codeSize, 8,
  90                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  91         if (module == NULL)
  92                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
  93
  94         module->nir = NULL;
  95         module->size = pCreateInfo->codeSize;
  96         memcpy(module->data, pCreateInfo->pCode, module->size);
  97
  98         _mesa_sha1_compute(module->data, module->size, module->sha1);
  99
 100         *pShaderModule = radv_shader_module_to_handle(module);
 101
 102         return VK_SUCCESS;
 103 }
 104
 105 void radv_DestroyShaderModule(
 106         VkDevice                                    _device,
 107         VkShaderModule                              _module,
 108         const VkAllocationCallbacks*                pAllocator)
 109 {
 110         RADV_FROM_HANDLE(radv_device, device, _device);
 111         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 112
 113         if (!module)
 114                 return;
 115
 116         vk_free2(&device->alloc, pAllocator, module);
 117 }
 118
 119 void
 120 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively)
 121 {
 122         bool progress;
 123
 124         do {
 125                 progress = false;
 126
 127                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 128                 NIR_PASS_V(shader, nir_lower_pack);
 129                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 130                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 131
 132                 NIR_PASS(progress, shader, nir_copy_prop);
 133                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 134                 NIR_PASS(progress, shader, nir_opt_dce);
 135                 if (nir_opt_trivial_continues(shader)) {
 136                         progress = true;
 137                         NIR_PASS(progress, shader, nir_copy_prop);
 138                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 139                         NIR_PASS(progress, shader, nir_opt_dce);
 140                 }
 141                 NIR_PASS(progress, shader, nir_opt_if);
 142                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 143                 NIR_PASS(progress, shader, nir_opt_cse);
 144                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 145                 NIR_PASS(progress, shader, nir_opt_algebraic);
 146                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 147                 NIR_PASS(progress, shader, nir_opt_undef);
 148                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 149                 if (shader->options->max_unroll_iterations) {
 150                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 151                 }
 152         } while (progress && !optimize_conservatively);
 153
 154         NIR_PASS(progress, shader, nir_opt_shrink_load);
 155         NIR_PASS(progress, shader, nir_opt_move_load_ubo);
 156 }
 157
 158 nir_shader *
 159 radv_shader_compile_to_nir(struct radv_device *device,
 160                            struct radv_shader_module *module,
 161                            const char *entrypoint_name,
 162                            gl_shader_stage stage,
 163                            const VkSpecializationInfo *spec_info,
 164                            const VkPipelineCreateFlags flags)
 165 {
 166         nir_shader *nir;
 167         nir_function *entry_point;
 168         if (module->nir) {
 169                 /* Some things such as our meta clear/blit code will give us a NIR
 170                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 171                  * and just use the NIR shader */
 172                 nir = module->nir;
 173                 nir->options = &nir_options;
 174                 nir_validate_shader(nir);
 175
 176                 assert(exec_list_length(&nir->functions) == 1);
 177                 struct exec_node *node = exec_list_get_head(&nir->functions);
 178                 entry_point = exec_node_data(nir_function, node, node);
 179         } else {
 180                 uint32_t *spirv = (uint32_t *) module->data;
 181                 assert(module->size % 4 == 0);
 182
 183                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 184                         radv_print_spirv(spirv, module->size, stderr);
 185
 186                 uint32_t num_spec_entries = 0;
 187                 struct nir_spirv_specialization *spec_entries = NULL;
 188                 if (spec_info && spec_info->mapEntryCount > 0) {
 189                         num_spec_entries = spec_info->mapEntryCount;
 190                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 191                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 192                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 193                                 const void *data = spec_info->pData + entry.offset;
 194                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 195
 196                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 197                                 if (spec_info->dataSize == 8)
 198                                         spec_entries[i].data64 = *(const uint64_t *)data;
 199                                 else
 200                                         spec_entries[i].data32 = *(const uint32_t *)data;
 201                         }
 202                 }
 203                 const struct spirv_to_nir_options spirv_options = {
 204                         .caps = {
 205                                 .device_group = true,
 206                                 .draw_parameters = true,
 207                                 .float64 = true,
 208                                 .image_read_without_format = true,
 209                                 .image_write_without_format = true,
 210                                 .tessellation = true,
 211                                 .int64 = true,
 212                                 .multiview = true,
 213                                 .subgroup_ballot = true,
 214                                 .subgroup_basic = true,
 215                                 .subgroup_quad = true,
 216                                 .subgroup_shuffle = true,
 217                                 .subgroup_vote = true,
 218                                 .variable_pointers = true,
 219                                 .gcn_shader = true,
 220                                 .trinary_minmax = true,
 221                                 .shader_viewport_index_layer = true,
 222                                 .descriptor_array_dynamic_indexing = true,
 223                                 .runtime_descriptor_array = true,
 224                         },
 225                 };
 226                 entry_point = spirv_to_nir(spirv, module->size / 4,
 227                                            spec_entries, num_spec_entries,
 228                                            stage, entrypoint_name,
 229                                            &spirv_options, &nir_options);
 230                 nir = entry_point->shader;
 231                 assert(nir->info.stage == stage);
 232                 nir_validate_shader(nir);
 233
 234                 free(spec_entries);
 235
 236                 /* We have to lower away local constant initializers right before we
 237                  * inline functions.  That way they get properly initialized at the top
 238                  * of the function and not at the top of its caller.
 239                  */
 240                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 241                 NIR_PASS_V(nir, nir_lower_returns);
 242                 NIR_PASS_V(nir, nir_inline_functions);
 243
 244                 /* Pick off the single entrypoint that we want */
 245                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 246                         if (func != entry_point)
 247                                 exec_node_remove(&func->node);
 248                 }
 249                 assert(exec_list_length(&nir->functions) == 1);
 250                 entry_point->name = ralloc_strdup(entry_point, "main");
 251
 252                 /* Make sure we lower constant initializers on output variables so that
 253                  * nir_remove_dead_variables below sees the corresponding stores
 254                  */
 255                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
 256
 257                 NIR_PASS_V(nir, nir_remove_dead_variables,
 258                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 259
 260                 /* Now that we've deleted all but the main function, we can go ahead and
 261                  * lower the rest of the constant initializers.
 262                  */
 263                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 264                 NIR_PASS_V(nir, nir_lower_system_values);
 265                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 266         }
 267
 268         /* Vulkan uses the separate-shader linking model */
 269         nir->info.separate_shader = true;
 270
 271         nir_shader_gather_info(nir, entry_point->impl);
 272
 273         static const nir_lower_tex_options tex_options = {
 274           .lower_txp = ~0,
 275         };
 276
 277         nir_lower_tex(nir, &tex_options);
 278
 279         nir_lower_vars_to_ssa(nir);
 280
 281         if (nir->info.stage == MESA_SHADER_VERTEX ||
 282             nir->info.stage == MESA_SHADER_GEOMETRY) {
 283                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 284                            nir_shader_get_entrypoint(nir), true, true);
 285         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
 286                    nir->info.stage == MESA_SHADER_FRAGMENT) {
 287                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 288                            nir_shader_get_entrypoint(nir), true, false);
 289         }
 290
 291         nir_split_var_copies(nir);
 292         nir_lower_var_copies(nir);
 293
 294         nir_lower_global_vars_to_local(nir);
 295         nir_remove_dead_variables(nir, nir_var_local);
 296         nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 297                         .subgroup_size = 64,
 298                         .ballot_bit_size = 64,
 299                         .lower_to_scalar = 1,
 300                         .lower_subgroup_masks = 1,
 301                         .lower_shuffle = 1,
 302                         .lower_shuffle_to_32bit = 1,
 303                         .lower_vote_eq_to_ballot = 1,
 304                 });
 305
 306         if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
 307                 radv_optimize_nir(nir, false);
 308
 309         /* Indirect lowering must be called after the radv_optimize_nir() loop
 310          * has been called at least once. Otherwise indirect lowering can
 311          * bloat the instruction count of the loop and cause it to be
 312          * considered too large for unrolling.
 313          */
 314         ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
 315         radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT);
 316
 317         return nir;
 318 }
 319
 320 void *
 321 radv_alloc_shader_memory(struct radv_device *device,
 322                          struct radv_shader_variant *shader)
 323 {
 324         mtx_lock(&device->shader_slab_mutex);
 325         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 326                 uint64_t offset = 0;
 327                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 328                         if (s->bo_offset - offset >= shader->code_size) {
 329                                 shader->bo = slab->bo;
 330                                 shader->bo_offset = offset;
 331                                 list_addtail(&shader->slab_list, &s->slab_list);
 332                                 mtx_unlock(&device->shader_slab_mutex);
 333                                 return slab->ptr + offset;
 334                         }
 335                         offset = align_u64(s->bo_offset + s->code_size, 256);
 336                 }
 337                 if (slab->size - offset >= shader->code_size) {
 338                         shader->bo = slab->bo;
 339                         shader->bo_offset = offset;
 340                         list_addtail(&shader->slab_list, &slab->shaders);
 341                         mtx_unlock(&device->shader_slab_mutex);
 342                         return slab->ptr + offset;
 343                 }
 344         }
 345
 346         mtx_unlock(&device->shader_slab_mutex);
 347         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 348
 349         slab->size = 256 * 1024;
 350         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 351                                              RADEON_DOMAIN_VRAM,
 352                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 353                                              device->physical_device->cpdma_prefetch_writes_memory ?
 354                                                      0 : RADEON_FLAG_READ_ONLY);
 355         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 356         list_inithead(&slab->shaders);
 357
 358         mtx_lock(&device->shader_slab_mutex);
 359         list_add(&slab->slabs, &device->shader_slabs);
 360
 361         shader->bo = slab->bo;
 362         shader->bo_offset = 0;
 363         list_add(&shader->slab_list, &slab->shaders);
 364         mtx_unlock(&device->shader_slab_mutex);
 365         return slab->ptr;
 366 }
 367
 368 void
 369 radv_destroy_shader_slabs(struct radv_device *device)
 370 {
 371         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 372                 device->ws->buffer_destroy(slab->bo);
 373                 free(slab);
 374         }
 375         mtx_destroy(&device->shader_slab_mutex);
 376 }
 377
 378 static void
 379 radv_fill_shader_variant(struct radv_device *device,
 380                          struct radv_shader_variant *variant,
 381                          struct ac_shader_binary *binary,
 382                          gl_shader_stage stage)
 383 {
 384         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 385         struct radv_shader_info *info = &variant->info.info;
 386         unsigned vgpr_comp_cnt = 0;
 387
 388         variant->code_size = binary->code_size;
 389         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 390                          S_00B12C_SCRATCH_EN(scratch_enabled);
 391
 392         variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 393                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 394                 S_00B848_DX10_CLAMP(1) |
 395                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 396
 397         switch (stage) {
 398         case MESA_SHADER_TESS_EVAL:
 399                 vgpr_comp_cnt = 3;
 400                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 401                 break;
 402         case MESA_SHADER_TESS_CTRL:
 403                 if (device->physical_device->rad_info.chip_class >= GFX9) {
 404                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 405                 } else {
 406                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 407                 }
 408                 break;
 409         case MESA_SHADER_VERTEX:
 410         case MESA_SHADER_GEOMETRY:
 411                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 412                 break;
 413         case MESA_SHADER_FRAGMENT:
 414                 break;
 415         case MESA_SHADER_COMPUTE:
 416                 variant->rsrc2 |=
 417                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 418                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 419                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 420                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 421                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 422                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 423                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 424                 break;
 425         default:
 426                 unreachable("unsupported shader type");
 427                 break;
 428         }
 429
 430         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 431             stage == MESA_SHADER_GEOMETRY) {
 432                 unsigned es_type = variant->info.gs.es_type;
 433                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 434
 435                 if (es_type == MESA_SHADER_VERTEX) {
 436                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 437                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 438                         es_vgpr_comp_cnt = 3;
 439                 } else {
 440                         unreachable("invalid shader ES type");
 441                 }
 442
 443                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 444                  * VGPR[0:4] are always loaded.
 445                  */
 446                 if (info->uses_invocation_id) {
 447                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 448                 } else if (info->uses_prim_id) {
 449                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 450                 } else if (variant->info.gs.vertices_in >= 3) {
 451                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 452                 } else {
 453                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 454                 }
 455
 456                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 457                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 458                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 459         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 460                    stage == MESA_SHADER_TESS_CTRL) {
 461                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 462         } else {
 463                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 464         }
 465
 466         void *ptr = radv_alloc_shader_memory(device, variant);
 467         memcpy(ptr, binary->code, binary->code_size);
 468 }
 469
 470 static struct radv_shader_variant *
 471 shader_variant_create(struct radv_device *device,
 472                       struct radv_shader_module *module,
 473                       struct nir_shader * const *shaders,
 474                       int shader_count,
 475                       gl_shader_stage stage,
 476                       struct radv_nir_compiler_options *options,
 477                       bool gs_copy_shader,
 478                       void **code_out,
 479                       unsigned *code_size_out)
 480 {
 481         enum radeon_family chip_family = device->physical_device->rad_info.family;
 482         enum ac_target_machine_options tm_options = 0;
 483         struct radv_shader_variant *variant;
 484         struct ac_shader_binary binary;
 485         LLVMTargetMachineRef tm;
 486
 487         variant = calloc(1, sizeof(struct radv_shader_variant));
 488         if (!variant)
 489                 return NULL;
 490
 491         options->family = chip_family;
 492         options->chip_class = device->physical_device->rad_info.chip_class;
 493         options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
 494         options->dump_preoptir = options->dump_shader &&
 495                                  device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
 496         options->record_llvm_ir = device->keep_shader_info;
 497         options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
 498         options->address32_hi = device->physical_device->rad_info.address32_hi;
 499
 500         if (options->supports_spill)
 501                 tm_options |= AC_TM_SUPPORTS_SPILL;
 502         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 503                 tm_options |= AC_TM_SISCHED;
 504         tm = ac_create_target_machine(chip_family, tm_options, NULL);
 505
 506         if (gs_copy_shader) {
 507                 assert(shader_count == 1);
 508                 radv_compile_gs_copy_shader(tm, *shaders, &binary,
 509                                             &variant->config, &variant->info,
 510                                             options);
 511         } else {
 512                 radv_compile_nir_shader(tm, &binary, &variant->config,
 513                                         &variant->info, shaders, shader_count,
 514                                         options);
 515         }
 516
 517         LLVMDisposeTargetMachine(tm);
 518
 519         radv_fill_shader_variant(device, variant, &binary, stage);
 520
 521         if (code_out) {
 522                 *code_out = binary.code;
 523                 *code_size_out = binary.code_size;
 524         } else
 525                 free(binary.code);
 526         free(binary.config);
 527         free(binary.rodata);
 528         free(binary.global_symbol_offsets);
 529         free(binary.relocs);
 530         variant->ref_count = 1;
 531
 532         if (device->keep_shader_info) {
 533                 variant->disasm_string = binary.disasm_string;
 534                 variant->llvm_ir_string = binary.llvm_ir_string;
 535                 if (!gs_copy_shader && !module->nir) {
 536                         variant->nir = *shaders;
 537                         variant->spirv = (uint32_t *)module->data;
 538                         variant->spirv_size = module->size;
 539                 }
 540         } else {
 541                 free(binary.disasm_string);
 542         }
 543
 544         return variant;
 545 }
 546
 547 struct radv_shader_variant *
 548 radv_shader_variant_create(struct radv_device *device,
 549                            struct radv_shader_module *module,
 550                            struct nir_shader *const *shaders,
 551                            int shader_count,
 552                            struct radv_pipeline_layout *layout,
 553                            const struct radv_shader_variant_key *key,
 554                            void **code_out,
 555                            unsigned *code_size_out)
 556 {
 557         struct radv_nir_compiler_options options = {0};
 558
 559         options.layout = layout;
 560         if (key)
 561                 options.key = *key;
 562
 563         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 564         options.supports_spill = true;
 565
 566         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 567                                      &options, false, code_out, code_size_out);
 568 }
 569
 570 struct radv_shader_variant *
 571 radv_create_gs_copy_shader(struct radv_device *device,
 572                            struct nir_shader *shader,
 573                            void **code_out,
 574                            unsigned *code_size_out,
 575                            bool multiview)
 576 {
 577         struct radv_nir_compiler_options options = {0};
 578
 579         options.key.has_multiview_view_index = multiview;
 580
 581         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 582                                      &options, true, code_out, code_size_out);
 583 }
 584
 585 void
 586 radv_shader_variant_destroy(struct radv_device *device,
 587                             struct radv_shader_variant *variant)
 588 {
 589         if (!p_atomic_dec_zero(&variant->ref_count))
 590                 return;
 591
 592         mtx_lock(&device->shader_slab_mutex);
 593         list_del(&variant->slab_list);
 594         mtx_unlock(&device->shader_slab_mutex);
 595
 596         ralloc_free(variant->nir);
 597         free(variant->disasm_string);
 598         free(variant->llvm_ir_string);
 599         free(variant);
 600 }
 601
 602 const char *
 603 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 604 {
 605         switch (stage) {
 606         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 607         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 608         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 609         case MESA_SHADER_COMPUTE: return "Compute Shader";
 610         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 611         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 612         default:
 613                 return "Unknown shader";
 614         };
 615 }
 616
 617 static void
 618 generate_shader_stats(struct radv_device *device,
 619                       struct radv_shader_variant *variant,
 620                       gl_shader_stage stage,
 621                       struct _mesa_string_buffer *buf)
 622 {
 623         unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 624         struct ac_shader_config *conf;
 625         unsigned max_simd_waves;
 626         unsigned lds_per_wave = 0;
 627
 628         max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
 629
 630         conf = &variant->config;
 631
 632         if (stage == MESA_SHADER_FRAGMENT) {
 633                 lds_per_wave = conf->lds_size * lds_increment +
 634                                align(variant->info.fs.num_interp * 48,
 635                                      lds_increment);
 636         }
 637
 638         if (conf->num_sgprs)
 639                 max_simd_waves =
 640                         MIN2(max_simd_waves,
 641                              radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
 642
 643         if (conf->num_vgprs)
 644                 max_simd_waves =
 645                         MIN2(max_simd_waves,
 646                              RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
 647
 648         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 649          * that PS can use.
 650          */
 651         if (lds_per_wave)
 652                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 653
 654         if (stage == MESA_SHADER_FRAGMENT) {
 655                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 656                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 657                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 658                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 659         }
 660
 661         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 662                                    "SGPRS: %d\n"
 663                                    "VGPRS: %d\n"
 664                                    "Spilled SGPRs: %d\n"
 665                                    "Spilled VGPRs: %d\n"
 666                                    "PrivMem VGPRS: %d\n"
 667                                    "Code Size: %d bytes\n"
 668                                    "LDS: %d blocks\n"
 669                                    "Scratch: %d bytes per wave\n"
 670                                    "Max Waves: %d\n"
 671                                    "********************\n\n\n",
 672                                    conf->num_sgprs, conf->num_vgprs,
 673                                    conf->spilled_sgprs, conf->spilled_vgprs,
 674                                    variant->info.private_mem_vgprs, variant->code_size,
 675                                    conf->lds_size, conf->scratch_bytes_per_wave,
 676                                    max_simd_waves);
 677 }
 678
 679 void
 680 radv_shader_dump_stats(struct radv_device *device,
 681                        struct radv_shader_variant *variant,
 682                        gl_shader_stage stage,
 683                        FILE *file)
 684 {
 685         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 686
 687         generate_shader_stats(device, variant, stage, buf);
 688
 689         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 690         fprintf(file, "%s", buf->buf);
 691
 692         _mesa_string_buffer_destroy(buf);
 693 }
 694
 695 VkResult
 696 radv_GetShaderInfoAMD(VkDevice _device,
 697                       VkPipeline _pipeline,
 698                       VkShaderStageFlagBits shaderStage,
 699                       VkShaderInfoTypeAMD infoType,
 700                       size_t* pInfoSize,
 701                       void* pInfo)
 702 {
 703         RADV_FROM_HANDLE(radv_device, device, _device);
 704         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 705         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 706         struct radv_shader_variant *variant = pipeline->shaders[stage];
 707         struct _mesa_string_buffer *buf;
 708         VkResult result = VK_SUCCESS;
 709
 710         /* Spec doesn't indicate what to do if the stage is invalid, so just
 711          * return no info for this. */
 712         if (!variant)
 713                 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
 714
 715         switch (infoType) {
 716         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 717                 if (!pInfo) {
 718                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 719                 } else {
 720                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 721                         struct ac_shader_config *conf = &variant->config;
 722
 723                         VkShaderStatisticsInfoAMD statistics = {};
 724                         statistics.shaderStageMask = shaderStage;
 725                         statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
 726                         statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device);
 727                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 728
 729                         if (stage == MESA_SHADER_COMPUTE) {
 730                                 unsigned *local_size = variant->nir->info.cs.local_size;
 731                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 732
 733                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 734                                                                ceil(workgroup_size / statistics.numPhysicalVgprs);
 735
 736                                 statistics.computeWorkGroupSize[0] = local_size[0];
 737                                 statistics.computeWorkGroupSize[1] = local_size[1];
 738                                 statistics.computeWorkGroupSize[2] = local_size[2];
 739                         } else {
 740                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 741                         }
 742
 743                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 744                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 745                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 746                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 747                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 748
 749                         size_t size = *pInfoSize;
 750                         *pInfoSize = sizeof(statistics);
 751
 752                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 753
 754                         if (size < *pInfoSize)
 755                                 result = VK_INCOMPLETE;
 756                 }
 757
 758                 break;
 759         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 760                 buf = _mesa_string_buffer_create(NULL, 1024);
 761
 762                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 763                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 764                 generate_shader_stats(device, variant, stage, buf);
 765
 766                 /* Need to include the null terminator. */
 767                 size_t length = buf->length + 1;
 768
 769                 if (!pInfo) {
 770                         *pInfoSize = length;
 771                 } else {
 772                         size_t size = *pInfoSize;
 773                         *pInfoSize = length;
 774
 775                         memcpy(pInfo, buf->buf, MIN2(size, length));
 776
 777                         if (size < length)
 778                                 result = VK_INCOMPLETE;
 779                 }
 780
 781                 _mesa_string_buffer_destroy(buf);
 782                 break;
 783         default:
 784                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 785                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 786                 break;
 787         }
 788
 789         return result;
 790 }