2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
50 #include "util/string_buffer.h"
52 static const struct nir_shader_compiler_options nir_options
= {
53 .vertex_id_zero_based
= true,
58 .lower_device_index_to_zero
= true,
61 .lower_bitfield_insert_to_bitfield_select
= true,
62 .lower_bitfield_extract
= true,
64 .lower_pack_snorm_2x16
= true,
65 .lower_pack_snorm_4x8
= true,
66 .lower_pack_unorm_2x16
= true,
67 .lower_pack_unorm_4x8
= true,
68 .lower_unpack_snorm_2x16
= true,
69 .lower_unpack_snorm_4x8
= true,
70 .lower_unpack_unorm_2x16
= true,
71 .lower_unpack_unorm_4x8
= true,
72 .lower_extract_byte
= true,
73 .lower_extract_word
= true,
76 .lower_mul_2x32_64
= true,
78 .max_unroll_iterations
= 32
81 VkResult
radv_CreateShaderModule(
83 const VkShaderModuleCreateInfo
* pCreateInfo
,
84 const VkAllocationCallbacks
* pAllocator
,
85 VkShaderModule
* pShaderModule
)
87 RADV_FROM_HANDLE(radv_device
, device
, _device
);
88 struct radv_shader_module
*module
;
90 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
91 assert(pCreateInfo
->flags
== 0);
93 module
= vk_alloc2(&device
->alloc
, pAllocator
,
94 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
95 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
97 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
100 module
->size
= pCreateInfo
->codeSize
;
101 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
103 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
105 *pShaderModule
= radv_shader_module_to_handle(module
);
110 void radv_DestroyShaderModule(
112 VkShaderModule _module
,
113 const VkAllocationCallbacks
* pAllocator
)
115 RADV_FROM_HANDLE(radv_device
, device
, _device
);
116 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
121 vk_free2(&device
->alloc
, pAllocator
, module
);
125 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
129 unsigned lower_flrp
=
130 (shader
->options
->lower_flrp16
? 16 : 0) |
131 (shader
->options
->lower_flrp32
? 32 : 0) |
132 (shader
->options
->lower_flrp64
? 64 : 0);
137 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_function_temp
);
138 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
140 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
141 NIR_PASS_V(shader
, nir_lower_pack
);
144 /* Only run this pass in the first call to
145 * radv_optimize_nir. Later calls assume that we've
146 * lowered away any copy_deref instructions and we
147 * don't want to introduce any more.
149 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
152 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
153 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
155 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
, NULL
);
156 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
158 NIR_PASS(progress
, shader
, nir_copy_prop
);
159 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
160 NIR_PASS(progress
, shader
, nir_opt_dce
);
161 if (nir_opt_trivial_continues(shader
)) {
163 NIR_PASS(progress
, shader
, nir_copy_prop
);
164 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
165 NIR_PASS(progress
, shader
, nir_opt_dce
);
167 NIR_PASS(progress
, shader
, nir_opt_if
, true);
168 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
169 NIR_PASS(progress
, shader
, nir_opt_cse
);
170 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
171 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
172 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
174 if (lower_flrp
!= 0) {
175 bool lower_flrp_progress
= false;
176 NIR_PASS(lower_flrp_progress
,
180 false /* always_precise */,
181 shader
->options
->lower_ffma
);
182 if (lower_flrp_progress
) {
183 NIR_PASS(progress
, shader
,
184 nir_opt_constant_folding
);
188 /* Nothing should rematerialize any flrps, so we only
189 * need to do this lowering once.
194 NIR_PASS(progress
, shader
, nir_opt_undef
);
195 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
196 if (shader
->options
->max_unroll_iterations
) {
197 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
199 } while (progress
&& !optimize_conservatively
);
201 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
202 NIR_PASS(progress
, shader
, nir_opt_move_load_ubo
);
206 radv_shader_compile_to_nir(struct radv_device
*device
,
207 struct radv_shader_module
*module
,
208 const char *entrypoint_name
,
209 gl_shader_stage stage
,
210 const VkSpecializationInfo
*spec_info
,
211 const VkPipelineCreateFlags flags
,
212 const struct radv_pipeline_layout
*layout
)
216 /* Some things such as our meta clear/blit code will give us a NIR
217 * shader directly. In that case, we just ignore the SPIR-V entirely
218 * and just use the NIR shader */
220 nir
->options
= &nir_options
;
221 nir_validate_shader(nir
, "in internal shader");
223 assert(exec_list_length(&nir
->functions
) == 1);
225 uint32_t *spirv
= (uint32_t *) module
->data
;
226 assert(module
->size
% 4 == 0);
228 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
229 radv_print_spirv(spirv
, module
->size
, stderr
);
231 uint32_t num_spec_entries
= 0;
232 struct nir_spirv_specialization
*spec_entries
= NULL
;
233 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
234 num_spec_entries
= spec_info
->mapEntryCount
;
235 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
236 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
237 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
238 const void *data
= spec_info
->pData
+ entry
.offset
;
239 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
241 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
242 if (spec_info
->dataSize
== 8)
243 spec_entries
[i
].data64
= *(const uint64_t *)data
;
245 spec_entries
[i
].data32
= *(const uint32_t *)data
;
248 const struct spirv_to_nir_options spirv_options
= {
249 .lower_ubo_ssbo_access_to_offsets
= true,
251 .amd_gcn_shader
= true,
252 .amd_shader_ballot
= device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
,
253 .amd_trinary_minmax
= true,
254 .derivative_group
= true,
255 .descriptor_array_dynamic_indexing
= true,
256 .descriptor_array_non_uniform_indexing
= true,
257 .descriptor_indexing
= true,
258 .device_group
= true,
259 .draw_parameters
= true,
262 .geometry_streams
= true,
263 .image_read_without_format
= true,
264 .image_write_without_format
= true,
268 .int64_atomics
= true,
270 .physical_storage_buffer_address
= true,
271 .runtime_descriptor_array
= true,
272 .shader_viewport_index_layer
= true,
273 .stencil_export
= true,
274 .storage_8bit
= true,
275 .storage_16bit
= true,
276 .storage_image_ms
= true,
277 .subgroup_arithmetic
= true,
278 .subgroup_ballot
= true,
279 .subgroup_basic
= true,
280 .subgroup_quad
= true,
281 .subgroup_shuffle
= true,
282 .subgroup_vote
= true,
283 .tessellation
= true,
284 .transform_feedback
= true,
285 .variable_pointers
= true,
287 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
288 .ssbo_addr_format
= nir_address_format_32bit_index_offset
,
289 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
290 .push_const_addr_format
= nir_address_format_logical
,
291 .shared_addr_format
= nir_address_format_32bit_offset
,
293 nir
= spirv_to_nir(spirv
, module
->size
/ 4,
294 spec_entries
, num_spec_entries
,
295 stage
, entrypoint_name
,
296 &spirv_options
, &nir_options
);
297 assert(nir
->info
.stage
== stage
);
298 nir_validate_shader(nir
, "after spirv_to_nir");
302 /* We have to lower away local constant initializers right before we
303 * inline functions. That way they get properly initialized at the top
304 * of the function and not at the top of its caller.
306 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
307 NIR_PASS_V(nir
, nir_lower_returns
);
308 NIR_PASS_V(nir
, nir_inline_functions
);
309 NIR_PASS_V(nir
, nir_opt_deref
);
311 /* Pick off the single entrypoint that we want */
312 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
313 if (func
->is_entrypoint
)
314 func
->name
= ralloc_strdup(func
, "main");
316 exec_node_remove(&func
->node
);
318 assert(exec_list_length(&nir
->functions
) == 1);
320 /* Make sure we lower constant initializers on output variables so that
321 * nir_remove_dead_variables below sees the corresponding stores
323 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
325 /* Now that we've deleted all but the main function, we can go ahead and
326 * lower the rest of the constant initializers.
328 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
330 /* Split member structs. We do this before lower_io_to_temporaries so that
331 * it doesn't lower system values to temporaries by accident.
333 NIR_PASS_V(nir
, nir_split_var_copies
);
334 NIR_PASS_V(nir
, nir_split_per_member_structs
);
336 NIR_PASS_V(nir
, nir_remove_dead_variables
,
337 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
339 NIR_PASS_V(nir
, nir_lower_system_values
);
340 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
341 NIR_PASS_V(nir
, radv_nir_lower_ycbcr_textures
, layout
);
344 /* Vulkan uses the separate-shader linking model */
345 nir
->info
.separate_shader
= true;
347 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
349 static const nir_lower_tex_options tex_options
= {
351 .lower_tg4_offsets
= true,
354 nir_lower_tex(nir
, &tex_options
);
356 nir_lower_vars_to_ssa(nir
);
358 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
359 nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
360 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
361 nir_shader_get_entrypoint(nir
), true, true);
362 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
363 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
364 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
365 nir_shader_get_entrypoint(nir
), true, false);
368 nir_split_var_copies(nir
);
370 nir_lower_global_vars_to_local(nir
);
371 nir_remove_dead_variables(nir
, nir_var_function_temp
);
372 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
374 .ballot_bit_size
= 64,
375 .lower_to_scalar
= 1,
376 .lower_subgroup_masks
= 1,
378 .lower_shuffle_to_32bit
= 1,
379 .lower_vote_eq_to_ballot
= 1,
382 nir_lower_load_const_to_scalar(nir
);
384 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
385 radv_optimize_nir(nir
, false, true);
387 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
388 * to remove any copies introduced by nir_opt_find_array_copies().
390 nir_lower_var_copies(nir
);
392 /* Indirect lowering must be called after the radv_optimize_nir() loop
393 * has been called at least once. Otherwise indirect lowering can
394 * bloat the instruction count of the loop and cause it to be
395 * considered too large for unrolling.
397 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
398 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
404 radv_alloc_shader_memory(struct radv_device
*device
,
405 struct radv_shader_variant
*shader
)
407 mtx_lock(&device
->shader_slab_mutex
);
408 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
410 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
411 if (s
->bo_offset
- offset
>= shader
->code_size
) {
412 shader
->bo
= slab
->bo
;
413 shader
->bo_offset
= offset
;
414 list_addtail(&shader
->slab_list
, &s
->slab_list
);
415 mtx_unlock(&device
->shader_slab_mutex
);
416 return slab
->ptr
+ offset
;
418 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
420 if (slab
->size
- offset
>= shader
->code_size
) {
421 shader
->bo
= slab
->bo
;
422 shader
->bo_offset
= offset
;
423 list_addtail(&shader
->slab_list
, &slab
->shaders
);
424 mtx_unlock(&device
->shader_slab_mutex
);
425 return slab
->ptr
+ offset
;
429 mtx_unlock(&device
->shader_slab_mutex
);
430 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
432 slab
->size
= 256 * 1024;
433 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
435 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
436 (device
->physical_device
->cpdma_prefetch_writes_memory
?
437 0 : RADEON_FLAG_READ_ONLY
),
438 RADV_BO_PRIORITY_SHADER
);
439 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
440 list_inithead(&slab
->shaders
);
442 mtx_lock(&device
->shader_slab_mutex
);
443 list_add(&slab
->slabs
, &device
->shader_slabs
);
445 shader
->bo
= slab
->bo
;
446 shader
->bo_offset
= 0;
447 list_add(&shader
->slab_list
, &slab
->shaders
);
448 mtx_unlock(&device
->shader_slab_mutex
);
453 radv_destroy_shader_slabs(struct radv_device
*device
)
455 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
456 device
->ws
->buffer_destroy(slab
->bo
);
459 mtx_destroy(&device
->shader_slab_mutex
);
462 /* For the UMR disassembler. */
463 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
464 #define DEBUGGER_NUM_MARKERS 5
467 radv_get_shader_binary_size(struct ac_shader_binary
*binary
)
469 return binary
->code_size
+ DEBUGGER_NUM_MARKERS
* 4;
473 radv_fill_shader_variant(struct radv_device
*device
,
474 struct radv_shader_variant
*variant
,
475 struct radv_nir_compiler_options
*options
,
476 struct ac_shader_binary
*binary
,
477 gl_shader_stage stage
)
479 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
480 struct radv_shader_info
*info
= &variant
->info
.info
;
481 unsigned vgpr_comp_cnt
= 0;
483 variant
->code_size
= radv_get_shader_binary_size(binary
);
484 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
485 S_00B12C_USER_SGPR_MSB(variant
->info
.num_user_sgprs
>> 5) |
486 S_00B12C_SCRATCH_EN(scratch_enabled
) |
487 S_00B12C_SO_BASE0_EN(!!info
->so
.strides
[0]) |
488 S_00B12C_SO_BASE1_EN(!!info
->so
.strides
[1]) |
489 S_00B12C_SO_BASE2_EN(!!info
->so
.strides
[2]) |
490 S_00B12C_SO_BASE3_EN(!!info
->so
.strides
[3]) |
491 S_00B12C_SO_EN(!!info
->so
.num_outputs
);
493 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
494 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
495 S_00B848_DX10_CLAMP(1) |
496 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
499 case MESA_SHADER_TESS_EVAL
:
500 if (options
->key
.tes
.as_es
) {
501 assert(device
->physical_device
->rad_info
.chip_class
<= GFX8
);
502 vgpr_comp_cnt
= info
->uses_prim_id
? 3 : 2;
504 bool enable_prim_id
= options
->key
.tes
.export_prim_id
|| info
->uses_prim_id
;
505 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
507 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
509 case MESA_SHADER_TESS_CTRL
:
510 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
511 /* We need at least 2 components for LS.
512 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
513 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
515 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 2 : 1;
517 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
520 case MESA_SHADER_VERTEX
:
521 if (variant
->info
.vs
.as_ls
) {
522 assert(device
->physical_device
->rad_info
.chip_class
<= GFX8
);
523 /* We need at least 2 components for LS.
524 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
525 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
527 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 2 : 1;
528 } else if (variant
->info
.vs
.as_es
) {
529 assert(device
->physical_device
->rad_info
.chip_class
<= GFX8
);
530 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
531 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 1 : 0;
533 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
534 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
535 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
537 if (options
->key
.vs
.export_prim_id
) {
539 } else if (info
->vs
.needs_instance_id
) {
546 case MESA_SHADER_FRAGMENT
:
547 case MESA_SHADER_GEOMETRY
:
549 case MESA_SHADER_COMPUTE
:
551 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
552 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
553 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
554 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
555 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
556 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
557 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
560 unreachable("unsupported shader type");
564 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
565 stage
== MESA_SHADER_GEOMETRY
) {
566 unsigned es_type
= variant
->info
.gs
.es_type
;
567 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
569 if (es_type
== MESA_SHADER_VERTEX
) {
570 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
571 es_vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 1 : 0;
572 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
573 es_vgpr_comp_cnt
= info
->uses_prim_id
? 3 : 2;
575 unreachable("invalid shader ES type");
578 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
579 * VGPR[0:4] are always loaded.
581 if (info
->uses_invocation_id
) {
582 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
583 } else if (info
->uses_prim_id
) {
584 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
585 } else if (variant
->info
.gs
.vertices_in
>= 3) {
586 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
588 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
591 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
592 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
593 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
594 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
595 stage
== MESA_SHADER_TESS_CTRL
) {
596 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
598 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
601 void *ptr
= radv_alloc_shader_memory(device
, variant
);
602 memcpy(ptr
, binary
->code
, binary
->code_size
);
604 /* Add end-of-code markers for the UMR disassembler. */
605 uint32_t *ptr32
= (uint32_t *)ptr
+ binary
->code_size
/ 4;
606 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
607 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
611 static void radv_init_llvm_target()
613 LLVMInitializeAMDGPUTargetInfo();
614 LLVMInitializeAMDGPUTarget();
615 LLVMInitializeAMDGPUTargetMC();
616 LLVMInitializeAMDGPUAsmPrinter();
618 /* For inline assembly. */
619 LLVMInitializeAMDGPUAsmParser();
621 /* Workaround for bug in llvm 4.0 that causes image intrinsics
623 * https://reviews.llvm.org/D26348
625 * Workaround for bug in llvm that causes the GPU to hang in presence
626 * of nested loops because there is an exec mask issue. The proper
627 * solution is to fix LLVM but this might require a bunch of work.
628 * https://bugs.llvm.org/show_bug.cgi?id=37744
630 * "mesa" is the prefix for error messages.
632 if (HAVE_LLVM
>= 0x0800) {
633 const char *argv
[2] = { "mesa", "-simplifycfg-sink-common=false" };
634 LLVMParseCommandLineOptions(2, argv
, NULL
);
637 const char *argv
[3] = { "mesa", "-simplifycfg-sink-common=false",
638 "-amdgpu-skip-threshold=1" };
639 LLVMParseCommandLineOptions(3, argv
, NULL
);
643 static once_flag radv_init_llvm_target_once_flag
= ONCE_FLAG_INIT
;
645 static void radv_init_llvm_once(void)
647 call_once(&radv_init_llvm_target_once_flag
, radv_init_llvm_target
);
650 static struct radv_shader_variant
*
651 shader_variant_create(struct radv_device
*device
,
652 struct radv_shader_module
*module
,
653 struct nir_shader
* const *shaders
,
655 gl_shader_stage stage
,
656 struct radv_nir_compiler_options
*options
,
659 unsigned *code_size_out
)
661 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
662 enum ac_target_machine_options tm_options
= 0;
663 struct radv_shader_variant
*variant
;
664 struct ac_shader_binary binary
;
665 struct ac_llvm_compiler ac_llvm
;
666 bool thread_compiler
;
667 variant
= calloc(1, sizeof(struct radv_shader_variant
));
671 options
->family
= chip_family
;
672 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
673 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
674 options
->dump_preoptir
= options
->dump_shader
&&
675 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
676 options
->record_llvm_ir
= device
->keep_shader_info
;
677 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
678 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
679 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
681 if (options
->supports_spill
)
682 tm_options
|= AC_TM_SUPPORTS_SPILL
;
683 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
684 tm_options
|= AC_TM_SISCHED
;
685 if (options
->check_ir
)
686 tm_options
|= AC_TM_CHECK_IR
;
687 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_LOAD_STORE_OPT
)
688 tm_options
|= AC_TM_NO_LOAD_STORE_OPT
;
690 thread_compiler
= !(device
->instance
->debug_flags
& RADV_DEBUG_NOTHREADLLVM
);
691 radv_init_llvm_once();
692 radv_init_llvm_compiler(&ac_llvm
,
694 chip_family
, tm_options
);
695 if (gs_copy_shader
) {
696 assert(shader_count
== 1);
697 radv_compile_gs_copy_shader(&ac_llvm
, *shaders
, &binary
,
698 &variant
->config
, &variant
->info
,
701 radv_compile_nir_shader(&ac_llvm
, &binary
, &variant
->config
,
702 &variant
->info
, shaders
, shader_count
,
706 radv_destroy_llvm_compiler(&ac_llvm
, thread_compiler
);
708 radv_fill_shader_variant(device
, variant
, options
, &binary
, stage
);
711 *code_out
= binary
.code
;
712 *code_size_out
= binary
.code_size
;
717 free(binary
.global_symbol_offsets
);
719 variant
->ref_count
= 1;
721 if (device
->keep_shader_info
) {
722 variant
->disasm_string
= binary
.disasm_string
;
723 variant
->llvm_ir_string
= binary
.llvm_ir_string
;
724 if (!gs_copy_shader
&& !module
->nir
) {
725 variant
->nir
= *shaders
;
726 variant
->spirv
= (uint32_t *)module
->data
;
727 variant
->spirv_size
= module
->size
;
730 free(binary
.disasm_string
);
736 struct radv_shader_variant
*
737 radv_shader_variant_create(struct radv_device
*device
,
738 struct radv_shader_module
*module
,
739 struct nir_shader
*const *shaders
,
741 struct radv_pipeline_layout
*layout
,
742 const struct radv_shader_variant_key
*key
,
744 unsigned *code_size_out
)
746 struct radv_nir_compiler_options options
= {0};
748 options
.layout
= layout
;
752 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
753 options
.supports_spill
= true;
755 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
756 &options
, false, code_out
, code_size_out
);
759 struct radv_shader_variant
*
760 radv_create_gs_copy_shader(struct radv_device
*device
,
761 struct nir_shader
*shader
,
763 unsigned *code_size_out
,
766 struct radv_nir_compiler_options options
= {0};
768 options
.key
.has_multiview_view_index
= multiview
;
770 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
771 &options
, true, code_out
, code_size_out
);
775 radv_shader_variant_destroy(struct radv_device
*device
,
776 struct radv_shader_variant
*variant
)
778 if (!p_atomic_dec_zero(&variant
->ref_count
))
781 mtx_lock(&device
->shader_slab_mutex
);
782 list_del(&variant
->slab_list
);
783 mtx_unlock(&device
->shader_slab_mutex
);
785 ralloc_free(variant
->nir
);
786 free(variant
->disasm_string
);
787 free(variant
->llvm_ir_string
);
792 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
795 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
796 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
797 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
798 case MESA_SHADER_COMPUTE
: return "Compute Shader";
799 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
800 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
802 return "Unknown shader";
807 generate_shader_stats(struct radv_device
*device
,
808 struct radv_shader_variant
*variant
,
809 gl_shader_stage stage
,
810 struct _mesa_string_buffer
*buf
)
812 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
813 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
814 struct ac_shader_config
*conf
;
815 unsigned max_simd_waves
;
816 unsigned lds_per_wave
= 0;
818 max_simd_waves
= ac_get_max_simd_waves(device
->physical_device
->rad_info
.family
);
820 conf
= &variant
->config
;
822 if (stage
== MESA_SHADER_FRAGMENT
) {
823 lds_per_wave
= conf
->lds_size
* lds_increment
+
824 align(variant
->info
.fs
.num_interp
* 48,
826 } else if (stage
== MESA_SHADER_COMPUTE
) {
827 unsigned max_workgroup_size
=
828 radv_nir_get_max_workgroup_size(chip_class
, variant
->nir
);
829 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
830 DIV_ROUND_UP(max_workgroup_size
, 64);
836 ac_get_num_physical_sgprs(chip_class
) / conf
->num_sgprs
);
841 RADV_NUM_PHYSICAL_VGPRS
/ conf
->num_vgprs
);
843 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
847 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
849 if (stage
== MESA_SHADER_FRAGMENT
) {
850 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
851 "SPI_PS_INPUT_ADDR = 0x%04x\n"
852 "SPI_PS_INPUT_ENA = 0x%04x\n",
853 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
856 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
859 "Spilled SGPRs: %d\n"
860 "Spilled VGPRs: %d\n"
861 "PrivMem VGPRS: %d\n"
862 "Code Size: %d bytes\n"
864 "Scratch: %d bytes per wave\n"
866 "********************\n\n\n",
867 conf
->num_sgprs
, conf
->num_vgprs
,
868 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
869 variant
->info
.private_mem_vgprs
, variant
->code_size
,
870 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
875 radv_shader_dump_stats(struct radv_device
*device
,
876 struct radv_shader_variant
*variant
,
877 gl_shader_stage stage
,
880 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
882 generate_shader_stats(device
, variant
, stage
, buf
);
884 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
885 fprintf(file
, "%s", buf
->buf
);
887 _mesa_string_buffer_destroy(buf
);
891 radv_GetShaderInfoAMD(VkDevice _device
,
892 VkPipeline _pipeline
,
893 VkShaderStageFlagBits shaderStage
,
894 VkShaderInfoTypeAMD infoType
,
898 RADV_FROM_HANDLE(radv_device
, device
, _device
);
899 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
900 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
901 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
902 struct _mesa_string_buffer
*buf
;
903 VkResult result
= VK_SUCCESS
;
905 /* Spec doesn't indicate what to do if the stage is invalid, so just
906 * return no info for this. */
908 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
911 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
913 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
915 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
916 struct ac_shader_config
*conf
= &variant
->config
;
918 VkShaderStatisticsInfoAMD statistics
= {};
919 statistics
.shaderStageMask
= shaderStage
;
920 statistics
.numPhysicalVgprs
= RADV_NUM_PHYSICAL_VGPRS
;
921 statistics
.numPhysicalSgprs
= ac_get_num_physical_sgprs(device
->physical_device
->rad_info
.chip_class
);
922 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
924 if (stage
== MESA_SHADER_COMPUTE
) {
925 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
926 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
928 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
929 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
931 statistics
.computeWorkGroupSize
[0] = local_size
[0];
932 statistics
.computeWorkGroupSize
[1] = local_size
[1];
933 statistics
.computeWorkGroupSize
[2] = local_size
[2];
935 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
938 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
939 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
940 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
941 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
942 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
944 size_t size
= *pInfoSize
;
945 *pInfoSize
= sizeof(statistics
);
947 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
949 if (size
< *pInfoSize
)
950 result
= VK_INCOMPLETE
;
954 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
955 buf
= _mesa_string_buffer_create(NULL
, 1024);
957 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
958 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->llvm_ir_string
);
959 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
960 generate_shader_stats(device
, variant
, stage
, buf
);
962 /* Need to include the null terminator. */
963 size_t length
= buf
->length
+ 1;
968 size_t size
= *pInfoSize
;
971 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
974 result
= VK_INCOMPLETE
;
977 _mesa_string_buffer_destroy(buf
);
980 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
981 result
= VK_ERROR_FEATURE_NOT_PRESENT
;