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radv/gfx10: adjust the GS NGG scratch size for streamout
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
41
42 #include "sid.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "ac_rtld.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50
51 #include "util/string_buffer.h"
52
53 static const struct nir_shader_compiler_options nir_options = {
54 .vertex_id_zero_based = true,
55 .lower_scmp = true,
56 .lower_flrp16 = true,
57 .lower_flrp32 = true,
58 .lower_flrp64 = true,
59 .lower_device_index_to_zero = true,
60 .lower_fsat = true,
61 .lower_fdiv = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .max_unroll_iterations = 32,
80 .use_interpolated_input_intrinsics = true,
81 };
82
83 bool
84 radv_can_dump_shader(struct radv_device *device,
85 struct radv_shader_module *module,
86 bool is_gs_copy_shader)
87 {
88 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
89 return false;
90
91 /* Only dump non-meta shaders, useful for debugging purposes. */
92 return (module && !module->nir) || is_gs_copy_shader;
93 }
94
95 bool
96 radv_can_dump_shader_stats(struct radv_device *device,
97 struct radv_shader_module *module)
98 {
99 /* Only dump non-meta shader stats. */
100 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
101 module && !module->nir;
102 }
103
104 unsigned shader_io_get_unique_index(gl_varying_slot slot)
105 {
106 /* handle patch indices separate */
107 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
108 return 0;
109 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
110 return 1;
111 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
112 return 2 + (slot - VARYING_SLOT_PATCH0);
113 if (slot == VARYING_SLOT_POS)
114 return 0;
115 if (slot == VARYING_SLOT_PSIZ)
116 return 1;
117 if (slot == VARYING_SLOT_CLIP_DIST0)
118 return 2;
119 if (slot == VARYING_SLOT_CLIP_DIST1)
120 return 3;
121 /* 3 is reserved for clip dist as well */
122 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
123 return 4 + (slot - VARYING_SLOT_VAR0);
124 unreachable("illegal slot in get unique index\n");
125 }
126
127 VkResult radv_CreateShaderModule(
128 VkDevice _device,
129 const VkShaderModuleCreateInfo* pCreateInfo,
130 const VkAllocationCallbacks* pAllocator,
131 VkShaderModule* pShaderModule)
132 {
133 RADV_FROM_HANDLE(radv_device, device, _device);
134 struct radv_shader_module *module;
135
136 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
137 assert(pCreateInfo->flags == 0);
138
139 module = vk_alloc2(&device->alloc, pAllocator,
140 sizeof(*module) + pCreateInfo->codeSize, 8,
141 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
142 if (module == NULL)
143 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
144
145 module->nir = NULL;
146 module->size = pCreateInfo->codeSize;
147 memcpy(module->data, pCreateInfo->pCode, module->size);
148
149 _mesa_sha1_compute(module->data, module->size, module->sha1);
150
151 *pShaderModule = radv_shader_module_to_handle(module);
152
153 return VK_SUCCESS;
154 }
155
156 void radv_DestroyShaderModule(
157 VkDevice _device,
158 VkShaderModule _module,
159 const VkAllocationCallbacks* pAllocator)
160 {
161 RADV_FROM_HANDLE(radv_device, device, _device);
162 RADV_FROM_HANDLE(radv_shader_module, module, _module);
163
164 if (!module)
165 return;
166
167 vk_free2(&device->alloc, pAllocator, module);
168 }
169
170 void
171 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
172 bool allow_copies)
173 {
174 bool progress;
175 unsigned lower_flrp =
176 (shader->options->lower_flrp16 ? 16 : 0) |
177 (shader->options->lower_flrp32 ? 32 : 0) |
178 (shader->options->lower_flrp64 ? 64 : 0);
179
180 do {
181 progress = false;
182
183 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
184 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
185
186 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
187 NIR_PASS_V(shader, nir_lower_pack);
188
189 if (allow_copies) {
190 /* Only run this pass in the first call to
191 * radv_optimize_nir. Later calls assume that we've
192 * lowered away any copy_deref instructions and we
193 * don't want to introduce any more.
194 */
195 NIR_PASS(progress, shader, nir_opt_find_array_copies);
196 }
197
198 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
199 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
200 NIR_PASS(progress, shader, nir_remove_dead_variables,
201 nir_var_function_temp);
202
203 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
204 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
205
206 NIR_PASS(progress, shader, nir_copy_prop);
207 NIR_PASS(progress, shader, nir_opt_remove_phis);
208 NIR_PASS(progress, shader, nir_opt_dce);
209 if (nir_opt_trivial_continues(shader)) {
210 progress = true;
211 NIR_PASS(progress, shader, nir_copy_prop);
212 NIR_PASS(progress, shader, nir_opt_remove_phis);
213 NIR_PASS(progress, shader, nir_opt_dce);
214 }
215 NIR_PASS(progress, shader, nir_opt_if, true);
216 NIR_PASS(progress, shader, nir_opt_dead_cf);
217 NIR_PASS(progress, shader, nir_opt_cse);
218 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
219 NIR_PASS(progress, shader, nir_opt_constant_folding);
220 NIR_PASS(progress, shader, nir_opt_algebraic);
221
222 if (lower_flrp != 0) {
223 bool lower_flrp_progress = false;
224 NIR_PASS(lower_flrp_progress,
225 shader,
226 nir_lower_flrp,
227 lower_flrp,
228 false /* always_precise */,
229 shader->options->lower_ffma);
230 if (lower_flrp_progress) {
231 NIR_PASS(progress, shader,
232 nir_opt_constant_folding);
233 progress = true;
234 }
235
236 /* Nothing should rematerialize any flrps, so we only
237 * need to do this lowering once.
238 */
239 lower_flrp = 0;
240 }
241
242 NIR_PASS(progress, shader, nir_opt_undef);
243 if (shader->options->max_unroll_iterations) {
244 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
245 }
246 } while (progress && !optimize_conservatively);
247
248 NIR_PASS(progress, shader, nir_opt_conditional_discard);
249 NIR_PASS(progress, shader, nir_opt_shrink_load);
250 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
251 }
252
253 nir_shader *
254 radv_shader_compile_to_nir(struct radv_device *device,
255 struct radv_shader_module *module,
256 const char *entrypoint_name,
257 gl_shader_stage stage,
258 const VkSpecializationInfo *spec_info,
259 const VkPipelineCreateFlags flags,
260 const struct radv_pipeline_layout *layout)
261 {
262 nir_shader *nir;
263 if (module->nir) {
264 /* Some things such as our meta clear/blit code will give us a NIR
265 * shader directly. In that case, we just ignore the SPIR-V entirely
266 * and just use the NIR shader */
267 nir = module->nir;
268 nir->options = &nir_options;
269 nir_validate_shader(nir, "in internal shader");
270
271 assert(exec_list_length(&nir->functions) == 1);
272 } else {
273 uint32_t *spirv = (uint32_t *) module->data;
274 assert(module->size % 4 == 0);
275
276 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
277 radv_print_spirv(spirv, module->size, stderr);
278
279 uint32_t num_spec_entries = 0;
280 struct nir_spirv_specialization *spec_entries = NULL;
281 if (spec_info && spec_info->mapEntryCount > 0) {
282 num_spec_entries = spec_info->mapEntryCount;
283 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
284 for (uint32_t i = 0; i < num_spec_entries; i++) {
285 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
286 const void *data = spec_info->pData + entry.offset;
287 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
288
289 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
290 if (spec_info->dataSize == 8)
291 spec_entries[i].data64 = *(const uint64_t *)data;
292 else
293 spec_entries[i].data32 = *(const uint32_t *)data;
294 }
295 }
296 const struct spirv_to_nir_options spirv_options = {
297 .lower_ubo_ssbo_access_to_offsets = true,
298 .caps = {
299 .amd_gcn_shader = true,
300 .amd_shader_ballot = device->physical_device->use_shader_ballot,
301 .amd_trinary_minmax = true,
302 .derivative_group = true,
303 .descriptor_array_dynamic_indexing = true,
304 .descriptor_array_non_uniform_indexing = true,
305 .descriptor_indexing = true,
306 .device_group = true,
307 .draw_parameters = true,
308 .float16 = true,
309 .float64 = true,
310 .geometry_streams = true,
311 .image_read_without_format = true,
312 .image_write_without_format = true,
313 .int8 = true,
314 .int16 = true,
315 .int64 = true,
316 .int64_atomics = true,
317 .multiview = true,
318 .physical_storage_buffer_address = true,
319 .post_depth_coverage = true,
320 .runtime_descriptor_array = true,
321 .shader_viewport_index_layer = true,
322 .stencil_export = true,
323 .storage_8bit = true,
324 .storage_16bit = true,
325 .storage_image_ms = true,
326 .subgroup_arithmetic = true,
327 .subgroup_ballot = true,
328 .subgroup_basic = true,
329 .subgroup_quad = true,
330 .subgroup_shuffle = true,
331 .subgroup_vote = true,
332 .tessellation = true,
333 .transform_feedback = true,
334 .variable_pointers = true,
335 },
336 .ubo_addr_format = nir_address_format_32bit_index_offset,
337 .ssbo_addr_format = nir_address_format_32bit_index_offset,
338 .phys_ssbo_addr_format = nir_address_format_64bit_global,
339 .push_const_addr_format = nir_address_format_logical,
340 .shared_addr_format = nir_address_format_32bit_offset,
341 .frag_coord_is_sysval = true,
342 };
343 nir = spirv_to_nir(spirv, module->size / 4,
344 spec_entries, num_spec_entries,
345 stage, entrypoint_name,
346 &spirv_options, &nir_options);
347 assert(nir->info.stage == stage);
348 nir_validate_shader(nir, "after spirv_to_nir");
349
350 free(spec_entries);
351
352 /* We have to lower away local constant initializers right before we
353 * inline functions. That way they get properly initialized at the top
354 * of the function and not at the top of its caller.
355 */
356 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
357 NIR_PASS_V(nir, nir_lower_returns);
358 NIR_PASS_V(nir, nir_inline_functions);
359 NIR_PASS_V(nir, nir_opt_deref);
360
361 /* Pick off the single entrypoint that we want */
362 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
363 if (func->is_entrypoint)
364 func->name = ralloc_strdup(func, "main");
365 else
366 exec_node_remove(&func->node);
367 }
368 assert(exec_list_length(&nir->functions) == 1);
369
370 /* Make sure we lower constant initializers on output variables so that
371 * nir_remove_dead_variables below sees the corresponding stores
372 */
373 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
374
375 /* Now that we've deleted all but the main function, we can go ahead and
376 * lower the rest of the constant initializers.
377 */
378 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
379
380 /* Split member structs. We do this before lower_io_to_temporaries so that
381 * it doesn't lower system values to temporaries by accident.
382 */
383 NIR_PASS_V(nir, nir_split_var_copies);
384 NIR_PASS_V(nir, nir_split_per_member_structs);
385
386 if (nir->info.stage == MESA_SHADER_FRAGMENT)
387 NIR_PASS_V(nir, nir_lower_input_attachments, true);
388
389 NIR_PASS_V(nir, nir_remove_dead_variables,
390 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
391
392 NIR_PASS_V(nir, nir_propagate_invariant);
393
394 NIR_PASS_V(nir, nir_lower_system_values);
395 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
396 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
397 }
398
399 /* Vulkan uses the separate-shader linking model */
400 nir->info.separate_shader = true;
401
402 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
403
404 static const nir_lower_tex_options tex_options = {
405 .lower_txp = ~0,
406 .lower_tg4_offsets = true,
407 };
408
409 nir_lower_tex(nir, &tex_options);
410
411 nir_lower_vars_to_ssa(nir);
412
413 if (nir->info.stage == MESA_SHADER_VERTEX ||
414 nir->info.stage == MESA_SHADER_GEOMETRY ||
415 nir->info.stage == MESA_SHADER_FRAGMENT) {
416 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
417 nir_shader_get_entrypoint(nir), true, true);
418 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
419 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
420 nir_shader_get_entrypoint(nir), true, false);
421 }
422
423 nir_split_var_copies(nir);
424
425 nir_lower_global_vars_to_local(nir);
426 nir_remove_dead_variables(nir, nir_var_function_temp);
427 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
428 .subgroup_size = 64,
429 .ballot_bit_size = 64,
430 .lower_to_scalar = 1,
431 .lower_subgroup_masks = 1,
432 .lower_shuffle = 1,
433 .lower_shuffle_to_32bit = 1,
434 .lower_vote_eq_to_ballot = 1,
435 });
436
437 nir_lower_load_const_to_scalar(nir);
438
439 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
440 radv_optimize_nir(nir, false, true);
441
442 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
443 * to remove any copies introduced by nir_opt_find_array_copies().
444 */
445 nir_lower_var_copies(nir);
446
447 /* Lower large variables that are always constant with load_constant
448 * intrinsics, which get turned into PC-relative loads from a data
449 * section next to the shader.
450 */
451 NIR_PASS_V(nir, nir_opt_large_constants,
452 glsl_get_natural_size_align_bytes, 16);
453
454 /* Indirect lowering must be called after the radv_optimize_nir() loop
455 * has been called at least once. Otherwise indirect lowering can
456 * bloat the instruction count of the loop and cause it to be
457 * considered too large for unrolling.
458 */
459 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
460 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
461
462 return nir;
463 }
464
465 static int
466 type_size_vec4(const struct glsl_type *type, bool bindless)
467 {
468 return glsl_count_attribute_slots(type, false);
469 }
470
471 static nir_variable *
472 find_layer_in_var(nir_shader *nir)
473 {
474 nir_foreach_variable(var, &nir->inputs) {
475 if (var->data.location == VARYING_SLOT_LAYER) {
476 return var;
477 }
478 }
479
480 nir_variable *var =
481 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
482 var->data.location = VARYING_SLOT_LAYER;
483 var->data.interpolation = INTERP_MODE_FLAT;
484 return var;
485 }
486
487 /* We use layered rendering to implement multiview, which means we need to map
488 * view_index to gl_Layer. The attachment lowering also uses needs to know the
489 * layer so that it can sample from the correct layer. The code generates a
490 * load from the layer_id sysval, but since we don't have a way to get at this
491 * information from the fragment shader, we also need to lower this to the
492 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
493 * slot, before lowering io, so that nir_assign_var_locations() will give the
494 * LAYER varying the correct driver_location.
495 */
496
497 static bool
498 lower_view_index(nir_shader *nir)
499 {
500 bool progress = false;
501 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
502 nir_builder b;
503 nir_builder_init(&b, entry);
504
505 nir_variable *layer = NULL;
506 nir_foreach_block(block, entry) {
507 nir_foreach_instr_safe(instr, block) {
508 if (instr->type != nir_instr_type_intrinsic)
509 continue;
510
511 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
512 if (load->intrinsic != nir_intrinsic_load_view_index &&
513 load->intrinsic != nir_intrinsic_load_layer_id)
514 continue;
515
516 if (!layer)
517 layer = find_layer_in_var(nir);
518
519 b.cursor = nir_before_instr(instr);
520 nir_ssa_def *def = nir_load_var(&b, layer);
521 nir_ssa_def_rewrite_uses(&load->dest.ssa,
522 nir_src_for_ssa(def));
523
524 nir_instr_remove(instr);
525 progress = true;
526 }
527 }
528
529 return progress;
530 }
531
532 void
533 radv_lower_fs_io(nir_shader *nir)
534 {
535 NIR_PASS_V(nir, lower_view_index);
536 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
537 MESA_SHADER_FRAGMENT);
538
539 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
540
541 /* This pass needs actual constants */
542 nir_opt_constant_folding(nir);
543
544 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
545 }
546
547
548 void *
549 radv_alloc_shader_memory(struct radv_device *device,
550 struct radv_shader_variant *shader)
551 {
552 mtx_lock(&device->shader_slab_mutex);
553 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
554 uint64_t offset = 0;
555 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
556 if (s->bo_offset - offset >= shader->code_size) {
557 shader->bo = slab->bo;
558 shader->bo_offset = offset;
559 list_addtail(&shader->slab_list, &s->slab_list);
560 mtx_unlock(&device->shader_slab_mutex);
561 return slab->ptr + offset;
562 }
563 offset = align_u64(s->bo_offset + s->code_size, 256);
564 }
565 if (slab->size - offset >= shader->code_size) {
566 shader->bo = slab->bo;
567 shader->bo_offset = offset;
568 list_addtail(&shader->slab_list, &slab->shaders);
569 mtx_unlock(&device->shader_slab_mutex);
570 return slab->ptr + offset;
571 }
572 }
573
574 mtx_unlock(&device->shader_slab_mutex);
575 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
576
577 slab->size = 256 * 1024;
578 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
579 RADEON_DOMAIN_VRAM,
580 RADEON_FLAG_NO_INTERPROCESS_SHARING |
581 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
582 0 : RADEON_FLAG_READ_ONLY),
583 RADV_BO_PRIORITY_SHADER);
584 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
585 list_inithead(&slab->shaders);
586
587 mtx_lock(&device->shader_slab_mutex);
588 list_add(&slab->slabs, &device->shader_slabs);
589
590 shader->bo = slab->bo;
591 shader->bo_offset = 0;
592 list_add(&shader->slab_list, &slab->shaders);
593 mtx_unlock(&device->shader_slab_mutex);
594 return slab->ptr;
595 }
596
597 void
598 radv_destroy_shader_slabs(struct radv_device *device)
599 {
600 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
601 device->ws->buffer_destroy(slab->bo);
602 free(slab);
603 }
604 mtx_destroy(&device->shader_slab_mutex);
605 }
606
607 /* For the UMR disassembler. */
608 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
609 #define DEBUGGER_NUM_MARKERS 5
610
611 static unsigned
612 radv_get_shader_binary_size(size_t code_size)
613 {
614 return code_size + DEBUGGER_NUM_MARKERS * 4;
615 }
616
617 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
618 const struct ac_shader_config *config_in,
619 const struct radv_shader_info *info,
620 gl_shader_stage stage,
621 struct ac_shader_config *config_out)
622 {
623 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
624 unsigned vgpr_comp_cnt = 0;
625 unsigned num_input_vgprs = info->num_input_vgprs;
626
627 if (stage == MESA_SHADER_FRAGMENT) {
628 num_input_vgprs = 0;
629 if (G_0286CC_PERSP_SAMPLE_ENA(config_in->spi_ps_input_addr))
630 num_input_vgprs += 2;
631 if (G_0286CC_PERSP_CENTER_ENA(config_in->spi_ps_input_addr))
632 num_input_vgprs += 2;
633 if (G_0286CC_PERSP_CENTROID_ENA(config_in->spi_ps_input_addr))
634 num_input_vgprs += 2;
635 if (G_0286CC_PERSP_PULL_MODEL_ENA(config_in->spi_ps_input_addr))
636 num_input_vgprs += 3;
637 if (G_0286CC_LINEAR_SAMPLE_ENA(config_in->spi_ps_input_addr))
638 num_input_vgprs += 2;
639 if (G_0286CC_LINEAR_CENTER_ENA(config_in->spi_ps_input_addr))
640 num_input_vgprs += 2;
641 if (G_0286CC_LINEAR_CENTROID_ENA(config_in->spi_ps_input_addr))
642 num_input_vgprs += 2;
643 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config_in->spi_ps_input_addr))
644 num_input_vgprs += 1;
645 if (G_0286CC_POS_X_FLOAT_ENA(config_in->spi_ps_input_addr))
646 num_input_vgprs += 1;
647 if (G_0286CC_POS_Y_FLOAT_ENA(config_in->spi_ps_input_addr))
648 num_input_vgprs += 1;
649 if (G_0286CC_POS_Z_FLOAT_ENA(config_in->spi_ps_input_addr))
650 num_input_vgprs += 1;
651 if (G_0286CC_POS_W_FLOAT_ENA(config_in->spi_ps_input_addr))
652 num_input_vgprs += 1;
653 if (G_0286CC_FRONT_FACE_ENA(config_in->spi_ps_input_addr))
654 num_input_vgprs += 1;
655 if (G_0286CC_ANCILLARY_ENA(config_in->spi_ps_input_addr))
656 num_input_vgprs += 1;
657 if (G_0286CC_SAMPLE_COVERAGE_ENA(config_in->spi_ps_input_addr))
658 num_input_vgprs += 1;
659 if (G_0286CC_POS_FIXED_PT_ENA(config_in->spi_ps_input_addr))
660 num_input_vgprs += 1;
661 }
662
663 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
664 /* +3 for scratch wave offset and VCC */
665 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
666
667 *config_out = *config_in;
668 config_out->num_vgprs = num_vgprs;
669 config_out->num_sgprs = num_sgprs;
670
671 /* Enable 64-bit and 16-bit denormals, because there is no performance
672 * cost.
673 *
674 * If denormals are enabled, all floating-point output modifiers are
675 * ignored.
676 *
677 * Don't enable denormals for 32-bit floats, because:
678 * - Floating-point output modifiers would be ignored by the hw.
679 * - Some opcodes don't support denormals, such as v_mad_f32. We would
680 * have to stop using those.
681 * - GFX6 & GFX7 would be very slow.
682 */
683 config_out->float_mode |= V_00B028_FP_64_DENORMS;
684
685 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
686 S_00B12C_SCRATCH_EN(scratch_enabled);
687
688 if (!pdevice->use_ngg_streamout) {
689 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
690 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
691 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
692 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
693 S_00B12C_SO_EN(!!info->so.num_outputs);
694 }
695
696 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
697 (info->wave_size == 32 ? 8 : 4)) |
698 S_00B848_DX10_CLAMP(1) |
699 S_00B848_FLOAT_MODE(config_out->float_mode);
700
701 if (pdevice->rad_info.chip_class >= GFX10) {
702 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
703 } else {
704 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
705 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
706 }
707
708 switch (stage) {
709 case MESA_SHADER_TESS_EVAL:
710 if (info->is_ngg) {
711 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
712 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
713 } else if (info->tes.as_es) {
714 assert(pdevice->rad_info.chip_class <= GFX8);
715 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
716
717 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
718 } else {
719 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
720 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
721
722 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
723 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
724 }
725 break;
726 case MESA_SHADER_TESS_CTRL:
727 if (pdevice->rad_info.chip_class >= GFX9) {
728 /* We need at least 2 components for LS.
729 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
730 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
731 */
732 if (pdevice->rad_info.chip_class >= GFX10) {
733 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
734 } else {
735 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
736 }
737 } else {
738 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
739 }
740 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
741 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
742 break;
743 case MESA_SHADER_VERTEX:
744 if (info->is_ngg) {
745 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
746 } else if (info->vs.as_ls) {
747 assert(pdevice->rad_info.chip_class <= GFX8);
748 /* We need at least 2 components for LS.
749 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
750 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
751 */
752 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
753 } else if (info->vs.as_es) {
754 assert(pdevice->rad_info.chip_class <= GFX8);
755 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
756 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
757 } else {
758 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
759 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
760 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
761 */
762 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
763 vgpr_comp_cnt = 3;
764 } else if (info->vs.export_prim_id) {
765 vgpr_comp_cnt = 2;
766 } else if (info->vs.needs_instance_id) {
767 vgpr_comp_cnt = 1;
768 } else {
769 vgpr_comp_cnt = 0;
770 }
771
772 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
773 }
774 break;
775 case MESA_SHADER_FRAGMENT:
776 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
777 break;
778 case MESA_SHADER_GEOMETRY:
779 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
780 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
781 break;
782 case MESA_SHADER_COMPUTE:
783 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
784 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
785 config_out->rsrc2 |=
786 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
787 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
788 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
789 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
790 info->cs.uses_thread_id[1] ? 1 : 0) |
791 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
792 S_00B84C_LDS_SIZE(config_in->lds_size);
793 break;
794 default:
795 unreachable("unsupported shader type");
796 break;
797 }
798
799 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
800 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
801 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
802 gl_shader_stage es_stage = stage;
803 if (stage == MESA_SHADER_GEOMETRY)
804 es_stage = info->gs.es_type;
805
806 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
807 if (es_stage == MESA_SHADER_VERTEX) {
808 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
809 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
810 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
811 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
812 } else
813 unreachable("Unexpected ES shader stage");
814
815 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
816 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
817 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
818 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
819 } else if (info->uses_prim_id) {
820 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
821 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
822 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
823 } else {
824 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
825 }
826
827 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
828 S_00B228_WGP_MODE(1);
829 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
830 S_00B22C_LDS_SIZE(config_in->lds_size) |
831 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
832 } else if (pdevice->rad_info.chip_class >= GFX9 &&
833 stage == MESA_SHADER_GEOMETRY) {
834 unsigned es_type = info->gs.es_type;
835 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
836
837 if (es_type == MESA_SHADER_VERTEX) {
838 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
839 if (info->vs.needs_instance_id) {
840 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
841 } else {
842 es_vgpr_comp_cnt = 0;
843 }
844 } else if (es_type == MESA_SHADER_TESS_EVAL) {
845 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
846 } else {
847 unreachable("invalid shader ES type");
848 }
849
850 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
851 * VGPR[0:4] are always loaded.
852 */
853 if (info->uses_invocation_id) {
854 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
855 } else if (info->uses_prim_id) {
856 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
857 } else if (info->gs.vertices_in >= 3) {
858 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
859 } else {
860 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
861 }
862
863 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
864 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
865 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
866 } else if (pdevice->rad_info.chip_class >= GFX9 &&
867 stage == MESA_SHADER_TESS_CTRL) {
868 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
869 } else {
870 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
871 }
872 }
873
874 struct radv_shader_variant *
875 radv_shader_variant_create(struct radv_device *device,
876 const struct radv_shader_binary *binary,
877 bool keep_shader_info)
878 {
879 struct ac_shader_config config = {0};
880 struct ac_rtld_binary rtld_binary = {0};
881 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
882 if (!variant)
883 return NULL;
884
885 variant->ref_count = 1;
886
887 if (binary->type == RADV_BINARY_TYPE_RTLD) {
888 struct ac_rtld_symbol lds_symbols[2];
889 unsigned num_lds_symbols = 0;
890 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
891 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
892
893 if (device->physical_device->rad_info.chip_class >= GFX9 &&
894 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
895 !binary->is_gs_copy_shader) {
896 /* We add this symbol even on LLVM <= 8 to ensure that
897 * shader->config.lds_size is set correctly below.
898 */
899 /* TODO: For some reasons, using the computed ESGS ring
900 * size randomly hangs with CTS. Just use the maximum
901 * possible LDS size for now.
902 */
903 unsigned ngg_scratch_size = 8 * 4;
904 if (binary->info.so.num_outputs) {
905 /* Memory layout of NGG streamout scratch:
906 * [0-3]: number of generated primitives
907 * [4-7]: number of emitted primitives
908 * [8-11]: streamout offsets
909 * [12:19]: primitive offsets for stream 0
910 * [20:27]: primitive offsets for stream 1
911 * [28:35]: primitive offsets for stream 2
912 * [36:43]: primitive offsets for stream 3
913 */
914 ngg_scratch_size = 44 * 4;
915 }
916
917 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
918 sym->name = "esgs_ring";
919 sym->size = (32 * 1024) - (binary->info.ngg_info.ngg_emit_size * 4) - ngg_scratch_size;
920 sym->align = 64 * 1024;
921 }
922
923 if (binary->info.is_ngg &&
924 binary->stage == MESA_SHADER_GEOMETRY) {
925 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
926 sym->name = "ngg_emit";
927 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
928 sym->align = 4;
929 }
930
931 struct ac_rtld_open_info open_info = {
932 .info = &device->physical_device->rad_info,
933 .shader_type = binary->stage,
934 .wave_size = binary->info.wave_size,
935 .num_parts = 1,
936 .elf_ptrs = &elf_data,
937 .elf_sizes = &elf_size,
938 .num_shared_lds_symbols = num_lds_symbols,
939 .shared_lds_symbols = lds_symbols,
940 };
941
942 if (!ac_rtld_open(&rtld_binary, open_info)) {
943 free(variant);
944 return NULL;
945 }
946
947 if (!ac_rtld_read_config(&rtld_binary, &config)) {
948 ac_rtld_close(&rtld_binary);
949 free(variant);
950 return NULL;
951 }
952
953 if (rtld_binary.lds_size > 0) {
954 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
955 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
956 }
957
958 variant->code_size = rtld_binary.rx_size;
959 variant->exec_size = rtld_binary.exec_size;
960 } else {
961 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
962 config = ((struct radv_shader_binary_legacy *)binary)->config;
963 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
964 variant->exec_size = variant->code_size;
965 }
966
967 variant->info = binary->info;
968 radv_postprocess_config(device->physical_device, &config, &binary->info,
969 binary->stage, &variant->config);
970
971 void *dest_ptr = radv_alloc_shader_memory(device, variant);
972
973 if (binary->type == RADV_BINARY_TYPE_RTLD) {
974 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
975 struct ac_rtld_upload_info info = {
976 .binary = &rtld_binary,
977 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
978 .rx_ptr = dest_ptr,
979 };
980
981 if (!ac_rtld_upload(&info)) {
982 radv_shader_variant_destroy(device, variant);
983 ac_rtld_close(&rtld_binary);
984 return NULL;
985 }
986
987 if (keep_shader_info ||
988 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
989 const char *disasm_data;
990 size_t disasm_size;
991 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
992 radv_shader_variant_destroy(device, variant);
993 ac_rtld_close(&rtld_binary);
994 return NULL;
995 }
996
997 variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
998 variant->disasm_string = malloc(disasm_size + 1);
999 memcpy(variant->disasm_string, disasm_data, disasm_size);
1000 variant->disasm_string[disasm_size] = 0;
1001 }
1002
1003 ac_rtld_close(&rtld_binary);
1004 } else {
1005 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1006 memcpy(dest_ptr, bin->data, bin->code_size);
1007
1008 /* Add end-of-code markers for the UMR disassembler. */
1009 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1010 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1011 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1012
1013 variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
1014 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->llvm_ir_size)) : NULL;
1015 }
1016 return variant;
1017 }
1018
1019 static char *
1020 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1021 int shader_count)
1022 {
1023 char *data = NULL;
1024 char *ret = NULL;
1025 size_t size = 0;
1026 FILE *f = open_memstream(&data, &size);
1027 if (f) {
1028 for (int i = 0; i < shader_count; ++i)
1029 nir_print_shader(shaders[i], f);
1030 fclose(f);
1031 }
1032
1033 ret = malloc(size + 1);
1034 if (ret) {
1035 memcpy(ret, data, size);
1036 ret[size] = 0;
1037 }
1038 free(data);
1039 return ret;
1040 }
1041
1042 static struct radv_shader_variant *
1043 shader_variant_compile(struct radv_device *device,
1044 struct radv_shader_module *module,
1045 struct nir_shader * const *shaders,
1046 int shader_count,
1047 gl_shader_stage stage,
1048 struct radv_shader_info *info,
1049 struct radv_nir_compiler_options *options,
1050 bool gs_copy_shader,
1051 bool keep_shader_info,
1052 struct radv_shader_binary **binary_out)
1053 {
1054 enum radeon_family chip_family = device->physical_device->rad_info.family;
1055 enum ac_target_machine_options tm_options = 0;
1056 struct ac_llvm_compiler ac_llvm;
1057 struct radv_shader_binary *binary = NULL;
1058 bool thread_compiler;
1059
1060 options->family = chip_family;
1061 options->chip_class = device->physical_device->rad_info.chip_class;
1062 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1063 options->dump_preoptir = options->dump_shader &&
1064 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1065 options->record_llvm_ir = keep_shader_info;
1066 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1067 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1068 options->address32_hi = device->physical_device->rad_info.address32_hi;
1069 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1070 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1071
1072 if ((stage == MESA_SHADER_GEOMETRY && !options->key.vs_common_out.as_ngg) ||
1073 gs_copy_shader)
1074 options->wave_size = 64;
1075 else if (stage == MESA_SHADER_COMPUTE)
1076 options->wave_size = device->physical_device->cs_wave_size;
1077 else if (stage == MESA_SHADER_FRAGMENT)
1078 options->wave_size = device->physical_device->ps_wave_size;
1079 else
1080 options->wave_size = device->physical_device->ge_wave_size;
1081
1082 if (options->supports_spill)
1083 tm_options |= AC_TM_SUPPORTS_SPILL;
1084 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
1085 tm_options |= AC_TM_SISCHED;
1086 if (options->check_ir)
1087 tm_options |= AC_TM_CHECK_IR;
1088 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
1089 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
1090
1091 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
1092 ac_init_llvm_once();
1093 radv_init_llvm_compiler(&ac_llvm,
1094 thread_compiler,
1095 chip_family, tm_options,
1096 options->wave_size);
1097 if (gs_copy_shader) {
1098 assert(shader_count == 1);
1099 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
1100 info, options);
1101 } else {
1102 radv_compile_nir_shader(&ac_llvm, &binary, info,
1103 shaders, shader_count, options);
1104 }
1105 binary->info = *info;
1106
1107 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
1108
1109 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1110 keep_shader_info);
1111 if (!variant) {
1112 free(binary);
1113 return NULL;
1114 }
1115
1116 if (options->dump_shader) {
1117 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
1118 }
1119
1120
1121 if (keep_shader_info) {
1122 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1123 if (!gs_copy_shader && !module->nir) {
1124 variant->spirv = (uint32_t *)module->data;
1125 variant->spirv_size = module->size;
1126 }
1127 }
1128
1129 if (binary_out)
1130 *binary_out = binary;
1131 else
1132 free(binary);
1133
1134 return variant;
1135 }
1136
1137 struct radv_shader_variant *
1138 radv_shader_variant_compile(struct radv_device *device,
1139 struct radv_shader_module *module,
1140 struct nir_shader *const *shaders,
1141 int shader_count,
1142 struct radv_pipeline_layout *layout,
1143 const struct radv_shader_variant_key *key,
1144 struct radv_shader_info *info,
1145 bool keep_shader_info,
1146 struct radv_shader_binary **binary_out)
1147 {
1148 struct radv_nir_compiler_options options = {0};
1149
1150 options.layout = layout;
1151 if (key)
1152 options.key = *key;
1153
1154 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
1155 options.supports_spill = true;
1156 options.robust_buffer_access = device->robust_buffer_access;
1157
1158 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1159 &options, false, keep_shader_info, binary_out);
1160 }
1161
1162 struct radv_shader_variant *
1163 radv_create_gs_copy_shader(struct radv_device *device,
1164 struct nir_shader *shader,
1165 struct radv_shader_info *info,
1166 struct radv_shader_binary **binary_out,
1167 bool keep_shader_info,
1168 bool multiview)
1169 {
1170 struct radv_nir_compiler_options options = {0};
1171
1172 options.key.has_multiview_view_index = multiview;
1173
1174 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1175 info, &options, true, keep_shader_info, binary_out);
1176 }
1177
1178 void
1179 radv_shader_variant_destroy(struct radv_device *device,
1180 struct radv_shader_variant *variant)
1181 {
1182 if (!p_atomic_dec_zero(&variant->ref_count))
1183 return;
1184
1185 mtx_lock(&device->shader_slab_mutex);
1186 list_del(&variant->slab_list);
1187 mtx_unlock(&device->shader_slab_mutex);
1188
1189 free(variant->nir_string);
1190 free(variant->disasm_string);
1191 free(variant->llvm_ir_string);
1192 free(variant);
1193 }
1194
1195 const char *
1196 radv_get_shader_name(struct radv_shader_info *info,
1197 gl_shader_stage stage)
1198 {
1199 switch (stage) {
1200 case MESA_SHADER_VERTEX:
1201 if (info->vs.as_ls)
1202 return "Vertex Shader as LS";
1203 else if (info->vs.as_es)
1204 return "Vertex Shader as ES";
1205 else if (info->is_ngg)
1206 return "Vertex Shader as ESGS";
1207 else
1208 return "Vertex Shader as VS";
1209 case MESA_SHADER_TESS_CTRL:
1210 return "Tessellation Control Shader";
1211 case MESA_SHADER_TESS_EVAL:
1212 if (info->tes.as_es)
1213 return "Tessellation Evaluation Shader as ES";
1214 else if (info->is_ngg)
1215 return "Tessellation Evaluation Shader as ESGS";
1216 else
1217 return "Tessellation Evaluation Shader as VS";
1218 case MESA_SHADER_GEOMETRY:
1219 return "Geometry Shader";
1220 case MESA_SHADER_FRAGMENT:
1221 return "Pixel Shader";
1222 case MESA_SHADER_COMPUTE:
1223 return "Compute Shader";
1224 default:
1225 return "Unknown shader";
1226 };
1227 }
1228
1229 unsigned
1230 radv_get_max_workgroup_size(enum chip_class chip_class,
1231 gl_shader_stage stage,
1232 const unsigned *sizes)
1233 {
1234 switch (stage) {
1235 case MESA_SHADER_TESS_CTRL:
1236 return chip_class >= GFX7 ? 128 : 64;
1237 case MESA_SHADER_GEOMETRY:
1238 return chip_class >= GFX9 ? 128 : 64;
1239 case MESA_SHADER_COMPUTE:
1240 break;
1241 default:
1242 return 0;
1243 }
1244
1245 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1246 return max_workgroup_size;
1247 }
1248
1249 unsigned
1250 radv_get_max_waves(struct radv_device *device,
1251 struct radv_shader_variant *variant,
1252 gl_shader_stage stage)
1253 {
1254 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1255 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1256 uint8_t wave_size = variant->info.wave_size;
1257 struct ac_shader_config *conf = &variant->config;
1258 unsigned max_simd_waves;
1259 unsigned lds_per_wave = 0;
1260
1261 max_simd_waves = ac_get_max_wave64_per_simd(device->physical_device->rad_info.family);
1262
1263 if (stage == MESA_SHADER_FRAGMENT) {
1264 lds_per_wave = conf->lds_size * lds_increment +
1265 align(variant->info.ps.num_interp * 48,
1266 lds_increment);
1267 } else if (stage == MESA_SHADER_COMPUTE) {
1268 unsigned max_workgroup_size =
1269 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1270 lds_per_wave = (conf->lds_size * lds_increment) /
1271 DIV_ROUND_UP(max_workgroup_size, wave_size);
1272 }
1273
1274 if (conf->num_sgprs)
1275 max_simd_waves =
1276 MIN2(max_simd_waves,
1277 ac_get_num_physical_sgprs(&device->physical_device->rad_info) /
1278 conf->num_sgprs);
1279
1280 if (conf->num_vgprs)
1281 max_simd_waves =
1282 MIN2(max_simd_waves,
1283 RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
1284
1285 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1286 * that PS can use.
1287 */
1288 if (lds_per_wave)
1289 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1290
1291 return max_simd_waves;
1292 }
1293
1294 static void
1295 generate_shader_stats(struct radv_device *device,
1296 struct radv_shader_variant *variant,
1297 gl_shader_stage stage,
1298 struct _mesa_string_buffer *buf)
1299 {
1300 struct ac_shader_config *conf = &variant->config;
1301 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1302
1303 if (stage == MESA_SHADER_FRAGMENT) {
1304 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1305 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1306 "SPI_PS_INPUT_ENA = 0x%04x\n",
1307 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1308 }
1309
1310 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1311 "SGPRS: %d\n"
1312 "VGPRS: %d\n"
1313 "Spilled SGPRs: %d\n"
1314 "Spilled VGPRs: %d\n"
1315 "PrivMem VGPRS: %d\n"
1316 "Code Size: %d bytes\n"
1317 "LDS: %d blocks\n"
1318 "Scratch: %d bytes per wave\n"
1319 "Max Waves: %d\n"
1320 "********************\n\n\n",
1321 conf->num_sgprs, conf->num_vgprs,
1322 conf->spilled_sgprs, conf->spilled_vgprs,
1323 variant->info.private_mem_vgprs, variant->exec_size,
1324 conf->lds_size, conf->scratch_bytes_per_wave,
1325 max_simd_waves);
1326 }
1327
1328 void
1329 radv_shader_dump_stats(struct radv_device *device,
1330 struct radv_shader_variant *variant,
1331 gl_shader_stage stage,
1332 FILE *file)
1333 {
1334 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1335
1336 generate_shader_stats(device, variant, stage, buf);
1337
1338 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1339 fprintf(file, "%s", buf->buf);
1340
1341 _mesa_string_buffer_destroy(buf);
1342 }
1343
1344 VkResult
1345 radv_GetShaderInfoAMD(VkDevice _device,
1346 VkPipeline _pipeline,
1347 VkShaderStageFlagBits shaderStage,
1348 VkShaderInfoTypeAMD infoType,
1349 size_t* pInfoSize,
1350 void* pInfo)
1351 {
1352 RADV_FROM_HANDLE(radv_device, device, _device);
1353 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1354 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1355 struct radv_shader_variant *variant = pipeline->shaders[stage];
1356 struct _mesa_string_buffer *buf;
1357 VkResult result = VK_SUCCESS;
1358
1359 /* Spec doesn't indicate what to do if the stage is invalid, so just
1360 * return no info for this. */
1361 if (!variant)
1362 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1363
1364 switch (infoType) {
1365 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1366 if (!pInfo) {
1367 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1368 } else {
1369 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1370 struct ac_shader_config *conf = &variant->config;
1371
1372 VkShaderStatisticsInfoAMD statistics = {};
1373 statistics.shaderStageMask = shaderStage;
1374 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1375 statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(&device->physical_device->rad_info);
1376 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1377
1378 if (stage == MESA_SHADER_COMPUTE) {
1379 unsigned *local_size = variant->info.cs.block_size;
1380 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1381
1382 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1383 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1384
1385 statistics.computeWorkGroupSize[0] = local_size[0];
1386 statistics.computeWorkGroupSize[1] = local_size[1];
1387 statistics.computeWorkGroupSize[2] = local_size[2];
1388 } else {
1389 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1390 }
1391
1392 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1393 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1394 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1395 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1396 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1397
1398 size_t size = *pInfoSize;
1399 *pInfoSize = sizeof(statistics);
1400
1401 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1402
1403 if (size < *pInfoSize)
1404 result = VK_INCOMPLETE;
1405 }
1406
1407 break;
1408 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1409 buf = _mesa_string_buffer_create(NULL, 1024);
1410
1411 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1412 _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
1413 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1414 generate_shader_stats(device, variant, stage, buf);
1415
1416 /* Need to include the null terminator. */
1417 size_t length = buf->length + 1;
1418
1419 if (!pInfo) {
1420 *pInfoSize = length;
1421 } else {
1422 size_t size = *pInfoSize;
1423 *pInfoSize = length;
1424
1425 memcpy(pInfo, buf->buf, MIN2(size, length));
1426
1427 if (size < length)
1428 result = VK_INCOMPLETE;
1429 }
1430
1431 _mesa_string_buffer_destroy(buf);
1432 break;
1433 default:
1434 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1435 result = VK_ERROR_FEATURE_NOT_PRESENT;
1436 break;
1437 }
1438
1439 return result;
1440 }