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radv: remove the secure compile support feature
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .max_unroll_iterations = 32,
80 .use_interpolated_input_intrinsics = true,
81 /* nir_lower_int64() isn't actually called for the LLVM backend, but
82 * this helps the loop unrolling heuristics. */
83 .lower_int64_options = nir_lower_imul64 |
84 nir_lower_imul_high64 |
85 nir_lower_imul_2x32_64 |
86 nir_lower_divmod64 |
87 nir_lower_minmax64 |
88 nir_lower_iabs64,
89 .lower_doubles_options = nir_lower_drcp |
90 nir_lower_dsqrt |
91 nir_lower_drsq |
92 nir_lower_ddiv,
93 };
94
95 static const struct nir_shader_compiler_options nir_options_aco = {
96 .vertex_id_zero_based = true,
97 .lower_scmp = true,
98 .lower_flrp16 = true,
99 .lower_flrp32 = true,
100 .lower_flrp64 = true,
101 .lower_device_index_to_zero = true,
102 .lower_fdiv = true,
103 .lower_fmod = true,
104 .lower_bitfield_insert_to_bitfield_select = true,
105 .lower_bitfield_extract = true,
106 .lower_pack_snorm_2x16 = true,
107 .lower_pack_snorm_4x8 = true,
108 .lower_pack_unorm_2x16 = true,
109 .lower_pack_unorm_4x8 = true,
110 .lower_unpack_snorm_2x16 = true,
111 .lower_unpack_snorm_4x8 = true,
112 .lower_unpack_unorm_2x16 = true,
113 .lower_unpack_unorm_4x8 = true,
114 .lower_unpack_half_2x16 = true,
115 .lower_extract_byte = true,
116 .lower_extract_word = true,
117 .lower_ffma = true,
118 .lower_fpow = true,
119 .lower_mul_2x32_64 = true,
120 .lower_rotate = true,
121 .max_unroll_iterations = 32,
122 .use_interpolated_input_intrinsics = true,
123 .lower_int64_options = nir_lower_imul64 |
124 nir_lower_imul_high64 |
125 nir_lower_imul_2x32_64 |
126 nir_lower_divmod64 |
127 nir_lower_minmax64 |
128 nir_lower_iabs64,
129 .lower_doubles_options = nir_lower_drcp |
130 nir_lower_dsqrt |
131 nir_lower_drsq |
132 nir_lower_ddiv,
133 };
134
135 bool
136 radv_can_dump_shader(struct radv_device *device,
137 struct radv_shader_module *module,
138 bool is_gs_copy_shader)
139 {
140 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
141 return false;
142 if (module)
143 return !module->nir ||
144 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
145
146 return is_gs_copy_shader;
147 }
148
149 bool
150 radv_can_dump_shader_stats(struct radv_device *device,
151 struct radv_shader_module *module)
152 {
153 /* Only dump non-meta shader stats. */
154 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
155 module && !module->nir;
156 }
157
158 VkResult radv_CreateShaderModule(
159 VkDevice _device,
160 const VkShaderModuleCreateInfo* pCreateInfo,
161 const VkAllocationCallbacks* pAllocator,
162 VkShaderModule* pShaderModule)
163 {
164 RADV_FROM_HANDLE(radv_device, device, _device);
165 struct radv_shader_module *module;
166
167 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
168 assert(pCreateInfo->flags == 0);
169
170 module = vk_alloc2(&device->vk.alloc, pAllocator,
171 sizeof(*module) + pCreateInfo->codeSize, 8,
172 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
173 if (module == NULL)
174 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
175
176 vk_object_base_init(&device->vk, &module->base,
177 VK_OBJECT_TYPE_SHADER_MODULE);
178
179 module->nir = NULL;
180 module->size = pCreateInfo->codeSize;
181 memcpy(module->data, pCreateInfo->pCode, module->size);
182
183 _mesa_sha1_compute(module->data, module->size, module->sha1);
184
185 *pShaderModule = radv_shader_module_to_handle(module);
186
187 return VK_SUCCESS;
188 }
189
190 void radv_DestroyShaderModule(
191 VkDevice _device,
192 VkShaderModule _module,
193 const VkAllocationCallbacks* pAllocator)
194 {
195 RADV_FROM_HANDLE(radv_device, device, _device);
196 RADV_FROM_HANDLE(radv_shader_module, module, _module);
197
198 if (!module)
199 return;
200
201 vk_object_base_finish(&module->base);
202 vk_free2(&device->vk.alloc, pAllocator, module);
203 }
204
205 void
206 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
207 bool allow_copies)
208 {
209 bool progress;
210 unsigned lower_flrp =
211 (shader->options->lower_flrp16 ? 16 : 0) |
212 (shader->options->lower_flrp32 ? 32 : 0) |
213 (shader->options->lower_flrp64 ? 64 : 0);
214
215 do {
216 progress = false;
217
218 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
219 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
220
221 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
222 NIR_PASS_V(shader, nir_lower_pack);
223
224 if (allow_copies) {
225 /* Only run this pass in the first call to
226 * radv_optimize_nir. Later calls assume that we've
227 * lowered away any copy_deref instructions and we
228 * don't want to introduce any more.
229 */
230 NIR_PASS(progress, shader, nir_opt_find_array_copies);
231 }
232
233 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
234 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
235 NIR_PASS(progress, shader, nir_remove_dead_variables,
236 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
237 NULL);
238
239 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
240 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
241
242 NIR_PASS(progress, shader, nir_copy_prop);
243 NIR_PASS(progress, shader, nir_opt_remove_phis);
244 NIR_PASS(progress, shader, nir_opt_dce);
245 if (nir_opt_trivial_continues(shader)) {
246 progress = true;
247 NIR_PASS(progress, shader, nir_copy_prop);
248 NIR_PASS(progress, shader, nir_opt_remove_phis);
249 NIR_PASS(progress, shader, nir_opt_dce);
250 }
251 NIR_PASS(progress, shader, nir_opt_if, true);
252 NIR_PASS(progress, shader, nir_opt_dead_cf);
253 NIR_PASS(progress, shader, nir_opt_cse);
254 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
255 NIR_PASS(progress, shader, nir_opt_constant_folding);
256 NIR_PASS(progress, shader, nir_opt_algebraic);
257
258 if (lower_flrp != 0) {
259 bool lower_flrp_progress = false;
260 NIR_PASS(lower_flrp_progress,
261 shader,
262 nir_lower_flrp,
263 lower_flrp,
264 false /* always_precise */,
265 shader->options->lower_ffma);
266 if (lower_flrp_progress) {
267 NIR_PASS(progress, shader,
268 nir_opt_constant_folding);
269 progress = true;
270 }
271
272 /* Nothing should rematerialize any flrps, so we only
273 * need to do this lowering once.
274 */
275 lower_flrp = 0;
276 }
277
278 NIR_PASS(progress, shader, nir_opt_undef);
279 if (shader->options->max_unroll_iterations) {
280 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
281 }
282 } while (progress && !optimize_conservatively);
283
284 NIR_PASS(progress, shader, nir_opt_conditional_discard);
285 NIR_PASS(progress, shader, nir_opt_shrink_load);
286 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
287 }
288
289 static void
290 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
291 {
292 assert(glsl_type_is_vector_or_scalar(type));
293
294 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
295 unsigned length = glsl_get_vector_elements(type);
296 *size = comp_size * length,
297 *align = comp_size;
298 }
299
300 nir_shader *
301 radv_shader_compile_to_nir(struct radv_device *device,
302 struct radv_shader_module *module,
303 const char *entrypoint_name,
304 gl_shader_stage stage,
305 const VkSpecializationInfo *spec_info,
306 const VkPipelineCreateFlags flags,
307 const struct radv_pipeline_layout *layout,
308 unsigned subgroup_size, unsigned ballot_bit_size)
309 {
310 nir_shader *nir;
311 const nir_shader_compiler_options *nir_options =
312 device->physical_device->use_llvm ? &nir_options_llvm :
313 &nir_options_aco;
314
315 if (module->nir) {
316 /* Some things such as our meta clear/blit code will give us a NIR
317 * shader directly. In that case, we just ignore the SPIR-V entirely
318 * and just use the NIR shader */
319 nir = module->nir;
320 nir->options = nir_options;
321 nir_validate_shader(nir, "in internal shader");
322
323 assert(exec_list_length(&nir->functions) == 1);
324 } else {
325 uint32_t *spirv = (uint32_t *) module->data;
326 assert(module->size % 4 == 0);
327
328 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
329 radv_print_spirv(module->data, module->size, stderr);
330
331 uint32_t num_spec_entries = 0;
332 struct nir_spirv_specialization *spec_entries = NULL;
333 if (spec_info && spec_info->mapEntryCount > 0) {
334 num_spec_entries = spec_info->mapEntryCount;
335 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
336 for (uint32_t i = 0; i < num_spec_entries; i++) {
337 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
338 const void *data = spec_info->pData + entry.offset;
339 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
340
341 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
342 switch (entry.size) {
343 case 8:
344 spec_entries[i].value.u64 = *(const uint64_t *)data;
345 break;
346 case 4:
347 spec_entries[i].value.u32 = *(const uint32_t *)data;
348 break;
349 case 2:
350 spec_entries[i].value.u16 = *(const uint16_t *)data;
351 break;
352 case 1:
353 spec_entries[i].value.u8 = *(const uint8_t *)data;
354 break;
355 default:
356 assert(!"Invalid spec constant size");
357 break;
358 }
359 }
360 }
361 const struct spirv_to_nir_options spirv_options = {
362 .lower_ubo_ssbo_access_to_offsets = true,
363 .caps = {
364 .amd_fragment_mask = true,
365 .amd_gcn_shader = true,
366 .amd_image_gather_bias_lod = true,
367 .amd_image_read_write_lod = true,
368 .amd_shader_ballot = true,
369 .amd_shader_explicit_vertex_parameter = true,
370 .amd_trinary_minmax = true,
371 .demote_to_helper_invocation = true,
372 .derivative_group = true,
373 .descriptor_array_dynamic_indexing = true,
374 .descriptor_array_non_uniform_indexing = true,
375 .descriptor_indexing = true,
376 .device_group = true,
377 .draw_parameters = true,
378 .float_controls = true,
379 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
380 .float64 = true,
381 .geometry_streams = true,
382 .image_ms_array = true,
383 .image_read_without_format = true,
384 .image_write_without_format = true,
385 .int8 = true,
386 .int16 = true,
387 .int64 = true,
388 .int64_atomics = true,
389 .min_lod = true,
390 .multiview = true,
391 .physical_storage_buffer_address = true,
392 .post_depth_coverage = true,
393 .runtime_descriptor_array = true,
394 .shader_clock = true,
395 .shader_viewport_index_layer = true,
396 .stencil_export = true,
397 .storage_8bit = true,
398 .storage_16bit = true,
399 .storage_image_ms = true,
400 .subgroup_arithmetic = true,
401 .subgroup_ballot = true,
402 .subgroup_basic = true,
403 .subgroup_quad = true,
404 .subgroup_shuffle = true,
405 .subgroup_vote = true,
406 .tessellation = true,
407 .transform_feedback = true,
408 .variable_pointers = true,
409 },
410 .ubo_addr_format = nir_address_format_32bit_index_offset,
411 .ssbo_addr_format = nir_address_format_32bit_index_offset,
412 .phys_ssbo_addr_format = nir_address_format_64bit_global,
413 .push_const_addr_format = nir_address_format_logical,
414 .shared_addr_format = nir_address_format_32bit_offset,
415 .frag_coord_is_sysval = true,
416 };
417 nir = spirv_to_nir(spirv, module->size / 4,
418 spec_entries, num_spec_entries,
419 stage, entrypoint_name,
420 &spirv_options, nir_options);
421 assert(nir->info.stage == stage);
422 nir_validate_shader(nir, "after spirv_to_nir");
423
424 free(spec_entries);
425
426 /* We have to lower away local constant initializers right before we
427 * inline functions. That way they get properly initialized at the top
428 * of the function and not at the top of its caller.
429 */
430 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
431 NIR_PASS_V(nir, nir_lower_returns);
432 NIR_PASS_V(nir, nir_inline_functions);
433 NIR_PASS_V(nir, nir_opt_deref);
434
435 /* Pick off the single entrypoint that we want */
436 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
437 if (func->is_entrypoint)
438 func->name = ralloc_strdup(func, "main");
439 else
440 exec_node_remove(&func->node);
441 }
442 assert(exec_list_length(&nir->functions) == 1);
443
444 /* Make sure we lower constant initializers on output variables so that
445 * nir_remove_dead_variables below sees the corresponding stores
446 */
447 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
448
449 /* Now that we've deleted all but the main function, we can go ahead and
450 * lower the rest of the constant initializers.
451 */
452 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
453
454 /* Split member structs. We do this before lower_io_to_temporaries so that
455 * it doesn't lower system values to temporaries by accident.
456 */
457 NIR_PASS_V(nir, nir_split_var_copies);
458 NIR_PASS_V(nir, nir_split_per_member_structs);
459
460 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
461 !device->physical_device->use_llvm)
462 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
463 if (nir->info.stage == MESA_SHADER_FRAGMENT)
464 NIR_PASS_V(nir, nir_lower_input_attachments, true);
465
466 NIR_PASS_V(nir, nir_remove_dead_variables,
467 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
468 NULL);
469
470 NIR_PASS_V(nir, nir_propagate_invariant);
471
472 NIR_PASS_V(nir, nir_lower_system_values);
473 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
474 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
475 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
476 NIR_PASS_V(nir, nir_lower_discard_to_demote);
477
478 nir_lower_doubles_options lower_doubles =
479 nir->options->lower_doubles_options;
480
481 if (device->physical_device->rad_info.chip_class == GFX6) {
482 /* GFX6 doesn't support v_floor_f64 and the precision
483 * of v_fract_f64 which is used to implement 64-bit
484 * floor is less than what Vulkan requires.
485 */
486 lower_doubles |= nir_lower_dfloor;
487 }
488
489 NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles);
490 }
491
492 /* Vulkan uses the separate-shader linking model */
493 nir->info.separate_shader = true;
494
495 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
496
497 if (nir->info.stage == MESA_SHADER_GEOMETRY)
498 nir_lower_gs_intrinsics(nir, true);
499
500 static const nir_lower_tex_options tex_options = {
501 .lower_txp = ~0,
502 .lower_tg4_offsets = true,
503 };
504
505 nir_lower_tex(nir, &tex_options);
506
507 nir_lower_vars_to_ssa(nir);
508
509 if (nir->info.stage == MESA_SHADER_VERTEX ||
510 nir->info.stage == MESA_SHADER_GEOMETRY ||
511 nir->info.stage == MESA_SHADER_FRAGMENT) {
512 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
513 nir_shader_get_entrypoint(nir), true, true);
514 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
515 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
516 nir_shader_get_entrypoint(nir), true, false);
517 }
518
519 nir_split_var_copies(nir);
520
521 nir_lower_global_vars_to_local(nir);
522 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
523 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
524 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
525 .subgroup_size = subgroup_size,
526 .ballot_bit_size = ballot_bit_size,
527 .lower_to_scalar = 1,
528 .lower_subgroup_masks = 1,
529 .lower_shuffle = 1,
530 .lower_shuffle_to_32bit = 1,
531 .lower_vote_eq_to_ballot = 1,
532 .lower_quad_broadcast_dynamic = 1,
533 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
534 });
535
536 nir_lower_load_const_to_scalar(nir);
537
538 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
539 radv_optimize_nir(nir, false, true);
540
541 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
542 * to remove any copies introduced by nir_opt_find_array_copies().
543 */
544 nir_lower_var_copies(nir);
545
546 /* Lower deref operations for compute shared memory. */
547 if (nir->info.stage == MESA_SHADER_COMPUTE) {
548 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
549 nir_var_mem_shared, shared_var_info);
550 NIR_PASS_V(nir, nir_lower_explicit_io,
551 nir_var_mem_shared, nir_address_format_32bit_offset);
552 }
553
554 /* Lower large variables that are always constant with load_constant
555 * intrinsics, which get turned into PC-relative loads from a data
556 * section next to the shader.
557 */
558 NIR_PASS_V(nir, nir_opt_large_constants,
559 glsl_get_natural_size_align_bytes, 16);
560
561 /* Indirect lowering must be called after the radv_optimize_nir() loop
562 * has been called at least once. Otherwise indirect lowering can
563 * bloat the instruction count of the loop and cause it to be
564 * considered too large for unrolling.
565 */
566 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
567 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
568
569 return nir;
570 }
571
572 static int
573 type_size_vec4(const struct glsl_type *type, bool bindless)
574 {
575 return glsl_count_attribute_slots(type, false);
576 }
577
578 static nir_variable *
579 find_layer_in_var(nir_shader *nir)
580 {
581 nir_foreach_variable(var, &nir->inputs) {
582 if (var->data.location == VARYING_SLOT_LAYER) {
583 return var;
584 }
585 }
586
587 nir_variable *var =
588 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
589 var->data.location = VARYING_SLOT_LAYER;
590 var->data.interpolation = INTERP_MODE_FLAT;
591 return var;
592 }
593
594 /* We use layered rendering to implement multiview, which means we need to map
595 * view_index to gl_Layer. The attachment lowering also uses needs to know the
596 * layer so that it can sample from the correct layer. The code generates a
597 * load from the layer_id sysval, but since we don't have a way to get at this
598 * information from the fragment shader, we also need to lower this to the
599 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
600 * slot, before lowering io, so that nir_assign_var_locations() will give the
601 * LAYER varying the correct driver_location.
602 */
603
604 static bool
605 lower_view_index(nir_shader *nir)
606 {
607 bool progress = false;
608 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
609 nir_builder b;
610 nir_builder_init(&b, entry);
611
612 nir_variable *layer = NULL;
613 nir_foreach_block(block, entry) {
614 nir_foreach_instr_safe(instr, block) {
615 if (instr->type != nir_instr_type_intrinsic)
616 continue;
617
618 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
619 if (load->intrinsic != nir_intrinsic_load_view_index &&
620 load->intrinsic != nir_intrinsic_load_layer_id)
621 continue;
622
623 if (!layer)
624 layer = find_layer_in_var(nir);
625
626 b.cursor = nir_before_instr(instr);
627 nir_ssa_def *def = nir_load_var(&b, layer);
628 nir_ssa_def_rewrite_uses(&load->dest.ssa,
629 nir_src_for_ssa(def));
630
631 nir_instr_remove(instr);
632 progress = true;
633 }
634 }
635
636 return progress;
637 }
638
639 void
640 radv_lower_fs_io(nir_shader *nir)
641 {
642 NIR_PASS_V(nir, lower_view_index);
643 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
644 MESA_SHADER_FRAGMENT);
645
646 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
647
648 /* This pass needs actual constants */
649 nir_opt_constant_folding(nir);
650
651 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
652 }
653
654
655 static void *
656 radv_alloc_shader_memory(struct radv_device *device,
657 struct radv_shader_variant *shader)
658 {
659 mtx_lock(&device->shader_slab_mutex);
660 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
661 uint64_t offset = 0;
662 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
663 if (s->bo_offset - offset >= shader->code_size) {
664 shader->bo = slab->bo;
665 shader->bo_offset = offset;
666 list_addtail(&shader->slab_list, &s->slab_list);
667 mtx_unlock(&device->shader_slab_mutex);
668 return slab->ptr + offset;
669 }
670 offset = align_u64(s->bo_offset + s->code_size, 256);
671 }
672 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
673 shader->bo = slab->bo;
674 shader->bo_offset = offset;
675 list_addtail(&shader->slab_list, &slab->shaders);
676 mtx_unlock(&device->shader_slab_mutex);
677 return slab->ptr + offset;
678 }
679 }
680
681 mtx_unlock(&device->shader_slab_mutex);
682 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
683
684 slab->size = MAX2(256 * 1024, shader->code_size);
685 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
686 RADEON_DOMAIN_VRAM,
687 RADEON_FLAG_NO_INTERPROCESS_SHARING |
688 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
689 0 : RADEON_FLAG_READ_ONLY),
690 RADV_BO_PRIORITY_SHADER);
691 if (!slab->bo) {
692 free(slab);
693 return NULL;
694 }
695
696 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
697 if (!slab->ptr) {
698 device->ws->buffer_destroy(slab->bo);
699 free(slab);
700 return NULL;
701 }
702
703 list_inithead(&slab->shaders);
704
705 mtx_lock(&device->shader_slab_mutex);
706 list_add(&slab->slabs, &device->shader_slabs);
707
708 shader->bo = slab->bo;
709 shader->bo_offset = 0;
710 list_add(&shader->slab_list, &slab->shaders);
711 mtx_unlock(&device->shader_slab_mutex);
712 return slab->ptr;
713 }
714
715 void
716 radv_destroy_shader_slabs(struct radv_device *device)
717 {
718 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
719 device->ws->buffer_destroy(slab->bo);
720 free(slab);
721 }
722 mtx_destroy(&device->shader_slab_mutex);
723 }
724
725 /* For the UMR disassembler. */
726 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
727 #define DEBUGGER_NUM_MARKERS 5
728
729 static unsigned
730 radv_get_shader_binary_size(size_t code_size)
731 {
732 return code_size + DEBUGGER_NUM_MARKERS * 4;
733 }
734
735 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
736 const struct ac_shader_config *config_in,
737 const struct radv_shader_info *info,
738 gl_shader_stage stage,
739 struct ac_shader_config *config_out)
740 {
741 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
742 unsigned vgpr_comp_cnt = 0;
743 unsigned num_input_vgprs = info->num_input_vgprs;
744
745 if (stage == MESA_SHADER_FRAGMENT) {
746 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
747 }
748
749 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
750 /* +3 for scratch wave offset and VCC */
751 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
752 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
753 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
754 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
755 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
756 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
757
758 *config_out = *config_in;
759 config_out->num_vgprs = num_vgprs;
760 config_out->num_sgprs = num_sgprs;
761 config_out->num_shared_vgprs = num_shared_vgprs;
762
763 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
764 S_00B12C_SCRATCH_EN(scratch_enabled);
765
766 if (!pdevice->use_ngg_streamout) {
767 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
768 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
769 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
770 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
771 S_00B12C_SO_EN(!!info->so.num_outputs);
772 }
773
774 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
775 (info->wave_size == 32 ? 8 : 4)) |
776 S_00B848_DX10_CLAMP(1) |
777 S_00B848_FLOAT_MODE(config_out->float_mode);
778
779 if (pdevice->rad_info.chip_class >= GFX10) {
780 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
781 } else {
782 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
783 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
784 }
785
786 switch (stage) {
787 case MESA_SHADER_TESS_EVAL:
788 if (info->is_ngg) {
789 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
790 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
791 } else if (info->tes.as_es) {
792 assert(pdevice->rad_info.chip_class <= GFX8);
793 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
794
795 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
796 } else {
797 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
798 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
799
800 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
801 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
802 }
803 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
804 break;
805 case MESA_SHADER_TESS_CTRL:
806 if (pdevice->rad_info.chip_class >= GFX9) {
807 /* We need at least 2 components for LS.
808 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
809 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
810 */
811 if (pdevice->rad_info.chip_class >= GFX10) {
812 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
813 } else {
814 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
815 }
816 } else {
817 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
818 }
819 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
820 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
821 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
822 break;
823 case MESA_SHADER_VERTEX:
824 if (info->is_ngg) {
825 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
826 } else if (info->vs.as_ls) {
827 assert(pdevice->rad_info.chip_class <= GFX8);
828 /* We need at least 2 components for LS.
829 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
830 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
831 */
832 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
833 } else if (info->vs.as_es) {
834 assert(pdevice->rad_info.chip_class <= GFX8);
835 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
836 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
837 } else {
838 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
839 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
840 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
841 */
842 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
843 vgpr_comp_cnt = 3;
844 } else if (info->vs.export_prim_id) {
845 vgpr_comp_cnt = 2;
846 } else if (info->vs.needs_instance_id) {
847 vgpr_comp_cnt = 1;
848 } else {
849 vgpr_comp_cnt = 0;
850 }
851
852 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
853 }
854 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
855 break;
856 case MESA_SHADER_FRAGMENT:
857 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
858 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
859 break;
860 case MESA_SHADER_GEOMETRY:
861 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
862 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
863 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
864 break;
865 case MESA_SHADER_COMPUTE:
866 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
867 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
868 config_out->rsrc2 |=
869 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
870 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
871 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
872 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
873 info->cs.uses_thread_id[1] ? 1 : 0) |
874 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
875 S_00B84C_LDS_SIZE(config_in->lds_size);
876 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
877
878 break;
879 default:
880 unreachable("unsupported shader type");
881 break;
882 }
883
884 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
885 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
886 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
887 gl_shader_stage es_stage = stage;
888 if (stage == MESA_SHADER_GEOMETRY)
889 es_stage = info->gs.es_type;
890
891 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
892 if (es_stage == MESA_SHADER_VERTEX) {
893 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
894 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
895 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
896 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
897 } else
898 unreachable("Unexpected ES shader stage");
899
900 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
901 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
902 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
903 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
904 } else if (info->uses_prim_id) {
905 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
906 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
907 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
908 } else {
909 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
910 }
911
912 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
913 S_00B228_WGP_MODE(1);
914 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
915 S_00B22C_LDS_SIZE(config_in->lds_size) |
916 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
917 } else if (pdevice->rad_info.chip_class >= GFX9 &&
918 stage == MESA_SHADER_GEOMETRY) {
919 unsigned es_type = info->gs.es_type;
920 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
921
922 if (es_type == MESA_SHADER_VERTEX) {
923 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
924 if (info->vs.needs_instance_id) {
925 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
926 } else {
927 es_vgpr_comp_cnt = 0;
928 }
929 } else if (es_type == MESA_SHADER_TESS_EVAL) {
930 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
931 } else {
932 unreachable("invalid shader ES type");
933 }
934
935 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
936 * VGPR[0:4] are always loaded.
937 */
938 if (info->uses_invocation_id) {
939 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
940 } else if (info->uses_prim_id) {
941 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
942 } else if (info->gs.vertices_in >= 3) {
943 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
944 } else {
945 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
946 }
947
948 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
949 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
950 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
951 } else if (pdevice->rad_info.chip_class >= GFX9 &&
952 stage == MESA_SHADER_TESS_CTRL) {
953 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
954 } else {
955 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
956 }
957 }
958
959 struct radv_shader_variant *
960 radv_shader_variant_create(struct radv_device *device,
961 const struct radv_shader_binary *binary,
962 bool keep_shader_info)
963 {
964 struct ac_shader_config config = {0};
965 struct ac_rtld_binary rtld_binary = {0};
966 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
967 if (!variant)
968 return NULL;
969
970 variant->ref_count = 1;
971
972 if (binary->type == RADV_BINARY_TYPE_RTLD) {
973 struct ac_rtld_symbol lds_symbols[2];
974 unsigned num_lds_symbols = 0;
975 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
976 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
977
978 if (device->physical_device->rad_info.chip_class >= GFX9 &&
979 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
980 !binary->is_gs_copy_shader) {
981 /* We add this symbol even on LLVM <= 8 to ensure that
982 * shader->config.lds_size is set correctly below.
983 */
984 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
985 sym->name = "esgs_ring";
986 sym->size = binary->info.ngg_info.esgs_ring_size;
987 sym->align = 64 * 1024;
988 }
989
990 if (binary->info.is_ngg &&
991 binary->stage == MESA_SHADER_GEOMETRY) {
992 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
993 sym->name = "ngg_emit";
994 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
995 sym->align = 4;
996 }
997
998 struct ac_rtld_open_info open_info = {
999 .info = &device->physical_device->rad_info,
1000 .shader_type = binary->stage,
1001 .wave_size = binary->info.wave_size,
1002 .num_parts = 1,
1003 .elf_ptrs = &elf_data,
1004 .elf_sizes = &elf_size,
1005 .num_shared_lds_symbols = num_lds_symbols,
1006 .shared_lds_symbols = lds_symbols,
1007 };
1008
1009 if (!ac_rtld_open(&rtld_binary, open_info)) {
1010 free(variant);
1011 return NULL;
1012 }
1013
1014 if (!ac_rtld_read_config(&device->physical_device->rad_info,
1015 &rtld_binary, &config)) {
1016 ac_rtld_close(&rtld_binary);
1017 free(variant);
1018 return NULL;
1019 }
1020
1021 if (rtld_binary.lds_size > 0) {
1022 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1023 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1024 }
1025
1026 variant->code_size = rtld_binary.rx_size;
1027 variant->exec_size = rtld_binary.exec_size;
1028 } else {
1029 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1030 config = ((struct radv_shader_binary_legacy *)binary)->config;
1031 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1032 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1033 }
1034
1035 variant->info = binary->info;
1036 radv_postprocess_config(device->physical_device, &config, &binary->info,
1037 binary->stage, &variant->config);
1038
1039 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1040 if (!dest_ptr) {
1041 if (binary->type == RADV_BINARY_TYPE_RTLD)
1042 ac_rtld_close(&rtld_binary);
1043 free(variant);
1044 return NULL;
1045 }
1046
1047 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1048 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1049 struct ac_rtld_upload_info info = {
1050 .binary = &rtld_binary,
1051 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1052 .rx_ptr = dest_ptr,
1053 };
1054
1055 if (!ac_rtld_upload(&info)) {
1056 radv_shader_variant_destroy(device, variant);
1057 ac_rtld_close(&rtld_binary);
1058 return NULL;
1059 }
1060
1061 if (keep_shader_info ||
1062 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1063 const char *disasm_data;
1064 size_t disasm_size;
1065 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1066 radv_shader_variant_destroy(device, variant);
1067 ac_rtld_close(&rtld_binary);
1068 return NULL;
1069 }
1070
1071 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1072 variant->disasm_string = malloc(disasm_size + 1);
1073 memcpy(variant->disasm_string, disasm_data, disasm_size);
1074 variant->disasm_string[disasm_size] = 0;
1075 }
1076
1077 ac_rtld_close(&rtld_binary);
1078 } else {
1079 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1080 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1081
1082 /* Add end-of-code markers for the UMR disassembler. */
1083 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1084 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1085 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1086
1087 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1088 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1089
1090 if (bin->stats_size) {
1091 variant->statistics = calloc(bin->stats_size, 1);
1092 memcpy(variant->statistics, bin->data, bin->stats_size);
1093 }
1094 }
1095 return variant;
1096 }
1097
1098 static char *
1099 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1100 int shader_count)
1101 {
1102 char *data = NULL;
1103 char *ret = NULL;
1104 size_t size = 0;
1105 FILE *f = open_memstream(&data, &size);
1106 if (f) {
1107 for (int i = 0; i < shader_count; ++i)
1108 nir_print_shader(shaders[i], f);
1109 fclose(f);
1110 }
1111
1112 ret = malloc(size + 1);
1113 if (ret) {
1114 memcpy(ret, data, size);
1115 ret[size] = 0;
1116 }
1117 free(data);
1118 return ret;
1119 }
1120
1121 static struct radv_shader_variant *
1122 shader_variant_compile(struct radv_device *device,
1123 struct radv_shader_module *module,
1124 struct nir_shader * const *shaders,
1125 int shader_count,
1126 gl_shader_stage stage,
1127 struct radv_shader_info *info,
1128 struct radv_nir_compiler_options *options,
1129 bool gs_copy_shader,
1130 bool keep_shader_info,
1131 bool keep_statistic_info,
1132 struct radv_shader_binary **binary_out)
1133 {
1134 enum radeon_family chip_family = device->physical_device->rad_info.family;
1135 struct radv_shader_binary *binary = NULL;
1136
1137 options->family = chip_family;
1138 options->chip_class = device->physical_device->rad_info.chip_class;
1139 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1140 options->dump_preoptir = options->dump_shader &&
1141 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1142 options->record_ir = keep_shader_info;
1143 options->record_stats = keep_statistic_info;
1144 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1145 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1146 options->address32_hi = device->physical_device->rad_info.address32_hi;
1147 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1148 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1149 options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup;
1150
1151 struct radv_shader_args args = {};
1152 args.options = options;
1153 args.shader_info = info;
1154 args.is_gs_copy_shader = gs_copy_shader;
1155 radv_declare_shader_args(&args,
1156 gs_copy_shader ? MESA_SHADER_VERTEX
1157 : shaders[shader_count - 1]->info.stage,
1158 shader_count >= 2,
1159 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1160 : MESA_SHADER_VERTEX);
1161
1162 if (device->physical_device->use_llvm ||
1163 options->dump_shader || options->record_ir)
1164 ac_init_llvm_once();
1165
1166 if (device->physical_device->use_llvm) {
1167 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1168 } else {
1169 aco_compile_shader(shader_count, shaders, &binary, &args);
1170 }
1171
1172 binary->info = *info;
1173
1174 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1175 keep_shader_info);
1176 if (!variant) {
1177 free(binary);
1178 return NULL;
1179 }
1180
1181 if (options->dump_shader) {
1182 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1183 for (int i = 1; i < shader_count; ++i)
1184 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1185
1186 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1187 }
1188
1189
1190 if (keep_shader_info) {
1191 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1192 if (!gs_copy_shader && !module->nir) {
1193 variant->spirv = malloc(module->size);
1194 if (!variant->spirv) {
1195 free(variant);
1196 free(binary);
1197 return NULL;
1198 }
1199
1200 memcpy(variant->spirv, module->data, module->size);
1201 variant->spirv_size = module->size;
1202 }
1203 }
1204
1205 if (binary_out)
1206 *binary_out = binary;
1207 else
1208 free(binary);
1209
1210 return variant;
1211 }
1212
1213 struct radv_shader_variant *
1214 radv_shader_variant_compile(struct radv_device *device,
1215 struct radv_shader_module *module,
1216 struct nir_shader *const *shaders,
1217 int shader_count,
1218 struct radv_pipeline_layout *layout,
1219 const struct radv_shader_variant_key *key,
1220 struct radv_shader_info *info,
1221 bool keep_shader_info, bool keep_statistic_info,
1222 struct radv_shader_binary **binary_out)
1223 {
1224 struct radv_nir_compiler_options options = {0};
1225
1226 options.layout = layout;
1227 if (key)
1228 options.key = *key;
1229
1230 options.explicit_scratch_args = !device->physical_device->use_llvm;
1231 options.robust_buffer_access = device->robust_buffer_access;
1232
1233 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1234 &options, false, keep_shader_info, keep_statistic_info, binary_out);
1235 }
1236
1237 struct radv_shader_variant *
1238 radv_create_gs_copy_shader(struct radv_device *device,
1239 struct nir_shader *shader,
1240 struct radv_shader_info *info,
1241 struct radv_shader_binary **binary_out,
1242 bool keep_shader_info, bool keep_statistic_info,
1243 bool multiview)
1244 {
1245 struct radv_nir_compiler_options options = {0};
1246
1247 options.explicit_scratch_args = !device->physical_device->use_llvm;
1248 options.key.has_multiview_view_index = multiview;
1249
1250 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1251 info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
1252 }
1253
1254 void
1255 radv_shader_variant_destroy(struct radv_device *device,
1256 struct radv_shader_variant *variant)
1257 {
1258 if (!p_atomic_dec_zero(&variant->ref_count))
1259 return;
1260
1261 mtx_lock(&device->shader_slab_mutex);
1262 list_del(&variant->slab_list);
1263 mtx_unlock(&device->shader_slab_mutex);
1264
1265 free(variant->spirv);
1266 free(variant->nir_string);
1267 free(variant->disasm_string);
1268 free(variant->ir_string);
1269 free(variant->statistics);
1270 free(variant);
1271 }
1272
1273 const char *
1274 radv_get_shader_name(struct radv_shader_info *info,
1275 gl_shader_stage stage)
1276 {
1277 switch (stage) {
1278 case MESA_SHADER_VERTEX:
1279 if (info->vs.as_ls)
1280 return "Vertex Shader as LS";
1281 else if (info->vs.as_es)
1282 return "Vertex Shader as ES";
1283 else if (info->is_ngg)
1284 return "Vertex Shader as ESGS";
1285 else
1286 return "Vertex Shader as VS";
1287 case MESA_SHADER_TESS_CTRL:
1288 return "Tessellation Control Shader";
1289 case MESA_SHADER_TESS_EVAL:
1290 if (info->tes.as_es)
1291 return "Tessellation Evaluation Shader as ES";
1292 else if (info->is_ngg)
1293 return "Tessellation Evaluation Shader as ESGS";
1294 else
1295 return "Tessellation Evaluation Shader as VS";
1296 case MESA_SHADER_GEOMETRY:
1297 return "Geometry Shader";
1298 case MESA_SHADER_FRAGMENT:
1299 return "Pixel Shader";
1300 case MESA_SHADER_COMPUTE:
1301 return "Compute Shader";
1302 default:
1303 return "Unknown shader";
1304 };
1305 }
1306
1307 unsigned
1308 radv_get_max_workgroup_size(enum chip_class chip_class,
1309 gl_shader_stage stage,
1310 const unsigned *sizes)
1311 {
1312 switch (stage) {
1313 case MESA_SHADER_TESS_CTRL:
1314 return chip_class >= GFX7 ? 128 : 64;
1315 case MESA_SHADER_GEOMETRY:
1316 return chip_class >= GFX9 ? 128 : 64;
1317 case MESA_SHADER_COMPUTE:
1318 break;
1319 default:
1320 return 0;
1321 }
1322
1323 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1324 return max_workgroup_size;
1325 }
1326
1327 unsigned
1328 radv_get_max_waves(struct radv_device *device,
1329 struct radv_shader_variant *variant,
1330 gl_shader_stage stage)
1331 {
1332 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1333 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1334 uint8_t wave_size = variant->info.wave_size;
1335 struct ac_shader_config *conf = &variant->config;
1336 unsigned max_simd_waves;
1337 unsigned lds_per_wave = 0;
1338
1339 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1340
1341 if (stage == MESA_SHADER_FRAGMENT) {
1342 lds_per_wave = conf->lds_size * lds_increment +
1343 align(variant->info.ps.num_interp * 48,
1344 lds_increment);
1345 } else if (stage == MESA_SHADER_COMPUTE) {
1346 unsigned max_workgroup_size =
1347 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1348 lds_per_wave = (conf->lds_size * lds_increment) /
1349 DIV_ROUND_UP(max_workgroup_size, wave_size);
1350 }
1351
1352 if (conf->num_sgprs) {
1353 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1354 max_simd_waves =
1355 MIN2(max_simd_waves,
1356 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1357 sgprs);
1358 }
1359
1360 if (conf->num_vgprs) {
1361 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1362 max_simd_waves =
1363 MIN2(max_simd_waves,
1364 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1365 }
1366
1367 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1368 if (lds_per_wave)
1369 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1370
1371 return max_simd_waves;
1372 }
1373
1374 static void
1375 generate_shader_stats(struct radv_device *device,
1376 struct radv_shader_variant *variant,
1377 gl_shader_stage stage,
1378 struct _mesa_string_buffer *buf)
1379 {
1380 struct ac_shader_config *conf = &variant->config;
1381 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1382
1383 if (stage == MESA_SHADER_FRAGMENT) {
1384 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1385 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1386 "SPI_PS_INPUT_ENA = 0x%04x\n",
1387 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1388 }
1389
1390 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1391 "SGPRS: %d\n"
1392 "VGPRS: %d\n"
1393 "Spilled SGPRs: %d\n"
1394 "Spilled VGPRs: %d\n"
1395 "PrivMem VGPRS: %d\n"
1396 "Code Size: %d bytes\n"
1397 "LDS: %d blocks\n"
1398 "Scratch: %d bytes per wave\n"
1399 "Max Waves: %d\n",
1400 conf->num_sgprs, conf->num_vgprs,
1401 conf->spilled_sgprs, conf->spilled_vgprs,
1402 variant->info.private_mem_vgprs, variant->exec_size,
1403 conf->lds_size, conf->scratch_bytes_per_wave,
1404 max_simd_waves);
1405
1406 if (variant->statistics) {
1407 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1408 for (unsigned i = 0; i < variant->statistics->count; i++) {
1409 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1410 uint32_t value = variant->statistics->values[i];
1411 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1412 }
1413 }
1414
1415 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1416 }
1417
1418 void
1419 radv_shader_dump_stats(struct radv_device *device,
1420 struct radv_shader_variant *variant,
1421 gl_shader_stage stage,
1422 FILE *file)
1423 {
1424 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1425
1426 generate_shader_stats(device, variant, stage, buf);
1427
1428 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1429 fprintf(file, "%s", buf->buf);
1430
1431 _mesa_string_buffer_destroy(buf);
1432 }
1433
1434 VkResult
1435 radv_GetShaderInfoAMD(VkDevice _device,
1436 VkPipeline _pipeline,
1437 VkShaderStageFlagBits shaderStage,
1438 VkShaderInfoTypeAMD infoType,
1439 size_t* pInfoSize,
1440 void* pInfo)
1441 {
1442 RADV_FROM_HANDLE(radv_device, device, _device);
1443 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1444 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1445 struct radv_shader_variant *variant = pipeline->shaders[stage];
1446 struct _mesa_string_buffer *buf;
1447 VkResult result = VK_SUCCESS;
1448
1449 /* Spec doesn't indicate what to do if the stage is invalid, so just
1450 * return no info for this. */
1451 if (!variant)
1452 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1453
1454 switch (infoType) {
1455 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1456 if (!pInfo) {
1457 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1458 } else {
1459 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1460 struct ac_shader_config *conf = &variant->config;
1461
1462 VkShaderStatisticsInfoAMD statistics = {};
1463 statistics.shaderStageMask = shaderStage;
1464 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1465 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1466 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1467
1468 if (stage == MESA_SHADER_COMPUTE) {
1469 unsigned *local_size = variant->info.cs.block_size;
1470 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1471
1472 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1473 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1474
1475 statistics.computeWorkGroupSize[0] = local_size[0];
1476 statistics.computeWorkGroupSize[1] = local_size[1];
1477 statistics.computeWorkGroupSize[2] = local_size[2];
1478 } else {
1479 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1480 }
1481
1482 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1483 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1484 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1485 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1486 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1487
1488 size_t size = *pInfoSize;
1489 *pInfoSize = sizeof(statistics);
1490
1491 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1492
1493 if (size < *pInfoSize)
1494 result = VK_INCOMPLETE;
1495 }
1496
1497 break;
1498 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1499 buf = _mesa_string_buffer_create(NULL, 1024);
1500
1501 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1502 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1503 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1504 generate_shader_stats(device, variant, stage, buf);
1505
1506 /* Need to include the null terminator. */
1507 size_t length = buf->length + 1;
1508
1509 if (!pInfo) {
1510 *pInfoSize = length;
1511 } else {
1512 size_t size = *pInfoSize;
1513 *pInfoSize = length;
1514
1515 memcpy(pInfo, buf->buf, MIN2(size, length));
1516
1517 if (size < length)
1518 result = VK_INCOMPLETE;
1519 }
1520
1521 _mesa_string_buffer_destroy(buf);
1522 break;
1523 default:
1524 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1525 result = VK_ERROR_FEATURE_NOT_PRESENT;
1526 break;
1527 }
1528
1529 return result;
1530 }