src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "radv_shader_helper.h"
  34 #include "nir/nir.h"
  35 #include "nir/nir_builder.h"
  36 #include "spirv/nir_spirv.h"
  37
  38 #include <llvm-c/Core.h>
  39 #include <llvm-c/TargetMachine.h>
  40 #include <llvm-c/Support.h>
  41
  42 #include "sid.h"
  43 #include "gfx9d.h"
  44 #include "ac_binary.h"
  45 #include "ac_llvm_util.h"
  46 #include "ac_nir_to_llvm.h"
  47 #include "vk_format.h"
  48 #include "util/debug.h"
  49 #include "ac_exp_param.h"
  50
  51 #include "util/string_buffer.h"
  52
  53 static const struct nir_shader_compiler_options nir_options = {
  54         .vertex_id_zero_based = true,
  55         .lower_scmp = true,
  56         .lower_flrp32 = true,
  57         .lower_flrp64 = true,
  58         .lower_device_index_to_zero = true,
  59         .lower_fsat = true,
  60         .lower_fdiv = true,
  61         .lower_sub = true,
  62         .lower_pack_snorm_2x16 = true,
  63         .lower_pack_snorm_4x8 = true,
  64         .lower_pack_unorm_2x16 = true,
  65         .lower_pack_unorm_4x8 = true,
  66         .lower_unpack_snorm_2x16 = true,
  67         .lower_unpack_snorm_4x8 = true,
  68         .lower_unpack_unorm_2x16 = true,
  69         .lower_unpack_unorm_4x8 = true,
  70         .lower_extract_byte = true,
  71         .lower_extract_word = true,
  72         .lower_ffma = true,
  73         .lower_fpow = true,
  74         .max_unroll_iterations = 32
  75 };
  76
  77 VkResult radv_CreateShaderModule(
  78         VkDevice                                    _device,
  79         const VkShaderModuleCreateInfo*             pCreateInfo,
  80         const VkAllocationCallbacks*                pAllocator,
  81         VkShaderModule*                             pShaderModule)
  82 {
  83         RADV_FROM_HANDLE(radv_device, device, _device);
  84         struct radv_shader_module *module;
  85
  86         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  87         assert(pCreateInfo->flags == 0);
  88
  89         module = vk_alloc2(&device->alloc, pAllocator,
  90                              sizeof(*module) + pCreateInfo->codeSize, 8,
  91                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  92         if (module == NULL)
  93                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
  94
  95         module->nir = NULL;
  96         module->size = pCreateInfo->codeSize;
  97         memcpy(module->data, pCreateInfo->pCode, module->size);
  98
  99         _mesa_sha1_compute(module->data, module->size, module->sha1);
 100
 101         *pShaderModule = radv_shader_module_to_handle(module);
 102
 103         return VK_SUCCESS;
 104 }
 105
 106 void radv_DestroyShaderModule(
 107         VkDevice                                    _device,
 108         VkShaderModule                              _module,
 109         const VkAllocationCallbacks*                pAllocator)
 110 {
 111         RADV_FROM_HANDLE(radv_device, device, _device);
 112         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 113
 114         if (!module)
 115                 return;
 116
 117         vk_free2(&device->alloc, pAllocator, module);
 118 }
 119
 120 void
 121 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively)
 122 {
 123         bool progress;
 124
 125         do {
 126                 progress = false;
 127
 128                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 129                 NIR_PASS_V(shader, nir_lower_pack);
 130
 131                 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
 132                 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
 133
 134                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 135                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 136
 137                 NIR_PASS(progress, shader, nir_copy_prop);
 138                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 139                 NIR_PASS(progress, shader, nir_opt_dce);
 140                 if (nir_opt_trivial_continues(shader)) {
 141                         progress = true;
 142                         NIR_PASS(progress, shader, nir_copy_prop);
 143                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 144                         NIR_PASS(progress, shader, nir_opt_dce);
 145                 }
 146                 NIR_PASS(progress, shader, nir_opt_if);
 147                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 148                 NIR_PASS(progress, shader, nir_opt_cse);
 149                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 150                 NIR_PASS(progress, shader, nir_opt_algebraic);
 151                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 152                 NIR_PASS(progress, shader, nir_opt_undef);
 153                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 154                 if (shader->options->max_unroll_iterations) {
 155                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 156                 }
 157         } while (progress && !optimize_conservatively);
 158
 159         NIR_PASS(progress, shader, nir_opt_shrink_load);
 160         NIR_PASS(progress, shader, nir_opt_move_load_ubo);
 161 }
 162
 163 nir_shader *
 164 radv_shader_compile_to_nir(struct radv_device *device,
 165                            struct radv_shader_module *module,
 166                            const char *entrypoint_name,
 167                            gl_shader_stage stage,
 168                            const VkSpecializationInfo *spec_info,
 169                            const VkPipelineCreateFlags flags)
 170 {
 171         nir_shader *nir;
 172         nir_function *entry_point;
 173         if (module->nir) {
 174                 /* Some things such as our meta clear/blit code will give us a NIR
 175                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 176                  * and just use the NIR shader */
 177                 nir = module->nir;
 178                 nir->options = &nir_options;
 179                 nir_validate_shader(nir);
 180
 181                 assert(exec_list_length(&nir->functions) == 1);
 182                 struct exec_node *node = exec_list_get_head(&nir->functions);
 183                 entry_point = exec_node_data(nir_function, node, node);
 184         } else {
 185                 uint32_t *spirv = (uint32_t *) module->data;
 186                 assert(module->size % 4 == 0);
 187
 188                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 189                         radv_print_spirv(spirv, module->size, stderr);
 190
 191                 uint32_t num_spec_entries = 0;
 192                 struct nir_spirv_specialization *spec_entries = NULL;
 193                 if (spec_info && spec_info->mapEntryCount > 0) {
 194                         num_spec_entries = spec_info->mapEntryCount;
 195                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 196                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 197                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 198                                 const void *data = spec_info->pData + entry.offset;
 199                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 200
 201                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 202                                 if (spec_info->dataSize == 8)
 203                                         spec_entries[i].data64 = *(const uint64_t *)data;
 204                                 else
 205                                         spec_entries[i].data32 = *(const uint32_t *)data;
 206                         }
 207                 }
 208                 const struct spirv_to_nir_options spirv_options = {
 209                         .caps = {
 210                                 .device_group = true,
 211                                 .draw_parameters = true,
 212                                 .float64 = true,
 213                                 .image_read_without_format = true,
 214                                 .image_write_without_format = true,
 215                                 .tessellation = true,
 216                                 .int64 = true,
 217                                 .int16 = true,
 218                                 .multiview = true,
 219                                 .subgroup_arithmetic = true,
 220                                 .subgroup_ballot = true,
 221                                 .subgroup_basic = true,
 222                                 .subgroup_quad = true,
 223                                 .subgroup_shuffle = true,
 224                                 .subgroup_vote = true,
 225                                 .variable_pointers = true,
 226                                 .gcn_shader = true,
 227                                 .trinary_minmax = true,
 228                                 .shader_viewport_index_layer = true,
 229                                 .descriptor_array_dynamic_indexing = true,
 230                                 .runtime_descriptor_array = true,
 231                                 .stencil_export = true,
 232                                 .storage_16bit = true,
 233                         },
 234                 };
 235                 entry_point = spirv_to_nir(spirv, module->size / 4,
 236                                            spec_entries, num_spec_entries,
 237                                            stage, entrypoint_name,
 238                                            &spirv_options, &nir_options);
 239                 nir = entry_point->shader;
 240                 assert(nir->info.stage == stage);
 241                 nir_validate_shader(nir);
 242
 243                 free(spec_entries);
 244
 245                 /* We have to lower away local constant initializers right before we
 246                  * inline functions.  That way they get properly initialized at the top
 247                  * of the function and not at the top of its caller.
 248                  */
 249                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 250                 NIR_PASS_V(nir, nir_lower_returns);
 251                 NIR_PASS_V(nir, nir_inline_functions);
 252                 NIR_PASS_V(nir, nir_copy_prop);
 253
 254                 /* Pick off the single entrypoint that we want */
 255                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 256                         if (func != entry_point)
 257                                 exec_node_remove(&func->node);
 258                 }
 259                 assert(exec_list_length(&nir->functions) == 1);
 260                 entry_point->name = ralloc_strdup(entry_point, "main");
 261
 262                 /* Make sure we lower constant initializers on output variables so that
 263                  * nir_remove_dead_variables below sees the corresponding stores
 264                  */
 265                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
 266
 267                 /* Now that we've deleted all but the main function, we can go ahead and
 268                  * lower the rest of the constant initializers.
 269                  */
 270                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 271
 272                 /* Split member structs.  We do this before lower_io_to_temporaries so that
 273                  * it doesn't lower system values to temporaries by accident.
 274                  */
 275                 NIR_PASS_V(nir, nir_split_var_copies);
 276                 NIR_PASS_V(nir, nir_split_per_member_structs);
 277
 278                 NIR_PASS_V(nir, nir_remove_dead_variables,
 279                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 280
 281                 NIR_PASS_V(nir, nir_lower_system_values);
 282                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 283         }
 284
 285         /* Vulkan uses the separate-shader linking model */
 286         nir->info.separate_shader = true;
 287
 288         nir_shader_gather_info(nir, entry_point->impl);
 289
 290         static const nir_lower_tex_options tex_options = {
 291           .lower_txp = ~0,
 292         };
 293
 294         nir_lower_tex(nir, &tex_options);
 295
 296         nir_lower_vars_to_ssa(nir);
 297
 298         if (nir->info.stage == MESA_SHADER_VERTEX ||
 299             nir->info.stage == MESA_SHADER_GEOMETRY) {
 300                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 301                            nir_shader_get_entrypoint(nir), true, true);
 302         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
 303                    nir->info.stage == MESA_SHADER_FRAGMENT) {
 304                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 305                            nir_shader_get_entrypoint(nir), true, false);
 306         }
 307
 308         nir_split_var_copies(nir);
 309         nir_lower_var_copies(nir);
 310
 311         nir_lower_global_vars_to_local(nir);
 312         nir_remove_dead_variables(nir, nir_var_local);
 313         nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 314                         .subgroup_size = 64,
 315                         .ballot_bit_size = 64,
 316                         .lower_to_scalar = 1,
 317                         .lower_subgroup_masks = 1,
 318                         .lower_shuffle = 1,
 319                         .lower_shuffle_to_32bit = 1,
 320                         .lower_vote_eq_to_ballot = 1,
 321                 });
 322
 323         nir_lower_load_const_to_scalar(nir);
 324
 325         if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
 326                 radv_optimize_nir(nir, false);
 327
 328         /* Indirect lowering must be called after the radv_optimize_nir() loop
 329          * has been called at least once. Otherwise indirect lowering can
 330          * bloat the instruction count of the loop and cause it to be
 331          * considered too large for unrolling.
 332          */
 333         ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
 334         radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT);
 335
 336         return nir;
 337 }
 338
 339 void *
 340 radv_alloc_shader_memory(struct radv_device *device,
 341                          struct radv_shader_variant *shader)
 342 {
 343         mtx_lock(&device->shader_slab_mutex);
 344         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 345                 uint64_t offset = 0;
 346                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 347                         if (s->bo_offset - offset >= shader->code_size) {
 348                                 shader->bo = slab->bo;
 349                                 shader->bo_offset = offset;
 350                                 list_addtail(&shader->slab_list, &s->slab_list);
 351                                 mtx_unlock(&device->shader_slab_mutex);
 352                                 return slab->ptr + offset;
 353                         }
 354                         offset = align_u64(s->bo_offset + s->code_size, 256);
 355                 }
 356                 if (slab->size - offset >= shader->code_size) {
 357                         shader->bo = slab->bo;
 358                         shader->bo_offset = offset;
 359                         list_addtail(&shader->slab_list, &slab->shaders);
 360                         mtx_unlock(&device->shader_slab_mutex);
 361                         return slab->ptr + offset;
 362                 }
 363         }
 364
 365         mtx_unlock(&device->shader_slab_mutex);
 366         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 367
 368         slab->size = 256 * 1024;
 369         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 370                                              RADEON_DOMAIN_VRAM,
 371                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 372                                              (device->physical_device->cpdma_prefetch_writes_memory ?
 373                                                      0 : RADEON_FLAG_READ_ONLY));
 374         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 375         list_inithead(&slab->shaders);
 376
 377         mtx_lock(&device->shader_slab_mutex);
 378         list_add(&slab->slabs, &device->shader_slabs);
 379
 380         shader->bo = slab->bo;
 381         shader->bo_offset = 0;
 382         list_add(&shader->slab_list, &slab->shaders);
 383         mtx_unlock(&device->shader_slab_mutex);
 384         return slab->ptr;
 385 }
 386
 387 void
 388 radv_destroy_shader_slabs(struct radv_device *device)
 389 {
 390         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 391                 device->ws->buffer_destroy(slab->bo);
 392                 free(slab);
 393         }
 394         mtx_destroy(&device->shader_slab_mutex);
 395 }
 396
 397 /* For the UMR disassembler. */
 398 #define DEBUGGER_END_OF_CODE_MARKER    0xbf9f0000 /* invalid instruction */
 399 #define DEBUGGER_NUM_MARKERS           5
 400
 401 static unsigned
 402 radv_get_shader_binary_size(struct ac_shader_binary *binary)
 403 {
 404         return binary->code_size + DEBUGGER_NUM_MARKERS * 4;
 405 }
 406
 407 static void
 408 radv_fill_shader_variant(struct radv_device *device,
 409                          struct radv_shader_variant *variant,
 410                          struct ac_shader_binary *binary,
 411                          gl_shader_stage stage)
 412 {
 413         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 414         struct radv_shader_info *info = &variant->info.info;
 415         unsigned vgpr_comp_cnt = 0;
 416
 417         variant->code_size = radv_get_shader_binary_size(binary);
 418         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 419                          S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
 420                          S_00B12C_SCRATCH_EN(scratch_enabled);
 421
 422         variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 423                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 424                 S_00B848_DX10_CLAMP(1) |
 425                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 426
 427         switch (stage) {
 428         case MESA_SHADER_TESS_EVAL:
 429                 vgpr_comp_cnt = 3;
 430                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 431                 break;
 432         case MESA_SHADER_TESS_CTRL:
 433                 if (device->physical_device->rad_info.chip_class >= GFX9) {
 434                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 435                 } else {
 436                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 437                 }
 438                 break;
 439         case MESA_SHADER_VERTEX:
 440         case MESA_SHADER_GEOMETRY:
 441                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 442                 break;
 443         case MESA_SHADER_FRAGMENT:
 444                 break;
 445         case MESA_SHADER_COMPUTE:
 446                 variant->rsrc2 |=
 447                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 448                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 449                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 450                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 451                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 452                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 453                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 454                 break;
 455         default:
 456                 unreachable("unsupported shader type");
 457                 break;
 458         }
 459
 460         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 461             stage == MESA_SHADER_GEOMETRY) {
 462                 unsigned es_type = variant->info.gs.es_type;
 463                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 464
 465                 if (es_type == MESA_SHADER_VERTEX) {
 466                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 467                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 468                         es_vgpr_comp_cnt = 3;
 469                 } else {
 470                         unreachable("invalid shader ES type");
 471                 }
 472
 473                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 474                  * VGPR[0:4] are always loaded.
 475                  */
 476                 if (info->uses_invocation_id) {
 477                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 478                 } else if (info->uses_prim_id) {
 479                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 480                 } else if (variant->info.gs.vertices_in >= 3) {
 481                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 482                 } else {
 483                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 484                 }
 485
 486                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 487                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 488                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 489         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 490                    stage == MESA_SHADER_TESS_CTRL) {
 491                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 492         } else {
 493                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 494         }
 495
 496         void *ptr = radv_alloc_shader_memory(device, variant);
 497         memcpy(ptr, binary->code, binary->code_size);
 498
 499         /* Add end-of-code markers for the UMR disassembler. */
 500        uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4;
 501        for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
 502                 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
 503
 504 }
 505
 506 static void radv_init_llvm_target()
 507 {
 508         LLVMInitializeAMDGPUTargetInfo();
 509         LLVMInitializeAMDGPUTarget();
 510         LLVMInitializeAMDGPUTargetMC();
 511         LLVMInitializeAMDGPUAsmPrinter();
 512
 513         /* For inline assembly. */
 514         LLVMInitializeAMDGPUAsmParser();
 515
 516         /* Workaround for bug in llvm 4.0 that causes image intrinsics
 517          * to disappear.
 518          * https://reviews.llvm.org/D26348
 519          *
 520          * Workaround for bug in llvm that causes the GPU to hang in presence
 521          * of nested loops because there is an exec mask issue. The proper
 522          * solution is to fix LLVM but this might require a bunch of work.
 523          * https://bugs.llvm.org/show_bug.cgi?id=37744
 524          *
 525          * "mesa" is the prefix for error messages.
 526          */
 527         const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
 528                                 "-amdgpu-skip-threshold=1" };
 529         LLVMParseCommandLineOptions(3, argv, NULL);
 530 }
 531
 532 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
 533
 534 static void radv_init_llvm_once(void)
 535 {
 536         call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
 537 }
 538
 539 static struct radv_shader_variant *
 540 shader_variant_create(struct radv_device *device,
 541                       struct radv_shader_module *module,
 542                       struct nir_shader * const *shaders,
 543                       int shader_count,
 544                       gl_shader_stage stage,
 545                       struct radv_nir_compiler_options *options,
 546                       bool gs_copy_shader,
 547                       void **code_out,
 548                       unsigned *code_size_out)
 549 {
 550         enum radeon_family chip_family = device->physical_device->rad_info.family;
 551         enum ac_target_machine_options tm_options = 0;
 552         struct radv_shader_variant *variant;
 553         struct ac_shader_binary binary;
 554         struct ac_llvm_compiler ac_llvm;
 555         bool thread_compiler;
 556         variant = calloc(1, sizeof(struct radv_shader_variant));
 557         if (!variant)
 558                 return NULL;
 559
 560         options->family = chip_family;
 561         options->chip_class = device->physical_device->rad_info.chip_class;
 562         options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
 563         options->dump_preoptir = options->dump_shader &&
 564                                  device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
 565         options->record_llvm_ir = device->keep_shader_info;
 566         options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
 567         options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
 568         options->address32_hi = device->physical_device->rad_info.address32_hi;
 569
 570         if (options->supports_spill)
 571                 tm_options |= AC_TM_SUPPORTS_SPILL;
 572         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 573                 tm_options |= AC_TM_SISCHED;
 574         if (options->check_ir)
 575                 tm_options |= AC_TM_CHECK_IR;
 576
 577         thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
 578         radv_init_llvm_once();
 579         radv_init_llvm_compiler(&ac_llvm, false,
 580                                 thread_compiler,
 581                                 chip_family, tm_options);
 582         if (gs_copy_shader) {
 583                 assert(shader_count == 1);
 584                 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
 585                                             &variant->config, &variant->info,
 586                                             options);
 587         } else {
 588                 radv_compile_nir_shader(&ac_llvm, &binary, &variant->config,
 589                                         &variant->info, shaders, shader_count,
 590                                         options);
 591         }
 592
 593         radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
 594
 595         radv_fill_shader_variant(device, variant, &binary, stage);
 596
 597         if (code_out) {
 598                 *code_out = binary.code;
 599                 *code_size_out = binary.code_size;
 600         } else
 601                 free(binary.code);
 602         free(binary.config);
 603         free(binary.rodata);
 604         free(binary.global_symbol_offsets);
 605         free(binary.relocs);
 606         variant->ref_count = 1;
 607
 608         if (device->keep_shader_info) {
 609                 variant->disasm_string = binary.disasm_string;
 610                 variant->llvm_ir_string = binary.llvm_ir_string;
 611                 if (!gs_copy_shader && !module->nir) {
 612                         variant->nir = *shaders;
 613                         variant->spirv = (uint32_t *)module->data;
 614                         variant->spirv_size = module->size;
 615                 }
 616         } else {
 617                 free(binary.disasm_string);
 618         }
 619
 620         return variant;
 621 }
 622
 623 struct radv_shader_variant *
 624 radv_shader_variant_create(struct radv_device *device,
 625                            struct radv_shader_module *module,
 626                            struct nir_shader *const *shaders,
 627                            int shader_count,
 628                            struct radv_pipeline_layout *layout,
 629                            const struct radv_shader_variant_key *key,
 630                            void **code_out,
 631                            unsigned *code_size_out)
 632 {
 633         struct radv_nir_compiler_options options = {0};
 634
 635         options.layout = layout;
 636         if (key)
 637                 options.key = *key;
 638
 639         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 640         options.supports_spill = true;
 641
 642         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 643                                      &options, false, code_out, code_size_out);
 644 }
 645
 646 struct radv_shader_variant *
 647 radv_create_gs_copy_shader(struct radv_device *device,
 648                            struct nir_shader *shader,
 649                            void **code_out,
 650                            unsigned *code_size_out,
 651                            bool multiview)
 652 {
 653         struct radv_nir_compiler_options options = {0};
 654
 655         options.key.has_multiview_view_index = multiview;
 656
 657         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 658                                      &options, true, code_out, code_size_out);
 659 }
 660
 661 void
 662 radv_shader_variant_destroy(struct radv_device *device,
 663                             struct radv_shader_variant *variant)
 664 {
 665         if (!p_atomic_dec_zero(&variant->ref_count))
 666                 return;
 667
 668         mtx_lock(&device->shader_slab_mutex);
 669         list_del(&variant->slab_list);
 670         mtx_unlock(&device->shader_slab_mutex);
 671
 672         ralloc_free(variant->nir);
 673         free(variant->disasm_string);
 674         free(variant->llvm_ir_string);
 675         free(variant);
 676 }
 677
 678 const char *
 679 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 680 {
 681         switch (stage) {
 682         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 683         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 684         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 685         case MESA_SHADER_COMPUTE: return "Compute Shader";
 686         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 687         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 688         default:
 689                 return "Unknown shader";
 690         };
 691 }
 692
 693 static void
 694 generate_shader_stats(struct radv_device *device,
 695                       struct radv_shader_variant *variant,
 696                       gl_shader_stage stage,
 697                       struct _mesa_string_buffer *buf)
 698 {
 699         unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 700         struct ac_shader_config *conf;
 701         unsigned max_simd_waves;
 702         unsigned lds_per_wave = 0;
 703
 704         max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
 705
 706         conf = &variant->config;
 707
 708         if (stage == MESA_SHADER_FRAGMENT) {
 709                 lds_per_wave = conf->lds_size * lds_increment +
 710                                align(variant->info.fs.num_interp * 48,
 711                                      lds_increment);
 712         }
 713
 714         if (conf->num_sgprs)
 715                 max_simd_waves =
 716                         MIN2(max_simd_waves,
 717                              radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
 718
 719         if (conf->num_vgprs)
 720                 max_simd_waves =
 721                         MIN2(max_simd_waves,
 722                              RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
 723
 724         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 725          * that PS can use.
 726          */
 727         if (lds_per_wave)
 728                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 729
 730         if (stage == MESA_SHADER_FRAGMENT) {
 731                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 732                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 733                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 734                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 735         }
 736
 737         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 738                                    "SGPRS: %d\n"
 739                                    "VGPRS: %d\n"
 740                                    "Spilled SGPRs: %d\n"
 741                                    "Spilled VGPRs: %d\n"
 742                                    "PrivMem VGPRS: %d\n"
 743                                    "Code Size: %d bytes\n"
 744                                    "LDS: %d blocks\n"
 745                                    "Scratch: %d bytes per wave\n"
 746                                    "Max Waves: %d\n"
 747                                    "********************\n\n\n",
 748                                    conf->num_sgprs, conf->num_vgprs,
 749                                    conf->spilled_sgprs, conf->spilled_vgprs,
 750                                    variant->info.private_mem_vgprs, variant->code_size,
 751                                    conf->lds_size, conf->scratch_bytes_per_wave,
 752                                    max_simd_waves);
 753 }
 754
 755 void
 756 radv_shader_dump_stats(struct radv_device *device,
 757                        struct radv_shader_variant *variant,
 758                        gl_shader_stage stage,
 759                        FILE *file)
 760 {
 761         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 762
 763         generate_shader_stats(device, variant, stage, buf);
 764
 765         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 766         fprintf(file, "%s", buf->buf);
 767
 768         _mesa_string_buffer_destroy(buf);
 769 }
 770
 771 VkResult
 772 radv_GetShaderInfoAMD(VkDevice _device,
 773                       VkPipeline _pipeline,
 774                       VkShaderStageFlagBits shaderStage,
 775                       VkShaderInfoTypeAMD infoType,
 776                       size_t* pInfoSize,
 777                       void* pInfo)
 778 {
 779         RADV_FROM_HANDLE(radv_device, device, _device);
 780         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 781         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 782         struct radv_shader_variant *variant = pipeline->shaders[stage];
 783         struct _mesa_string_buffer *buf;
 784         VkResult result = VK_SUCCESS;
 785
 786         /* Spec doesn't indicate what to do if the stage is invalid, so just
 787          * return no info for this. */
 788         if (!variant)
 789                 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
 790
 791         switch (infoType) {
 792         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 793                 if (!pInfo) {
 794                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 795                 } else {
 796                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 797                         struct ac_shader_config *conf = &variant->config;
 798
 799                         VkShaderStatisticsInfoAMD statistics = {};
 800                         statistics.shaderStageMask = shaderStage;
 801                         statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
 802                         statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device);
 803                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 804
 805                         if (stage == MESA_SHADER_COMPUTE) {
 806                                 unsigned *local_size = variant->nir->info.cs.local_size;
 807                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 808
 809                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 810                                                                ceil((double)workgroup_size / statistics.numPhysicalVgprs);
 811
 812                                 statistics.computeWorkGroupSize[0] = local_size[0];
 813                                 statistics.computeWorkGroupSize[1] = local_size[1];
 814                                 statistics.computeWorkGroupSize[2] = local_size[2];
 815                         } else {
 816                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 817                         }
 818
 819                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 820                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 821                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 822                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 823                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 824
 825                         size_t size = *pInfoSize;
 826                         *pInfoSize = sizeof(statistics);
 827
 828                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 829
 830                         if (size < *pInfoSize)
 831                                 result = VK_INCOMPLETE;
 832                 }
 833
 834                 break;
 835         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 836                 buf = _mesa_string_buffer_create(NULL, 1024);
 837
 838                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 839                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 840                 generate_shader_stats(device, variant, stage, buf);
 841
 842                 /* Need to include the null terminator. */
 843                 size_t length = buf->length + 1;
 844
 845                 if (!pInfo) {
 846                         *pInfoSize = length;
 847                 } else {
 848                         size_t size = *pInfoSize;
 849                         *pInfoSize = length;
 850
 851                         memcpy(pInfo, buf->buf, MIN2(size, length));
 852
 853                         if (size < length)
 854                                 result = VK_INCOMPLETE;
 855                 }
 856
 857                 _mesa_string_buffer_destroy(buf);
 858                 break;
 859         default:
 860                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 861                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 862                 break;
 863         }
 864
 865         return result;
 866 }