projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv/gfx10: fix the ESGS ring size symbol
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
41
42 #include "sid.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "ac_rtld.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50
51 #include "aco_interface.h"
52
53 #include "util/string_buffer.h"
54
55 static const struct nir_shader_compiler_options nir_options_llvm = {
56 .vertex_id_zero_based = true,
57 .lower_scmp = true,
58 .lower_flrp16 = true,
59 .lower_flrp32 = true,
60 .lower_flrp64 = true,
61 .lower_device_index_to_zero = true,
62 .lower_fsat = true,
63 .lower_fdiv = true,
64 .lower_bitfield_insert_to_bitfield_select = true,
65 .lower_bitfield_extract = true,
66 .lower_sub = true,
67 .lower_pack_snorm_2x16 = true,
68 .lower_pack_snorm_4x8 = true,
69 .lower_pack_unorm_2x16 = true,
70 .lower_pack_unorm_4x8 = true,
71 .lower_unpack_snorm_2x16 = true,
72 .lower_unpack_snorm_4x8 = true,
73 .lower_unpack_unorm_2x16 = true,
74 .lower_unpack_unorm_4x8 = true,
75 .lower_extract_byte = true,
76 .lower_extract_word = true,
77 .lower_ffma = true,
78 .lower_fpow = true,
79 .lower_mul_2x32_64 = true,
80 .lower_rotate = true,
81 .max_unroll_iterations = 32,
82 .use_interpolated_input_intrinsics = true,
83 };
84
85 static const struct nir_shader_compiler_options nir_options_aco = {
86 .vertex_id_zero_based = true,
87 .lower_scmp = true,
88 .lower_flrp16 = true,
89 .lower_flrp32 = true,
90 .lower_flrp64 = true,
91 .lower_device_index_to_zero = true,
92 .lower_fdiv = true,
93 .lower_bitfield_insert_to_bitfield_select = true,
94 .lower_bitfield_extract = true,
95 .lower_pack_snorm_2x16 = true,
96 .lower_pack_snorm_4x8 = true,
97 .lower_pack_unorm_2x16 = true,
98 .lower_pack_unorm_4x8 = true,
99 .lower_unpack_snorm_2x16 = true,
100 .lower_unpack_snorm_4x8 = true,
101 .lower_unpack_unorm_2x16 = true,
102 .lower_unpack_unorm_4x8 = true,
103 .lower_unpack_half_2x16 = true,
104 .lower_extract_byte = true,
105 .lower_extract_word = true,
106 .lower_ffma = true,
107 .lower_fpow = true,
108 .lower_mul_2x32_64 = true,
109 .lower_rotate = true,
110 .max_unroll_iterations = 32,
111 .use_interpolated_input_intrinsics = true,
112 };
113
114 bool
115 radv_can_dump_shader(struct radv_device *device,
116 struct radv_shader_module *module,
117 bool is_gs_copy_shader)
118 {
119 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
120 return false;
121 if (module)
122 return !module->nir ||
123 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
124
125 return is_gs_copy_shader;
126 }
127
128 bool
129 radv_can_dump_shader_stats(struct radv_device *device,
130 struct radv_shader_module *module)
131 {
132 /* Only dump non-meta shader stats. */
133 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
134 module && !module->nir;
135 }
136
137 unsigned shader_io_get_unique_index(gl_varying_slot slot)
138 {
139 /* handle patch indices separate */
140 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
141 return 0;
142 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
143 return 1;
144 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
145 return 2 + (slot - VARYING_SLOT_PATCH0);
146 if (slot == VARYING_SLOT_POS)
147 return 0;
148 if (slot == VARYING_SLOT_PSIZ)
149 return 1;
150 if (slot == VARYING_SLOT_CLIP_DIST0)
151 return 2;
152 if (slot == VARYING_SLOT_CLIP_DIST1)
153 return 3;
154 /* 3 is reserved for clip dist as well */
155 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
156 return 4 + (slot - VARYING_SLOT_VAR0);
157 unreachable("illegal slot in get unique index\n");
158 }
159
160 VkResult radv_CreateShaderModule(
161 VkDevice _device,
162 const VkShaderModuleCreateInfo* pCreateInfo,
163 const VkAllocationCallbacks* pAllocator,
164 VkShaderModule* pShaderModule)
165 {
166 RADV_FROM_HANDLE(radv_device, device, _device);
167 struct radv_shader_module *module;
168
169 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
170 assert(pCreateInfo->flags == 0);
171
172 module = vk_alloc2(&device->alloc, pAllocator,
173 sizeof(*module) + pCreateInfo->codeSize, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
175 if (module == NULL)
176 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
177
178 module->nir = NULL;
179 module->size = pCreateInfo->codeSize;
180 memcpy(module->data, pCreateInfo->pCode, module->size);
181
182 _mesa_sha1_compute(module->data, module->size, module->sha1);
183
184 *pShaderModule = radv_shader_module_to_handle(module);
185
186 return VK_SUCCESS;
187 }
188
189 void radv_DestroyShaderModule(
190 VkDevice _device,
191 VkShaderModule _module,
192 const VkAllocationCallbacks* pAllocator)
193 {
194 RADV_FROM_HANDLE(radv_device, device, _device);
195 RADV_FROM_HANDLE(radv_shader_module, module, _module);
196
197 if (!module)
198 return;
199
200 vk_free2(&device->alloc, pAllocator, module);
201 }
202
203 void
204 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
205 bool allow_copies)
206 {
207 bool progress;
208 unsigned lower_flrp =
209 (shader->options->lower_flrp16 ? 16 : 0) |
210 (shader->options->lower_flrp32 ? 32 : 0) |
211 (shader->options->lower_flrp64 ? 64 : 0);
212
213 do {
214 progress = false;
215
216 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
217 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
218
219 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
220 NIR_PASS_V(shader, nir_lower_pack);
221
222 if (allow_copies) {
223 /* Only run this pass in the first call to
224 * radv_optimize_nir. Later calls assume that we've
225 * lowered away any copy_deref instructions and we
226 * don't want to introduce any more.
227 */
228 NIR_PASS(progress, shader, nir_opt_find_array_copies);
229 }
230
231 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
232 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
233 NIR_PASS(progress, shader, nir_remove_dead_variables,
234 nir_var_function_temp);
235
236 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
237 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
238
239 NIR_PASS(progress, shader, nir_copy_prop);
240 NIR_PASS(progress, shader, nir_opt_remove_phis);
241 NIR_PASS(progress, shader, nir_opt_dce);
242 if (nir_opt_trivial_continues(shader)) {
243 progress = true;
244 NIR_PASS(progress, shader, nir_copy_prop);
245 NIR_PASS(progress, shader, nir_opt_remove_phis);
246 NIR_PASS(progress, shader, nir_opt_dce);
247 }
248 NIR_PASS(progress, shader, nir_opt_if, true);
249 NIR_PASS(progress, shader, nir_opt_dead_cf);
250 NIR_PASS(progress, shader, nir_opt_cse);
251 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
252 NIR_PASS(progress, shader, nir_opt_constant_folding);
253 NIR_PASS(progress, shader, nir_opt_algebraic);
254
255 if (lower_flrp != 0) {
256 bool lower_flrp_progress = false;
257 NIR_PASS(lower_flrp_progress,
258 shader,
259 nir_lower_flrp,
260 lower_flrp,
261 false /* always_precise */,
262 shader->options->lower_ffma);
263 if (lower_flrp_progress) {
264 NIR_PASS(progress, shader,
265 nir_opt_constant_folding);
266 progress = true;
267 }
268
269 /* Nothing should rematerialize any flrps, so we only
270 * need to do this lowering once.
271 */
272 lower_flrp = 0;
273 }
274
275 NIR_PASS(progress, shader, nir_opt_undef);
276 if (shader->options->max_unroll_iterations) {
277 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
278 }
279 } while (progress && !optimize_conservatively);
280
281 NIR_PASS(progress, shader, nir_opt_conditional_discard);
282 NIR_PASS(progress, shader, nir_opt_shrink_load);
283 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
284 }
285
286 nir_shader *
287 radv_shader_compile_to_nir(struct radv_device *device,
288 struct radv_shader_module *module,
289 const char *entrypoint_name,
290 gl_shader_stage stage,
291 const VkSpecializationInfo *spec_info,
292 const VkPipelineCreateFlags flags,
293 const struct radv_pipeline_layout *layout,
294 bool use_aco)
295 {
296 nir_shader *nir;
297 const nir_shader_compiler_options *nir_options = use_aco ? &nir_options_aco :
298 &nir_options_llvm;
299 if (module->nir) {
300 /* Some things such as our meta clear/blit code will give us a NIR
301 * shader directly. In that case, we just ignore the SPIR-V entirely
302 * and just use the NIR shader */
303 nir = module->nir;
304 nir->options = nir_options;
305 nir_validate_shader(nir, "in internal shader");
306
307 assert(exec_list_length(&nir->functions) == 1);
308 } else {
309 uint32_t *spirv = (uint32_t *) module->data;
310 assert(module->size % 4 == 0);
311
312 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
313 radv_print_spirv(spirv, module->size, stderr);
314
315 uint32_t num_spec_entries = 0;
316 struct nir_spirv_specialization *spec_entries = NULL;
317 if (spec_info && spec_info->mapEntryCount > 0) {
318 num_spec_entries = spec_info->mapEntryCount;
319 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
320 for (uint32_t i = 0; i < num_spec_entries; i++) {
321 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
322 const void *data = spec_info->pData + entry.offset;
323 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
324
325 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
326 if (spec_info->dataSize == 8)
327 spec_entries[i].data64 = *(const uint64_t *)data;
328 else
329 spec_entries[i].data32 = *(const uint32_t *)data;
330 }
331 }
332 const struct spirv_to_nir_options spirv_options = {
333 .lower_ubo_ssbo_access_to_offsets = true,
334 .caps = {
335 .amd_gcn_shader = true,
336 .amd_shader_ballot = device->physical_device->use_shader_ballot,
337 .amd_trinary_minmax = true,
338 .demote_to_helper_invocation = device->physical_device->use_aco,
339 .derivative_group = true,
340 .descriptor_array_dynamic_indexing = true,
341 .descriptor_array_non_uniform_indexing = true,
342 .descriptor_indexing = true,
343 .device_group = true,
344 .draw_parameters = true,
345 .float16 = !device->physical_device->use_aco,
346 .float64 = true,
347 .geometry_streams = true,
348 .image_read_without_format = true,
349 .image_write_without_format = true,
350 .int8 = !device->physical_device->use_aco,
351 .int16 = !device->physical_device->use_aco,
352 .int64 = true,
353 .int64_atomics = true,
354 .multiview = true,
355 .physical_storage_buffer_address = true,
356 .post_depth_coverage = true,
357 .runtime_descriptor_array = true,
358 .shader_viewport_index_layer = true,
359 .stencil_export = true,
360 .storage_8bit = !device->physical_device->use_aco,
361 .storage_16bit = !device->physical_device->use_aco,
362 .storage_image_ms = true,
363 .subgroup_arithmetic = true,
364 .subgroup_ballot = true,
365 .subgroup_basic = true,
366 .subgroup_quad = true,
367 .subgroup_shuffle = true,
368 .subgroup_vote = true,
369 .tessellation = true,
370 .transform_feedback = true,
371 .variable_pointers = true,
372 },
373 .ubo_addr_format = nir_address_format_32bit_index_offset,
374 .ssbo_addr_format = nir_address_format_32bit_index_offset,
375 .phys_ssbo_addr_format = nir_address_format_64bit_global,
376 .push_const_addr_format = nir_address_format_logical,
377 .shared_addr_format = nir_address_format_32bit_offset,
378 .frag_coord_is_sysval = true,
379 };
380 nir = spirv_to_nir(spirv, module->size / 4,
381 spec_entries, num_spec_entries,
382 stage, entrypoint_name,
383 &spirv_options, nir_options);
384 assert(nir->info.stage == stage);
385 nir_validate_shader(nir, "after spirv_to_nir");
386
387 free(spec_entries);
388
389 /* We have to lower away local constant initializers right before we
390 * inline functions. That way they get properly initialized at the top
391 * of the function and not at the top of its caller.
392 */
393 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
394 NIR_PASS_V(nir, nir_lower_returns);
395 NIR_PASS_V(nir, nir_inline_functions);
396 NIR_PASS_V(nir, nir_opt_deref);
397
398 /* Pick off the single entrypoint that we want */
399 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
400 if (func->is_entrypoint)
401 func->name = ralloc_strdup(func, "main");
402 else
403 exec_node_remove(&func->node);
404 }
405 assert(exec_list_length(&nir->functions) == 1);
406
407 /* Make sure we lower constant initializers on output variables so that
408 * nir_remove_dead_variables below sees the corresponding stores
409 */
410 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
411
412 /* Now that we've deleted all but the main function, we can go ahead and
413 * lower the rest of the constant initializers.
414 */
415 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
416
417 /* Split member structs. We do this before lower_io_to_temporaries so that
418 * it doesn't lower system values to temporaries by accident.
419 */
420 NIR_PASS_V(nir, nir_split_var_copies);
421 NIR_PASS_V(nir, nir_split_per_member_structs);
422
423 if (nir->info.stage == MESA_SHADER_FRAGMENT && use_aco)
424 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
425 if (nir->info.stage == MESA_SHADER_FRAGMENT)
426 NIR_PASS_V(nir, nir_lower_input_attachments, true);
427
428 NIR_PASS_V(nir, nir_remove_dead_variables,
429 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
430
431 NIR_PASS_V(nir, nir_propagate_invariant);
432
433 NIR_PASS_V(nir, nir_lower_system_values);
434 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
435 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
436 }
437
438 /* Vulkan uses the separate-shader linking model */
439 nir->info.separate_shader = true;
440
441 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
442
443 static const nir_lower_tex_options tex_options = {
444 .lower_txp = ~0,
445 .lower_tg4_offsets = true,
446 };
447
448 nir_lower_tex(nir, &tex_options);
449
450 nir_lower_vars_to_ssa(nir);
451
452 if (nir->info.stage == MESA_SHADER_VERTEX ||
453 nir->info.stage == MESA_SHADER_GEOMETRY ||
454 nir->info.stage == MESA_SHADER_FRAGMENT) {
455 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
456 nir_shader_get_entrypoint(nir), true, true);
457 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
458 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
459 nir_shader_get_entrypoint(nir), true, false);
460 }
461
462 nir_split_var_copies(nir);
463
464 nir_lower_global_vars_to_local(nir);
465 nir_remove_dead_variables(nir, nir_var_function_temp);
466 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
467 .subgroup_size = 64,
468 .ballot_bit_size = 64,
469 .lower_to_scalar = 1,
470 .lower_subgroup_masks = 1,
471 .lower_shuffle = 1,
472 .lower_shuffle_to_32bit = 1,
473 .lower_vote_eq_to_ballot = 1,
474 });
475
476 nir_lower_load_const_to_scalar(nir);
477
478 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
479 radv_optimize_nir(nir, false, true);
480
481 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
482 * to remove any copies introduced by nir_opt_find_array_copies().
483 */
484 nir_lower_var_copies(nir);
485
486 /* Lower large variables that are always constant with load_constant
487 * intrinsics, which get turned into PC-relative loads from a data
488 * section next to the shader.
489 */
490 NIR_PASS_V(nir, nir_opt_large_constants,
491 glsl_get_natural_size_align_bytes, 16);
492
493 /* Indirect lowering must be called after the radv_optimize_nir() loop
494 * has been called at least once. Otherwise indirect lowering can
495 * bloat the instruction count of the loop and cause it to be
496 * considered too large for unrolling.
497 */
498 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
499 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
500
501 return nir;
502 }
503
504 static int
505 type_size_vec4(const struct glsl_type *type, bool bindless)
506 {
507 return glsl_count_attribute_slots(type, false);
508 }
509
510 static nir_variable *
511 find_layer_in_var(nir_shader *nir)
512 {
513 nir_foreach_variable(var, &nir->inputs) {
514 if (var->data.location == VARYING_SLOT_LAYER) {
515 return var;
516 }
517 }
518
519 nir_variable *var =
520 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
521 var->data.location = VARYING_SLOT_LAYER;
522 var->data.interpolation = INTERP_MODE_FLAT;
523 return var;
524 }
525
526 /* We use layered rendering to implement multiview, which means we need to map
527 * view_index to gl_Layer. The attachment lowering also uses needs to know the
528 * layer so that it can sample from the correct layer. The code generates a
529 * load from the layer_id sysval, but since we don't have a way to get at this
530 * information from the fragment shader, we also need to lower this to the
531 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
532 * slot, before lowering io, so that nir_assign_var_locations() will give the
533 * LAYER varying the correct driver_location.
534 */
535
536 static bool
537 lower_view_index(nir_shader *nir)
538 {
539 bool progress = false;
540 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
541 nir_builder b;
542 nir_builder_init(&b, entry);
543
544 nir_variable *layer = NULL;
545 nir_foreach_block(block, entry) {
546 nir_foreach_instr_safe(instr, block) {
547 if (instr->type != nir_instr_type_intrinsic)
548 continue;
549
550 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
551 if (load->intrinsic != nir_intrinsic_load_view_index &&
552 load->intrinsic != nir_intrinsic_load_layer_id)
553 continue;
554
555 if (!layer)
556 layer = find_layer_in_var(nir);
557
558 b.cursor = nir_before_instr(instr);
559 nir_ssa_def *def = nir_load_var(&b, layer);
560 nir_ssa_def_rewrite_uses(&load->dest.ssa,
561 nir_src_for_ssa(def));
562
563 nir_instr_remove(instr);
564 progress = true;
565 }
566 }
567
568 return progress;
569 }
570
571 void
572 radv_lower_fs_io(nir_shader *nir)
573 {
574 NIR_PASS_V(nir, lower_view_index);
575 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
576 MESA_SHADER_FRAGMENT);
577
578 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
579
580 /* This pass needs actual constants */
581 nir_opt_constant_folding(nir);
582
583 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
584 }
585
586
587 void *
588 radv_alloc_shader_memory(struct radv_device *device,
589 struct radv_shader_variant *shader)
590 {
591 mtx_lock(&device->shader_slab_mutex);
592 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
593 uint64_t offset = 0;
594 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
595 if (s->bo_offset - offset >= shader->code_size) {
596 shader->bo = slab->bo;
597 shader->bo_offset = offset;
598 list_addtail(&shader->slab_list, &s->slab_list);
599 mtx_unlock(&device->shader_slab_mutex);
600 return slab->ptr + offset;
601 }
602 offset = align_u64(s->bo_offset + s->code_size, 256);
603 }
604 if (slab->size - offset >= shader->code_size) {
605 shader->bo = slab->bo;
606 shader->bo_offset = offset;
607 list_addtail(&shader->slab_list, &slab->shaders);
608 mtx_unlock(&device->shader_slab_mutex);
609 return slab->ptr + offset;
610 }
611 }
612
613 mtx_unlock(&device->shader_slab_mutex);
614 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
615
616 slab->size = 256 * 1024;
617 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
618 RADEON_DOMAIN_VRAM,
619 RADEON_FLAG_NO_INTERPROCESS_SHARING |
620 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
621 0 : RADEON_FLAG_READ_ONLY),
622 RADV_BO_PRIORITY_SHADER);
623 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
624 list_inithead(&slab->shaders);
625
626 mtx_lock(&device->shader_slab_mutex);
627 list_add(&slab->slabs, &device->shader_slabs);
628
629 shader->bo = slab->bo;
630 shader->bo_offset = 0;
631 list_add(&shader->slab_list, &slab->shaders);
632 mtx_unlock(&device->shader_slab_mutex);
633 return slab->ptr;
634 }
635
636 void
637 radv_destroy_shader_slabs(struct radv_device *device)
638 {
639 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
640 device->ws->buffer_destroy(slab->bo);
641 free(slab);
642 }
643 mtx_destroy(&device->shader_slab_mutex);
644 }
645
646 /* For the UMR disassembler. */
647 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
648 #define DEBUGGER_NUM_MARKERS 5
649
650 static unsigned
651 radv_get_shader_binary_size(size_t code_size)
652 {
653 return code_size + DEBUGGER_NUM_MARKERS * 4;
654 }
655
656 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
657 const struct ac_shader_config *config_in,
658 const struct radv_shader_info *info,
659 gl_shader_stage stage,
660 struct ac_shader_config *config_out)
661 {
662 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
663 unsigned vgpr_comp_cnt = 0;
664 unsigned num_input_vgprs = info->num_input_vgprs;
665
666 if (stage == MESA_SHADER_FRAGMENT) {
667 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
668 }
669
670 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
671 /* +3 for scratch wave offset and VCC */
672 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
673 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
674 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
675 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
676 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
677 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
678
679 *config_out = *config_in;
680 config_out->num_vgprs = num_vgprs;
681 config_out->num_sgprs = num_sgprs;
682 config_out->num_shared_vgprs = num_shared_vgprs;
683
684 /* Enable 64-bit and 16-bit denormals, because there is no performance
685 * cost.
686 *
687 * If denormals are enabled, all floating-point output modifiers are
688 * ignored.
689 *
690 * Don't enable denormals for 32-bit floats, because:
691 * - Floating-point output modifiers would be ignored by the hw.
692 * - Some opcodes don't support denormals, such as v_mad_f32. We would
693 * have to stop using those.
694 * - GFX6 & GFX7 would be very slow.
695 */
696 config_out->float_mode |= V_00B028_FP_64_DENORMS;
697
698 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
699 S_00B12C_SCRATCH_EN(scratch_enabled);
700
701 if (!pdevice->use_ngg_streamout) {
702 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
703 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
704 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
705 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
706 S_00B12C_SO_EN(!!info->so.num_outputs);
707 }
708
709 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
710 (info->wave_size == 32 ? 8 : 4)) |
711 S_00B848_DX10_CLAMP(1) |
712 S_00B848_FLOAT_MODE(config_out->float_mode);
713
714 if (pdevice->rad_info.chip_class >= GFX10) {
715 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
716 } else {
717 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
718 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
719 }
720
721 switch (stage) {
722 case MESA_SHADER_TESS_EVAL:
723 if (info->is_ngg) {
724 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
725 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
726 } else if (info->tes.as_es) {
727 assert(pdevice->rad_info.chip_class <= GFX8);
728 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
729
730 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
731 } else {
732 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
733 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
734
735 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
736 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
737 }
738 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
739 break;
740 case MESA_SHADER_TESS_CTRL:
741 if (pdevice->rad_info.chip_class >= GFX9) {
742 /* We need at least 2 components for LS.
743 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
744 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
745 */
746 if (pdevice->rad_info.chip_class >= GFX10) {
747 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
748 } else {
749 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
750 }
751 } else {
752 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
753 }
754 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
755 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
756 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
757 break;
758 case MESA_SHADER_VERTEX:
759 if (info->is_ngg) {
760 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
761 } else if (info->vs.as_ls) {
762 assert(pdevice->rad_info.chip_class <= GFX8);
763 /* We need at least 2 components for LS.
764 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
765 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
766 */
767 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
768 } else if (info->vs.as_es) {
769 assert(pdevice->rad_info.chip_class <= GFX8);
770 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
771 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
772 } else {
773 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
774 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
775 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
776 */
777 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
778 vgpr_comp_cnt = 3;
779 } else if (info->vs.export_prim_id) {
780 vgpr_comp_cnt = 2;
781 } else if (info->vs.needs_instance_id) {
782 vgpr_comp_cnt = 1;
783 } else {
784 vgpr_comp_cnt = 0;
785 }
786
787 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
788 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
789 }
790 break;
791 case MESA_SHADER_FRAGMENT:
792 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
793 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
794 break;
795 case MESA_SHADER_GEOMETRY:
796 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
797 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
798 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
799 break;
800 case MESA_SHADER_COMPUTE:
801 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
802 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
803 config_out->rsrc2 |=
804 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
805 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
806 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
807 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
808 info->cs.uses_thread_id[1] ? 1 : 0) |
809 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
810 S_00B84C_LDS_SIZE(config_in->lds_size);
811 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
812
813 break;
814 default:
815 unreachable("unsupported shader type");
816 break;
817 }
818
819 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
820 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
821 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
822 gl_shader_stage es_stage = stage;
823 if (stage == MESA_SHADER_GEOMETRY)
824 es_stage = info->gs.es_type;
825
826 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
827 if (es_stage == MESA_SHADER_VERTEX) {
828 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
829 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
830 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
831 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
832 } else
833 unreachable("Unexpected ES shader stage");
834
835 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
836 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
837 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
838 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
839 } else if (info->uses_prim_id) {
840 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
841 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
842 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
843 } else {
844 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
845 }
846
847 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
848 S_00B228_WGP_MODE(1);
849 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
850 S_00B22C_LDS_SIZE(config_in->lds_size) |
851 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
852 } else if (pdevice->rad_info.chip_class >= GFX9 &&
853 stage == MESA_SHADER_GEOMETRY) {
854 unsigned es_type = info->gs.es_type;
855 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
856
857 if (es_type == MESA_SHADER_VERTEX) {
858 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
859 if (info->vs.needs_instance_id) {
860 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
861 } else {
862 es_vgpr_comp_cnt = 0;
863 }
864 } else if (es_type == MESA_SHADER_TESS_EVAL) {
865 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
866 } else {
867 unreachable("invalid shader ES type");
868 }
869
870 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
871 * VGPR[0:4] are always loaded.
872 */
873 if (info->uses_invocation_id) {
874 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
875 } else if (info->uses_prim_id) {
876 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
877 } else if (info->gs.vertices_in >= 3) {
878 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
879 } else {
880 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
881 }
882
883 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
884 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
885 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
886 } else if (pdevice->rad_info.chip_class >= GFX9 &&
887 stage == MESA_SHADER_TESS_CTRL) {
888 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
889 } else {
890 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
891 }
892 }
893
894 struct radv_shader_variant *
895 radv_shader_variant_create(struct radv_device *device,
896 const struct radv_shader_binary *binary,
897 bool keep_shader_info)
898 {
899 struct ac_shader_config config = {0};
900 struct ac_rtld_binary rtld_binary = {0};
901 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
902 if (!variant)
903 return NULL;
904
905 variant->ref_count = 1;
906
907 if (binary->type == RADV_BINARY_TYPE_RTLD) {
908 struct ac_rtld_symbol lds_symbols[2];
909 unsigned num_lds_symbols = 0;
910 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
911 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
912
913 if (device->physical_device->rad_info.chip_class >= GFX9 &&
914 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
915 !binary->is_gs_copy_shader) {
916 /* We add this symbol even on LLVM <= 8 to ensure that
917 * shader->config.lds_size is set correctly below.
918 */
919 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
920 sym->name = "esgs_ring";
921 sym->size = binary->info.ngg_info.esgs_ring_size;
922 sym->align = 64 * 1024;
923 }
924
925 if (binary->info.is_ngg &&
926 binary->stage == MESA_SHADER_GEOMETRY) {
927 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
928 sym->name = "ngg_emit";
929 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
930 sym->align = 4;
931 }
932
933 struct ac_rtld_open_info open_info = {
934 .info = &device->physical_device->rad_info,
935 .shader_type = binary->stage,
936 .wave_size = binary->info.wave_size,
937 .num_parts = 1,
938 .elf_ptrs = &elf_data,
939 .elf_sizes = &elf_size,
940 .num_shared_lds_symbols = num_lds_symbols,
941 .shared_lds_symbols = lds_symbols,
942 };
943
944 if (!ac_rtld_open(&rtld_binary, open_info)) {
945 free(variant);
946 return NULL;
947 }
948
949 if (!ac_rtld_read_config(&rtld_binary, &config)) {
950 ac_rtld_close(&rtld_binary);
951 free(variant);
952 return NULL;
953 }
954
955 if (rtld_binary.lds_size > 0) {
956 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
957 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
958 }
959
960 variant->code_size = rtld_binary.rx_size;
961 variant->exec_size = rtld_binary.exec_size;
962 } else {
963 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
964 config = ((struct radv_shader_binary_legacy *)binary)->config;
965 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
966 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
967 }
968
969 variant->info = binary->info;
970 radv_postprocess_config(device->physical_device, &config, &binary->info,
971 binary->stage, &variant->config);
972
973 void *dest_ptr = radv_alloc_shader_memory(device, variant);
974
975 if (binary->type == RADV_BINARY_TYPE_RTLD) {
976 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
977 struct ac_rtld_upload_info info = {
978 .binary = &rtld_binary,
979 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
980 .rx_ptr = dest_ptr,
981 };
982
983 if (!ac_rtld_upload(&info)) {
984 radv_shader_variant_destroy(device, variant);
985 ac_rtld_close(&rtld_binary);
986 return NULL;
987 }
988
989 if (keep_shader_info ||
990 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
991 const char *disasm_data;
992 size_t disasm_size;
993 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
994 radv_shader_variant_destroy(device, variant);
995 ac_rtld_close(&rtld_binary);
996 return NULL;
997 }
998
999 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1000 variant->disasm_string = malloc(disasm_size + 1);
1001 memcpy(variant->disasm_string, disasm_data, disasm_size);
1002 variant->disasm_string[disasm_size] = 0;
1003 }
1004
1005 ac_rtld_close(&rtld_binary);
1006 } else {
1007 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1008 memcpy(dest_ptr, bin->data, bin->code_size);
1009
1010 /* Add end-of-code markers for the UMR disassembler. */
1011 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1012 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1013 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1014
1015 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
1016 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL;
1017 }
1018 return variant;
1019 }
1020
1021 static char *
1022 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1023 int shader_count)
1024 {
1025 char *data = NULL;
1026 char *ret = NULL;
1027 size_t size = 0;
1028 FILE *f = open_memstream(&data, &size);
1029 if (f) {
1030 for (int i = 0; i < shader_count; ++i)
1031 nir_print_shader(shaders[i], f);
1032 fclose(f);
1033 }
1034
1035 ret = malloc(size + 1);
1036 if (ret) {
1037 memcpy(ret, data, size);
1038 ret[size] = 0;
1039 }
1040 free(data);
1041 return ret;
1042 }
1043
1044 static struct radv_shader_variant *
1045 shader_variant_compile(struct radv_device *device,
1046 struct radv_shader_module *module,
1047 struct nir_shader * const *shaders,
1048 int shader_count,
1049 gl_shader_stage stage,
1050 struct radv_shader_info *info,
1051 struct radv_nir_compiler_options *options,
1052 bool gs_copy_shader,
1053 bool keep_shader_info,
1054 bool use_aco,
1055 struct radv_shader_binary **binary_out)
1056 {
1057 enum radeon_family chip_family = device->physical_device->rad_info.family;
1058 struct radv_shader_binary *binary = NULL;
1059
1060 options->family = chip_family;
1061 options->chip_class = device->physical_device->rad_info.chip_class;
1062 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1063 options->dump_preoptir = options->dump_shader &&
1064 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1065 options->record_ir = keep_shader_info;
1066 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1067 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1068 options->address32_hi = device->physical_device->rad_info.address32_hi;
1069 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1070 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1071
1072 if ((stage == MESA_SHADER_GEOMETRY && !options->key.vs_common_out.as_ngg) ||
1073 gs_copy_shader)
1074 options->wave_size = 64;
1075 else if (stage == MESA_SHADER_COMPUTE)
1076 options->wave_size = device->physical_device->cs_wave_size;
1077 else if (stage == MESA_SHADER_FRAGMENT)
1078 options->wave_size = device->physical_device->ps_wave_size;
1079 else
1080 options->wave_size = device->physical_device->ge_wave_size;
1081
1082 if (!use_aco || options->dump_shader || options->record_ir)
1083 ac_init_llvm_once();
1084
1085 if (use_aco) {
1086 aco_compile_shader(shader_count, shaders, &binary, info, options);
1087 binary->info = *info;
1088 } else {
1089 enum ac_target_machine_options tm_options = 0;
1090 struct ac_llvm_compiler ac_llvm;
1091 bool thread_compiler;
1092
1093 if (options->supports_spill)
1094 tm_options |= AC_TM_SUPPORTS_SPILL;
1095 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
1096 tm_options |= AC_TM_SISCHED;
1097 if (options->check_ir)
1098 tm_options |= AC_TM_CHECK_IR;
1099 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
1100 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
1101
1102 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
1103 radv_init_llvm_compiler(&ac_llvm,
1104 thread_compiler,
1105 chip_family, tm_options,
1106 options->wave_size);
1107
1108 if (gs_copy_shader) {
1109 assert(shader_count == 1);
1110 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
1111 info, options);
1112 } else {
1113 radv_compile_nir_shader(&ac_llvm, &binary, info,
1114 shaders, shader_count, options);
1115 }
1116
1117 binary->info = *info;
1118 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
1119 }
1120
1121 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1122 keep_shader_info);
1123 if (!variant) {
1124 free(binary);
1125 return NULL;
1126 }
1127 variant->aco_used = use_aco;
1128
1129 if (options->dump_shader) {
1130 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
1131 }
1132
1133
1134 if (keep_shader_info) {
1135 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1136 if (!gs_copy_shader && !module->nir) {
1137 variant->spirv = (uint32_t *)module->data;
1138 variant->spirv_size = module->size;
1139 }
1140 }
1141
1142 if (binary_out)
1143 *binary_out = binary;
1144 else
1145 free(binary);
1146
1147 return variant;
1148 }
1149
1150 struct radv_shader_variant *
1151 radv_shader_variant_compile(struct radv_device *device,
1152 struct radv_shader_module *module,
1153 struct nir_shader *const *shaders,
1154 int shader_count,
1155 struct radv_pipeline_layout *layout,
1156 const struct radv_shader_variant_key *key,
1157 struct radv_shader_info *info,
1158 bool keep_shader_info,
1159 bool use_aco,
1160 struct radv_shader_binary **binary_out)
1161 {
1162 struct radv_nir_compiler_options options = {0};
1163
1164 options.layout = layout;
1165 if (key)
1166 options.key = *key;
1167
1168 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
1169 options.supports_spill = true;
1170 options.robust_buffer_access = device->robust_buffer_access;
1171
1172 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1173 &options, false, keep_shader_info, use_aco, binary_out);
1174 }
1175
1176 struct radv_shader_variant *
1177 radv_create_gs_copy_shader(struct radv_device *device,
1178 struct nir_shader *shader,
1179 struct radv_shader_info *info,
1180 struct radv_shader_binary **binary_out,
1181 bool keep_shader_info,
1182 bool multiview)
1183 {
1184 struct radv_nir_compiler_options options = {0};
1185
1186 options.key.has_multiview_view_index = multiview;
1187
1188 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1189 info, &options, true, keep_shader_info, false, binary_out);
1190 }
1191
1192 void
1193 radv_shader_variant_destroy(struct radv_device *device,
1194 struct radv_shader_variant *variant)
1195 {
1196 if (!p_atomic_dec_zero(&variant->ref_count))
1197 return;
1198
1199 mtx_lock(&device->shader_slab_mutex);
1200 list_del(&variant->slab_list);
1201 mtx_unlock(&device->shader_slab_mutex);
1202
1203 free(variant->nir_string);
1204 free(variant->disasm_string);
1205 free(variant->ir_string);
1206 free(variant);
1207 }
1208
1209 const char *
1210 radv_get_shader_name(struct radv_shader_info *info,
1211 gl_shader_stage stage)
1212 {
1213 switch (stage) {
1214 case MESA_SHADER_VERTEX:
1215 if (info->vs.as_ls)
1216 return "Vertex Shader as LS";
1217 else if (info->vs.as_es)
1218 return "Vertex Shader as ES";
1219 else if (info->is_ngg)
1220 return "Vertex Shader as ESGS";
1221 else
1222 return "Vertex Shader as VS";
1223 case MESA_SHADER_TESS_CTRL:
1224 return "Tessellation Control Shader";
1225 case MESA_SHADER_TESS_EVAL:
1226 if (info->tes.as_es)
1227 return "Tessellation Evaluation Shader as ES";
1228 else if (info->is_ngg)
1229 return "Tessellation Evaluation Shader as ESGS";
1230 else
1231 return "Tessellation Evaluation Shader as VS";
1232 case MESA_SHADER_GEOMETRY:
1233 return "Geometry Shader";
1234 case MESA_SHADER_FRAGMENT:
1235 return "Pixel Shader";
1236 case MESA_SHADER_COMPUTE:
1237 return "Compute Shader";
1238 default:
1239 return "Unknown shader";
1240 };
1241 }
1242
1243 unsigned
1244 radv_get_max_workgroup_size(enum chip_class chip_class,
1245 gl_shader_stage stage,
1246 const unsigned *sizes)
1247 {
1248 switch (stage) {
1249 case MESA_SHADER_TESS_CTRL:
1250 return chip_class >= GFX7 ? 128 : 64;
1251 case MESA_SHADER_GEOMETRY:
1252 return chip_class >= GFX9 ? 128 : 64;
1253 case MESA_SHADER_COMPUTE:
1254 break;
1255 default:
1256 return 0;
1257 }
1258
1259 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1260 return max_workgroup_size;
1261 }
1262
1263 unsigned
1264 radv_get_max_waves(struct radv_device *device,
1265 struct radv_shader_variant *variant,
1266 gl_shader_stage stage)
1267 {
1268 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1269 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1270 uint8_t wave_size = variant->info.wave_size;
1271 struct ac_shader_config *conf = &variant->config;
1272 unsigned max_simd_waves;
1273 unsigned lds_per_wave = 0;
1274
1275 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1276
1277 if (stage == MESA_SHADER_FRAGMENT) {
1278 lds_per_wave = conf->lds_size * lds_increment +
1279 align(variant->info.ps.num_interp * 48,
1280 lds_increment);
1281 } else if (stage == MESA_SHADER_COMPUTE) {
1282 unsigned max_workgroup_size =
1283 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1284 lds_per_wave = (conf->lds_size * lds_increment) /
1285 DIV_ROUND_UP(max_workgroup_size, wave_size);
1286 }
1287
1288 if (conf->num_sgprs)
1289 max_simd_waves =
1290 MIN2(max_simd_waves,
1291 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1292 conf->num_sgprs);
1293
1294 if (conf->num_vgprs)
1295 max_simd_waves =
1296 MIN2(max_simd_waves,
1297 RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
1298
1299 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1300 * that PS can use.
1301 */
1302 if (lds_per_wave)
1303 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1304
1305 return max_simd_waves;
1306 }
1307
1308 static void
1309 generate_shader_stats(struct radv_device *device,
1310 struct radv_shader_variant *variant,
1311 gl_shader_stage stage,
1312 struct _mesa_string_buffer *buf)
1313 {
1314 struct ac_shader_config *conf = &variant->config;
1315 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1316
1317 if (stage == MESA_SHADER_FRAGMENT) {
1318 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1319 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1320 "SPI_PS_INPUT_ENA = 0x%04x\n",
1321 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1322 }
1323
1324 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1325 "SGPRS: %d\n"
1326 "VGPRS: %d\n"
1327 "Spilled SGPRs: %d\n"
1328 "Spilled VGPRs: %d\n"
1329 "PrivMem VGPRS: %d\n"
1330 "Code Size: %d bytes\n"
1331 "LDS: %d blocks\n"
1332 "Scratch: %d bytes per wave\n"
1333 "Max Waves: %d\n"
1334 "********************\n\n\n",
1335 conf->num_sgprs, conf->num_vgprs,
1336 conf->spilled_sgprs, conf->spilled_vgprs,
1337 variant->info.private_mem_vgprs, variant->exec_size,
1338 conf->lds_size, conf->scratch_bytes_per_wave,
1339 max_simd_waves);
1340 }
1341
1342 void
1343 radv_shader_dump_stats(struct radv_device *device,
1344 struct radv_shader_variant *variant,
1345 gl_shader_stage stage,
1346 FILE *file)
1347 {
1348 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1349
1350 generate_shader_stats(device, variant, stage, buf);
1351
1352 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1353 fprintf(file, "%s", buf->buf);
1354
1355 _mesa_string_buffer_destroy(buf);
1356 }
1357
1358 VkResult
1359 radv_GetShaderInfoAMD(VkDevice _device,
1360 VkPipeline _pipeline,
1361 VkShaderStageFlagBits shaderStage,
1362 VkShaderInfoTypeAMD infoType,
1363 size_t* pInfoSize,
1364 void* pInfo)
1365 {
1366 RADV_FROM_HANDLE(radv_device, device, _device);
1367 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1368 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1369 struct radv_shader_variant *variant = pipeline->shaders[stage];
1370 struct _mesa_string_buffer *buf;
1371 VkResult result = VK_SUCCESS;
1372
1373 /* Spec doesn't indicate what to do if the stage is invalid, so just
1374 * return no info for this. */
1375 if (!variant)
1376 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1377
1378 switch (infoType) {
1379 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1380 if (!pInfo) {
1381 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1382 } else {
1383 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1384 struct ac_shader_config *conf = &variant->config;
1385
1386 VkShaderStatisticsInfoAMD statistics = {};
1387 statistics.shaderStageMask = shaderStage;
1388 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1389 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1390 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1391
1392 if (stage == MESA_SHADER_COMPUTE) {
1393 unsigned *local_size = variant->info.cs.block_size;
1394 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1395
1396 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1397 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1398
1399 statistics.computeWorkGroupSize[0] = local_size[0];
1400 statistics.computeWorkGroupSize[1] = local_size[1];
1401 statistics.computeWorkGroupSize[2] = local_size[2];
1402 } else {
1403 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1404 }
1405
1406 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1407 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1408 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1409 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1410 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1411
1412 size_t size = *pInfoSize;
1413 *pInfoSize = sizeof(statistics);
1414
1415 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1416
1417 if (size < *pInfoSize)
1418 result = VK_INCOMPLETE;
1419 }
1420
1421 break;
1422 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1423 buf = _mesa_string_buffer_create(NULL, 1024);
1424
1425 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1426 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1427 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1428 generate_shader_stats(device, variant, stage, buf);
1429
1430 /* Need to include the null terminator. */
1431 size_t length = buf->length + 1;
1432
1433 if (!pInfo) {
1434 *pInfoSize = length;
1435 } else {
1436 size_t size = *pInfoSize;
1437 *pInfoSize = length;
1438
1439 memcpy(pInfo, buf->buf, MIN2(size, length));
1440
1441 if (size < length)
1442 result = VK_INCOMPLETE;
1443 }
1444
1445 _mesa_string_buffer_destroy(buf);
1446 break;
1447 default:
1448 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1449 result = VK_ERROR_FEATURE_NOT_PRESENT;
1450 break;
1451 }
1452
1453 return result;
1454 }