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radv: remove RADV_DEBUG=nosisched and RADV_PERFTEST=sisched
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41 #include <llvm-c/Support.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "ac_rtld.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51
52 #include "aco_interface.h"
53
54 #include "util/string_buffer.h"
55
56 static const struct nir_shader_compiler_options nir_options_llvm = {
57 .vertex_id_zero_based = true,
58 .lower_scmp = true,
59 .lower_flrp16 = true,
60 .lower_flrp32 = true,
61 .lower_flrp64 = true,
62 .lower_device_index_to_zero = true,
63 .lower_fsat = true,
64 .lower_fdiv = true,
65 .lower_fmod = true,
66 .lower_bitfield_insert_to_bitfield_select = true,
67 .lower_bitfield_extract = true,
68 .lower_sub = true,
69 .lower_pack_snorm_2x16 = true,
70 .lower_pack_snorm_4x8 = true,
71 .lower_pack_unorm_2x16 = true,
72 .lower_pack_unorm_4x8 = true,
73 .lower_unpack_snorm_2x16 = true,
74 .lower_unpack_snorm_4x8 = true,
75 .lower_unpack_unorm_2x16 = true,
76 .lower_unpack_unorm_4x8 = true,
77 .lower_extract_byte = true,
78 .lower_extract_word = true,
79 .lower_ffma = true,
80 .lower_fpow = true,
81 .lower_mul_2x32_64 = true,
82 .lower_rotate = true,
83 .max_unroll_iterations = 32,
84 .use_interpolated_input_intrinsics = true,
85 /* nir_lower_int64() isn't actually called for the LLVM backend, but
86 * this helps the loop unrolling heuristics. */
87 .lower_int64_options = nir_lower_imul64 |
88 nir_lower_imul_high64 |
89 nir_lower_imul_2x32_64 |
90 nir_lower_divmod64 |
91 nir_lower_minmax64 |
92 nir_lower_iabs64,
93 };
94
95 static const struct nir_shader_compiler_options nir_options_aco = {
96 .vertex_id_zero_based = true,
97 .lower_scmp = true,
98 .lower_flrp16 = true,
99 .lower_flrp32 = true,
100 .lower_flrp64 = true,
101 .lower_device_index_to_zero = true,
102 .lower_fdiv = true,
103 .lower_fmod = true,
104 .lower_bitfield_insert_to_bitfield_select = true,
105 .lower_bitfield_extract = true,
106 .lower_pack_snorm_2x16 = true,
107 .lower_pack_snorm_4x8 = true,
108 .lower_pack_unorm_2x16 = true,
109 .lower_pack_unorm_4x8 = true,
110 .lower_unpack_snorm_2x16 = true,
111 .lower_unpack_snorm_4x8 = true,
112 .lower_unpack_unorm_2x16 = true,
113 .lower_unpack_unorm_4x8 = true,
114 .lower_unpack_half_2x16 = true,
115 .lower_extract_byte = true,
116 .lower_extract_word = true,
117 .lower_ffma = true,
118 .lower_fpow = true,
119 .lower_mul_2x32_64 = true,
120 .lower_rotate = true,
121 .max_unroll_iterations = 32,
122 .use_interpolated_input_intrinsics = true,
123 .lower_int64_options = nir_lower_imul64 |
124 nir_lower_imul_high64 |
125 nir_lower_imul_2x32_64 |
126 nir_lower_divmod64 |
127 nir_lower_logic64 |
128 nir_lower_minmax64 |
129 nir_lower_iabs64,
130 };
131
132 bool
133 radv_can_dump_shader(struct radv_device *device,
134 struct radv_shader_module *module,
135 bool is_gs_copy_shader)
136 {
137 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
138 return false;
139 if (module)
140 return !module->nir ||
141 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
142
143 return is_gs_copy_shader;
144 }
145
146 bool
147 radv_can_dump_shader_stats(struct radv_device *device,
148 struct radv_shader_module *module)
149 {
150 /* Only dump non-meta shader stats. */
151 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
152 module && !module->nir;
153 }
154
155 VkResult radv_CreateShaderModule(
156 VkDevice _device,
157 const VkShaderModuleCreateInfo* pCreateInfo,
158 const VkAllocationCallbacks* pAllocator,
159 VkShaderModule* pShaderModule)
160 {
161 RADV_FROM_HANDLE(radv_device, device, _device);
162 struct radv_shader_module *module;
163
164 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
165 assert(pCreateInfo->flags == 0);
166
167 module = vk_alloc2(&device->alloc, pAllocator,
168 sizeof(*module) + pCreateInfo->codeSize, 8,
169 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
170 if (module == NULL)
171 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
172
173 module->nir = NULL;
174 module->size = pCreateInfo->codeSize;
175 memcpy(module->data, pCreateInfo->pCode, module->size);
176
177 _mesa_sha1_compute(module->data, module->size, module->sha1);
178
179 *pShaderModule = radv_shader_module_to_handle(module);
180
181 return VK_SUCCESS;
182 }
183
184 void radv_DestroyShaderModule(
185 VkDevice _device,
186 VkShaderModule _module,
187 const VkAllocationCallbacks* pAllocator)
188 {
189 RADV_FROM_HANDLE(radv_device, device, _device);
190 RADV_FROM_HANDLE(radv_shader_module, module, _module);
191
192 if (!module)
193 return;
194
195 vk_free2(&device->alloc, pAllocator, module);
196 }
197
198 void
199 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
200 bool allow_copies)
201 {
202 bool progress;
203 unsigned lower_flrp =
204 (shader->options->lower_flrp16 ? 16 : 0) |
205 (shader->options->lower_flrp32 ? 32 : 0) |
206 (shader->options->lower_flrp64 ? 64 : 0);
207
208 do {
209 progress = false;
210
211 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
212 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
213
214 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
215 NIR_PASS_V(shader, nir_lower_pack);
216
217 if (allow_copies) {
218 /* Only run this pass in the first call to
219 * radv_optimize_nir. Later calls assume that we've
220 * lowered away any copy_deref instructions and we
221 * don't want to introduce any more.
222 */
223 NIR_PASS(progress, shader, nir_opt_find_array_copies);
224 }
225
226 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
227 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
228 NIR_PASS(progress, shader, nir_remove_dead_variables,
229 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out);
230
231 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
232 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
233
234 NIR_PASS(progress, shader, nir_copy_prop);
235 NIR_PASS(progress, shader, nir_opt_remove_phis);
236 NIR_PASS(progress, shader, nir_opt_dce);
237 if (nir_opt_trivial_continues(shader)) {
238 progress = true;
239 NIR_PASS(progress, shader, nir_copy_prop);
240 NIR_PASS(progress, shader, nir_opt_remove_phis);
241 NIR_PASS(progress, shader, nir_opt_dce);
242 }
243 NIR_PASS(progress, shader, nir_opt_if, true);
244 NIR_PASS(progress, shader, nir_opt_dead_cf);
245 NIR_PASS(progress, shader, nir_opt_cse);
246 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
247 NIR_PASS(progress, shader, nir_opt_constant_folding);
248 NIR_PASS(progress, shader, nir_opt_algebraic);
249
250 if (lower_flrp != 0) {
251 bool lower_flrp_progress = false;
252 NIR_PASS(lower_flrp_progress,
253 shader,
254 nir_lower_flrp,
255 lower_flrp,
256 false /* always_precise */,
257 shader->options->lower_ffma);
258 if (lower_flrp_progress) {
259 NIR_PASS(progress, shader,
260 nir_opt_constant_folding);
261 progress = true;
262 }
263
264 /* Nothing should rematerialize any flrps, so we only
265 * need to do this lowering once.
266 */
267 lower_flrp = 0;
268 }
269
270 NIR_PASS(progress, shader, nir_opt_undef);
271 if (shader->options->max_unroll_iterations) {
272 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
273 }
274 } while (progress && !optimize_conservatively);
275
276 NIR_PASS(progress, shader, nir_opt_conditional_discard);
277 NIR_PASS(progress, shader, nir_opt_shrink_load);
278 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
279 }
280
281 static void
282 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
283 {
284 assert(glsl_type_is_vector_or_scalar(type));
285
286 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
287 unsigned length = glsl_get_vector_elements(type);
288 *size = comp_size * length,
289 *align = comp_size;
290 }
291
292 nir_shader *
293 radv_shader_compile_to_nir(struct radv_device *device,
294 struct radv_shader_module *module,
295 const char *entrypoint_name,
296 gl_shader_stage stage,
297 const VkSpecializationInfo *spec_info,
298 const VkPipelineCreateFlags flags,
299 const struct radv_pipeline_layout *layout,
300 bool use_aco)
301 {
302 nir_shader *nir;
303 const nir_shader_compiler_options *nir_options = use_aco ? &nir_options_aco :
304 &nir_options_llvm;
305 if (module->nir) {
306 /* Some things such as our meta clear/blit code will give us a NIR
307 * shader directly. In that case, we just ignore the SPIR-V entirely
308 * and just use the NIR shader */
309 nir = module->nir;
310 nir->options = nir_options;
311 nir_validate_shader(nir, "in internal shader");
312
313 assert(exec_list_length(&nir->functions) == 1);
314 } else {
315 uint32_t *spirv = (uint32_t *) module->data;
316 assert(module->size % 4 == 0);
317
318 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
319 radv_print_spirv(module->data, module->size, stderr);
320
321 uint32_t num_spec_entries = 0;
322 struct nir_spirv_specialization *spec_entries = NULL;
323 if (spec_info && spec_info->mapEntryCount > 0) {
324 num_spec_entries = spec_info->mapEntryCount;
325 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
326 for (uint32_t i = 0; i < num_spec_entries; i++) {
327 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
328 const void *data = spec_info->pData + entry.offset;
329 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
330
331 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
332 if (spec_info->dataSize == 8)
333 spec_entries[i].data64 = *(const uint64_t *)data;
334 else
335 spec_entries[i].data32 = *(const uint32_t *)data;
336 }
337 }
338 const struct spirv_to_nir_options spirv_options = {
339 .lower_ubo_ssbo_access_to_offsets = true,
340 .caps = {
341 .amd_fragment_mask = true,
342 .amd_gcn_shader = true,
343 .amd_image_read_write_lod = true,
344 .amd_shader_ballot = device->physical_device->use_shader_ballot,
345 .amd_shader_explicit_vertex_parameter = true,
346 .amd_trinary_minmax = true,
347 .demote_to_helper_invocation = device->physical_device->use_aco,
348 .derivative_group = true,
349 .descriptor_array_dynamic_indexing = true,
350 .descriptor_array_non_uniform_indexing = true,
351 .descriptor_indexing = true,
352 .device_group = true,
353 .draw_parameters = true,
354 .float_controls = true,
355 .float16 = !device->physical_device->use_aco,
356 .float64 = true,
357 .geometry_streams = true,
358 .image_ms_array = true,
359 .image_read_without_format = true,
360 .image_write_without_format = true,
361 .int8 = !device->physical_device->use_aco,
362 .int16 = !device->physical_device->use_aco,
363 .int64 = true,
364 .int64_atomics = true,
365 .multiview = true,
366 .physical_storage_buffer_address = true,
367 .post_depth_coverage = true,
368 .runtime_descriptor_array = true,
369 .shader_clock = true,
370 .shader_viewport_index_layer = true,
371 .stencil_export = true,
372 .storage_8bit = !device->physical_device->use_aco,
373 .storage_16bit = !device->physical_device->use_aco,
374 .storage_image_ms = true,
375 .subgroup_arithmetic = true,
376 .subgroup_ballot = true,
377 .subgroup_basic = true,
378 .subgroup_quad = true,
379 .subgroup_shuffle = true,
380 .subgroup_vote = true,
381 .tessellation = true,
382 .transform_feedback = true,
383 .variable_pointers = true,
384 },
385 .ubo_addr_format = nir_address_format_32bit_index_offset,
386 .ssbo_addr_format = nir_address_format_32bit_index_offset,
387 .phys_ssbo_addr_format = nir_address_format_64bit_global,
388 .push_const_addr_format = nir_address_format_logical,
389 .shared_addr_format = nir_address_format_32bit_offset,
390 .frag_coord_is_sysval = true,
391 };
392 nir = spirv_to_nir(spirv, module->size / 4,
393 spec_entries, num_spec_entries,
394 stage, entrypoint_name,
395 &spirv_options, nir_options);
396 assert(nir->info.stage == stage);
397 nir_validate_shader(nir, "after spirv_to_nir");
398
399 free(spec_entries);
400
401 /* We have to lower away local constant initializers right before we
402 * inline functions. That way they get properly initialized at the top
403 * of the function and not at the top of its caller.
404 */
405 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
406 NIR_PASS_V(nir, nir_lower_returns);
407 NIR_PASS_V(nir, nir_inline_functions);
408 NIR_PASS_V(nir, nir_opt_deref);
409
410 /* Pick off the single entrypoint that we want */
411 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
412 if (func->is_entrypoint)
413 func->name = ralloc_strdup(func, "main");
414 else
415 exec_node_remove(&func->node);
416 }
417 assert(exec_list_length(&nir->functions) == 1);
418
419 /* Make sure we lower constant initializers on output variables so that
420 * nir_remove_dead_variables below sees the corresponding stores
421 */
422 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
423
424 /* Now that we've deleted all but the main function, we can go ahead and
425 * lower the rest of the constant initializers.
426 */
427 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
428
429 /* Split member structs. We do this before lower_io_to_temporaries so that
430 * it doesn't lower system values to temporaries by accident.
431 */
432 NIR_PASS_V(nir, nir_split_var_copies);
433 NIR_PASS_V(nir, nir_split_per_member_structs);
434
435 if (nir->info.stage == MESA_SHADER_FRAGMENT && use_aco)
436 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
437 if (nir->info.stage == MESA_SHADER_FRAGMENT)
438 NIR_PASS_V(nir, nir_lower_input_attachments, true);
439
440 NIR_PASS_V(nir, nir_remove_dead_variables,
441 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
442
443 NIR_PASS_V(nir, nir_propagate_invariant);
444
445 NIR_PASS_V(nir, nir_lower_system_values);
446 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
447 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
448 }
449
450 /* Vulkan uses the separate-shader linking model */
451 nir->info.separate_shader = true;
452
453 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
454
455 if (nir->info.stage == MESA_SHADER_GEOMETRY && use_aco)
456 nir_lower_gs_intrinsics(nir, true);
457
458 static const nir_lower_tex_options tex_options = {
459 .lower_txp = ~0,
460 .lower_tg4_offsets = true,
461 };
462
463 nir_lower_tex(nir, &tex_options);
464
465 nir_lower_vars_to_ssa(nir);
466
467 if (nir->info.stage == MESA_SHADER_VERTEX ||
468 nir->info.stage == MESA_SHADER_GEOMETRY ||
469 nir->info.stage == MESA_SHADER_FRAGMENT) {
470 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
471 nir_shader_get_entrypoint(nir), true, true);
472 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
473 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
474 nir_shader_get_entrypoint(nir), true, false);
475 }
476
477 nir_split_var_copies(nir);
478
479 nir_lower_global_vars_to_local(nir);
480 nir_remove_dead_variables(nir, nir_var_function_temp);
481 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
482 .subgroup_size = 64,
483 .ballot_bit_size = 64,
484 .lower_to_scalar = 1,
485 .lower_subgroup_masks = 1,
486 .lower_shuffle = 1,
487 .lower_shuffle_to_32bit = 1,
488 .lower_vote_eq_to_ballot = 1,
489 });
490
491 nir_lower_load_const_to_scalar(nir);
492
493 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
494 radv_optimize_nir(nir, false, true);
495
496 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
497 * to remove any copies introduced by nir_opt_find_array_copies().
498 */
499 nir_lower_var_copies(nir);
500
501 /* Lower deref operations for compute shared memory. */
502 if (nir->info.stage == MESA_SHADER_COMPUTE) {
503 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
504 nir_var_mem_shared, shared_var_info);
505 NIR_PASS_V(nir, nir_lower_explicit_io,
506 nir_var_mem_shared, nir_address_format_32bit_offset);
507 }
508
509 /* Lower large variables that are always constant with load_constant
510 * intrinsics, which get turned into PC-relative loads from a data
511 * section next to the shader.
512 */
513 NIR_PASS_V(nir, nir_opt_large_constants,
514 glsl_get_natural_size_align_bytes, 16);
515
516 /* Indirect lowering must be called after the radv_optimize_nir() loop
517 * has been called at least once. Otherwise indirect lowering can
518 * bloat the instruction count of the loop and cause it to be
519 * considered too large for unrolling.
520 */
521 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
522 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
523
524 return nir;
525 }
526
527 static int
528 type_size_vec4(const struct glsl_type *type, bool bindless)
529 {
530 return glsl_count_attribute_slots(type, false);
531 }
532
533 static nir_variable *
534 find_layer_in_var(nir_shader *nir)
535 {
536 nir_foreach_variable(var, &nir->inputs) {
537 if (var->data.location == VARYING_SLOT_LAYER) {
538 return var;
539 }
540 }
541
542 nir_variable *var =
543 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
544 var->data.location = VARYING_SLOT_LAYER;
545 var->data.interpolation = INTERP_MODE_FLAT;
546 return var;
547 }
548
549 /* We use layered rendering to implement multiview, which means we need to map
550 * view_index to gl_Layer. The attachment lowering also uses needs to know the
551 * layer so that it can sample from the correct layer. The code generates a
552 * load from the layer_id sysval, but since we don't have a way to get at this
553 * information from the fragment shader, we also need to lower this to the
554 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
555 * slot, before lowering io, so that nir_assign_var_locations() will give the
556 * LAYER varying the correct driver_location.
557 */
558
559 static bool
560 lower_view_index(nir_shader *nir)
561 {
562 bool progress = false;
563 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
564 nir_builder b;
565 nir_builder_init(&b, entry);
566
567 nir_variable *layer = NULL;
568 nir_foreach_block(block, entry) {
569 nir_foreach_instr_safe(instr, block) {
570 if (instr->type != nir_instr_type_intrinsic)
571 continue;
572
573 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
574 if (load->intrinsic != nir_intrinsic_load_view_index &&
575 load->intrinsic != nir_intrinsic_load_layer_id)
576 continue;
577
578 if (!layer)
579 layer = find_layer_in_var(nir);
580
581 b.cursor = nir_before_instr(instr);
582 nir_ssa_def *def = nir_load_var(&b, layer);
583 nir_ssa_def_rewrite_uses(&load->dest.ssa,
584 nir_src_for_ssa(def));
585
586 nir_instr_remove(instr);
587 progress = true;
588 }
589 }
590
591 return progress;
592 }
593
594 void
595 radv_lower_fs_io(nir_shader *nir)
596 {
597 NIR_PASS_V(nir, lower_view_index);
598 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
599 MESA_SHADER_FRAGMENT);
600
601 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
602
603 /* This pass needs actual constants */
604 nir_opt_constant_folding(nir);
605
606 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
607 }
608
609
610 void *
611 radv_alloc_shader_memory(struct radv_device *device,
612 struct radv_shader_variant *shader)
613 {
614 mtx_lock(&device->shader_slab_mutex);
615 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
616 uint64_t offset = 0;
617 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
618 if (s->bo_offset - offset >= shader->code_size) {
619 shader->bo = slab->bo;
620 shader->bo_offset = offset;
621 list_addtail(&shader->slab_list, &s->slab_list);
622 mtx_unlock(&device->shader_slab_mutex);
623 return slab->ptr + offset;
624 }
625 offset = align_u64(s->bo_offset + s->code_size, 256);
626 }
627 if (slab->size - offset >= shader->code_size) {
628 shader->bo = slab->bo;
629 shader->bo_offset = offset;
630 list_addtail(&shader->slab_list, &slab->shaders);
631 mtx_unlock(&device->shader_slab_mutex);
632 return slab->ptr + offset;
633 }
634 }
635
636 mtx_unlock(&device->shader_slab_mutex);
637 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
638
639 slab->size = 256 * 1024;
640 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
641 RADEON_DOMAIN_VRAM,
642 RADEON_FLAG_NO_INTERPROCESS_SHARING |
643 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
644 0 : RADEON_FLAG_READ_ONLY),
645 RADV_BO_PRIORITY_SHADER);
646 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
647 list_inithead(&slab->shaders);
648
649 mtx_lock(&device->shader_slab_mutex);
650 list_add(&slab->slabs, &device->shader_slabs);
651
652 shader->bo = slab->bo;
653 shader->bo_offset = 0;
654 list_add(&shader->slab_list, &slab->shaders);
655 mtx_unlock(&device->shader_slab_mutex);
656 return slab->ptr;
657 }
658
659 void
660 radv_destroy_shader_slabs(struct radv_device *device)
661 {
662 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
663 device->ws->buffer_destroy(slab->bo);
664 free(slab);
665 }
666 mtx_destroy(&device->shader_slab_mutex);
667 }
668
669 /* For the UMR disassembler. */
670 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
671 #define DEBUGGER_NUM_MARKERS 5
672
673 static unsigned
674 radv_get_shader_binary_size(size_t code_size)
675 {
676 return code_size + DEBUGGER_NUM_MARKERS * 4;
677 }
678
679 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
680 const struct ac_shader_config *config_in,
681 const struct radv_shader_info *info,
682 gl_shader_stage stage,
683 struct ac_shader_config *config_out)
684 {
685 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
686 unsigned vgpr_comp_cnt = 0;
687 unsigned num_input_vgprs = info->num_input_vgprs;
688
689 if (stage == MESA_SHADER_FRAGMENT) {
690 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
691 }
692
693 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
694 /* +3 for scratch wave offset and VCC */
695 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
696 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
697 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
698 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
699 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
700 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
701
702 *config_out = *config_in;
703 config_out->num_vgprs = num_vgprs;
704 config_out->num_sgprs = num_sgprs;
705 config_out->num_shared_vgprs = num_shared_vgprs;
706
707 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
708 S_00B12C_SCRATCH_EN(scratch_enabled);
709
710 if (!pdevice->use_ngg_streamout) {
711 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
712 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
713 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
714 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
715 S_00B12C_SO_EN(!!info->so.num_outputs);
716 }
717
718 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
719 (info->wave_size == 32 ? 8 : 4)) |
720 S_00B848_DX10_CLAMP(1) |
721 S_00B848_FLOAT_MODE(config_out->float_mode);
722
723 if (pdevice->rad_info.chip_class >= GFX10) {
724 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
725 } else {
726 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
727 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
728 }
729
730 switch (stage) {
731 case MESA_SHADER_TESS_EVAL:
732 if (info->is_ngg) {
733 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
734 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
735 } else if (info->tes.as_es) {
736 assert(pdevice->rad_info.chip_class <= GFX8);
737 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
738
739 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
740 } else {
741 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
742 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
743
744 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
745 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
746 }
747 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
748 break;
749 case MESA_SHADER_TESS_CTRL:
750 if (pdevice->rad_info.chip_class >= GFX9) {
751 /* We need at least 2 components for LS.
752 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
753 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
754 */
755 if (pdevice->rad_info.chip_class >= GFX10) {
756 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
757 } else {
758 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
759 }
760 } else {
761 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
762 }
763 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
764 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
765 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
766 break;
767 case MESA_SHADER_VERTEX:
768 if (info->is_ngg) {
769 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
770 } else if (info->vs.as_ls) {
771 assert(pdevice->rad_info.chip_class <= GFX8);
772 /* We need at least 2 components for LS.
773 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
774 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
775 */
776 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
777 } else if (info->vs.as_es) {
778 assert(pdevice->rad_info.chip_class <= GFX8);
779 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
780 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
781 } else {
782 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
783 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
784 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
785 */
786 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
787 vgpr_comp_cnt = 3;
788 } else if (info->vs.export_prim_id) {
789 vgpr_comp_cnt = 2;
790 } else if (info->vs.needs_instance_id) {
791 vgpr_comp_cnt = 1;
792 } else {
793 vgpr_comp_cnt = 0;
794 }
795
796 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
797 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
798 }
799 break;
800 case MESA_SHADER_FRAGMENT:
801 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
802 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
803 break;
804 case MESA_SHADER_GEOMETRY:
805 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
806 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
807 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
808 break;
809 case MESA_SHADER_COMPUTE:
810 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
811 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
812 config_out->rsrc2 |=
813 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
814 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
815 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
816 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
817 info->cs.uses_thread_id[1] ? 1 : 0) |
818 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
819 S_00B84C_LDS_SIZE(config_in->lds_size);
820 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
821
822 break;
823 default:
824 unreachable("unsupported shader type");
825 break;
826 }
827
828 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
829 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
830 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
831 gl_shader_stage es_stage = stage;
832 if (stage == MESA_SHADER_GEOMETRY)
833 es_stage = info->gs.es_type;
834
835 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
836 if (es_stage == MESA_SHADER_VERTEX) {
837 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
838 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
839 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
840 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
841 } else
842 unreachable("Unexpected ES shader stage");
843
844 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
845 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
846 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
847 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
848 } else if (info->uses_prim_id) {
849 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
850 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
851 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
852 } else {
853 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
854 }
855
856 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
857 S_00B228_WGP_MODE(1);
858 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
859 S_00B22C_LDS_SIZE(config_in->lds_size) |
860 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
861 } else if (pdevice->rad_info.chip_class >= GFX9 &&
862 stage == MESA_SHADER_GEOMETRY) {
863 unsigned es_type = info->gs.es_type;
864 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
865
866 if (es_type == MESA_SHADER_VERTEX) {
867 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
868 if (info->vs.needs_instance_id) {
869 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
870 } else {
871 es_vgpr_comp_cnt = 0;
872 }
873 } else if (es_type == MESA_SHADER_TESS_EVAL) {
874 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
875 } else {
876 unreachable("invalid shader ES type");
877 }
878
879 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
880 * VGPR[0:4] are always loaded.
881 */
882 if (info->uses_invocation_id) {
883 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
884 } else if (info->uses_prim_id) {
885 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
886 } else if (info->gs.vertices_in >= 3) {
887 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
888 } else {
889 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
890 }
891
892 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
893 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
894 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
895 } else if (pdevice->rad_info.chip_class >= GFX9 &&
896 stage == MESA_SHADER_TESS_CTRL) {
897 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
898 } else {
899 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
900 }
901 }
902
903 struct radv_shader_variant *
904 radv_shader_variant_create(struct radv_device *device,
905 const struct radv_shader_binary *binary,
906 bool keep_shader_info)
907 {
908 struct ac_shader_config config = {0};
909 struct ac_rtld_binary rtld_binary = {0};
910 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
911 if (!variant)
912 return NULL;
913
914 variant->ref_count = 1;
915
916 if (binary->type == RADV_BINARY_TYPE_RTLD) {
917 struct ac_rtld_symbol lds_symbols[2];
918 unsigned num_lds_symbols = 0;
919 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
920 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
921
922 if (device->physical_device->rad_info.chip_class >= GFX9 &&
923 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
924 !binary->is_gs_copy_shader) {
925 /* We add this symbol even on LLVM <= 8 to ensure that
926 * shader->config.lds_size is set correctly below.
927 */
928 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
929 sym->name = "esgs_ring";
930 sym->size = binary->info.ngg_info.esgs_ring_size;
931 sym->align = 64 * 1024;
932 }
933
934 if (binary->info.is_ngg &&
935 binary->stage == MESA_SHADER_GEOMETRY) {
936 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
937 sym->name = "ngg_emit";
938 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
939 sym->align = 4;
940 }
941
942 struct ac_rtld_open_info open_info = {
943 .info = &device->physical_device->rad_info,
944 .shader_type = binary->stage,
945 .wave_size = binary->info.wave_size,
946 .num_parts = 1,
947 .elf_ptrs = &elf_data,
948 .elf_sizes = &elf_size,
949 .num_shared_lds_symbols = num_lds_symbols,
950 .shared_lds_symbols = lds_symbols,
951 };
952
953 if (!ac_rtld_open(&rtld_binary, open_info)) {
954 free(variant);
955 return NULL;
956 }
957
958 if (!ac_rtld_read_config(&rtld_binary, &config)) {
959 ac_rtld_close(&rtld_binary);
960 free(variant);
961 return NULL;
962 }
963
964 /* Enable 64-bit and 16-bit denormals, because there is no performance
965 * cost.
966 *
967 * If denormals are enabled, all floating-point output modifiers are
968 * ignored.
969 *
970 * Don't enable denormals for 32-bit floats, because:
971 * - Floating-point output modifiers would be ignored by the hw.
972 * - Some opcodes don't support denormals, such as v_mad_f32. We would
973 * have to stop using those.
974 * - GFX6 & GFX7 would be very slow.
975 */
976 config.float_mode |= V_00B028_FP_64_DENORMS;
977
978 if (rtld_binary.lds_size > 0) {
979 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
980 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
981 }
982
983 variant->code_size = rtld_binary.rx_size;
984 variant->exec_size = rtld_binary.exec_size;
985 } else {
986 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
987 config = ((struct radv_shader_binary_legacy *)binary)->config;
988 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
989 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
990 }
991
992 variant->info = binary->info;
993 radv_postprocess_config(device->physical_device, &config, &binary->info,
994 binary->stage, &variant->config);
995
996 if (radv_device_use_secure_compile(device->instance)) {
997 if (binary->type == RADV_BINARY_TYPE_RTLD)
998 ac_rtld_close(&rtld_binary);
999
1000 return variant;
1001 }
1002
1003 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1004
1005 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1006 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1007 struct ac_rtld_upload_info info = {
1008 .binary = &rtld_binary,
1009 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1010 .rx_ptr = dest_ptr,
1011 };
1012
1013 if (!ac_rtld_upload(&info)) {
1014 radv_shader_variant_destroy(device, variant);
1015 ac_rtld_close(&rtld_binary);
1016 return NULL;
1017 }
1018
1019 if (keep_shader_info ||
1020 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1021 const char *disasm_data;
1022 size_t disasm_size;
1023 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1024 radv_shader_variant_destroy(device, variant);
1025 ac_rtld_close(&rtld_binary);
1026 return NULL;
1027 }
1028
1029 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1030 variant->disasm_string = malloc(disasm_size + 1);
1031 memcpy(variant->disasm_string, disasm_data, disasm_size);
1032 variant->disasm_string[disasm_size] = 0;
1033 }
1034
1035 ac_rtld_close(&rtld_binary);
1036 } else {
1037 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1038 memcpy(dest_ptr, bin->data, bin->code_size);
1039
1040 /* Add end-of-code markers for the UMR disassembler. */
1041 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1042 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1043 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1044
1045 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
1046 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL;
1047 }
1048 return variant;
1049 }
1050
1051 static char *
1052 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1053 int shader_count)
1054 {
1055 char *data = NULL;
1056 char *ret = NULL;
1057 size_t size = 0;
1058 FILE *f = open_memstream(&data, &size);
1059 if (f) {
1060 for (int i = 0; i < shader_count; ++i)
1061 nir_print_shader(shaders[i], f);
1062 fclose(f);
1063 }
1064
1065 ret = malloc(size + 1);
1066 if (ret) {
1067 memcpy(ret, data, size);
1068 ret[size] = 0;
1069 }
1070 free(data);
1071 return ret;
1072 }
1073
1074 static struct radv_shader_variant *
1075 shader_variant_compile(struct radv_device *device,
1076 struct radv_shader_module *module,
1077 struct nir_shader * const *shaders,
1078 int shader_count,
1079 gl_shader_stage stage,
1080 struct radv_shader_info *info,
1081 struct radv_nir_compiler_options *options,
1082 bool gs_copy_shader,
1083 bool keep_shader_info,
1084 bool use_aco,
1085 struct radv_shader_binary **binary_out)
1086 {
1087 enum radeon_family chip_family = device->physical_device->rad_info.family;
1088 struct radv_shader_binary *binary = NULL;
1089
1090 options->family = chip_family;
1091 options->chip_class = device->physical_device->rad_info.chip_class;
1092 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1093 options->dump_preoptir = options->dump_shader &&
1094 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1095 options->record_ir = keep_shader_info;
1096 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1097 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1098 options->address32_hi = device->physical_device->rad_info.address32_hi;
1099 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1100 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1101
1102 struct radv_shader_args args = {};
1103 args.options = options;
1104 args.shader_info = info;
1105 args.is_gs_copy_shader = gs_copy_shader;
1106 radv_declare_shader_args(&args,
1107 gs_copy_shader ? MESA_SHADER_VERTEX
1108 : shaders[shader_count - 1]->info.stage,
1109 shader_count >= 2,
1110 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1111 : MESA_SHADER_VERTEX);
1112
1113 if (!use_aco || options->dump_shader || options->record_ir)
1114 ac_init_llvm_once();
1115
1116 if (use_aco) {
1117 aco_compile_shader(shader_count, shaders, &binary, &args);
1118 binary->info = *info;
1119 } else {
1120 enum ac_target_machine_options tm_options = 0;
1121 struct ac_llvm_compiler ac_llvm;
1122 bool thread_compiler;
1123
1124 tm_options |= AC_TM_SUPPORTS_SPILL;
1125 if (options->check_ir)
1126 tm_options |= AC_TM_CHECK_IR;
1127 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
1128 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
1129
1130 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
1131 radv_init_llvm_compiler(&ac_llvm,
1132 thread_compiler,
1133 chip_family, tm_options,
1134 info->wave_size);
1135
1136 if (gs_copy_shader) {
1137 assert(shader_count == 1);
1138 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
1139 &args);
1140 } else {
1141 radv_compile_nir_shader(&ac_llvm, &binary, &args,
1142 shaders, shader_count);
1143 }
1144
1145 binary->info = *info;
1146 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
1147 }
1148
1149 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1150 keep_shader_info);
1151 if (!variant) {
1152 free(binary);
1153 return NULL;
1154 }
1155 variant->aco_used = use_aco;
1156
1157 if (options->dump_shader) {
1158 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
1159 }
1160
1161
1162 if (keep_shader_info) {
1163 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1164 if (!gs_copy_shader && !module->nir) {
1165 variant->spirv = malloc(module->size);
1166 if (!variant->spirv) {
1167 free(variant);
1168 free(binary);
1169 return NULL;
1170 }
1171
1172 memcpy(variant->spirv, module->data, module->size);
1173 variant->spirv_size = module->size;
1174 }
1175 }
1176
1177 if (binary_out)
1178 *binary_out = binary;
1179 else
1180 free(binary);
1181
1182 return variant;
1183 }
1184
1185 struct radv_shader_variant *
1186 radv_shader_variant_compile(struct radv_device *device,
1187 struct radv_shader_module *module,
1188 struct nir_shader *const *shaders,
1189 int shader_count,
1190 struct radv_pipeline_layout *layout,
1191 const struct radv_shader_variant_key *key,
1192 struct radv_shader_info *info,
1193 bool keep_shader_info,
1194 bool use_aco,
1195 struct radv_shader_binary **binary_out)
1196 {
1197 struct radv_nir_compiler_options options = {0};
1198
1199 options.layout = layout;
1200 if (key)
1201 options.key = *key;
1202
1203 options.explicit_scratch_args = use_aco;
1204 options.robust_buffer_access = device->robust_buffer_access;
1205
1206 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1207 &options, false, keep_shader_info, use_aco, binary_out);
1208 }
1209
1210 struct radv_shader_variant *
1211 radv_create_gs_copy_shader(struct radv_device *device,
1212 struct nir_shader *shader,
1213 struct radv_shader_info *info,
1214 struct radv_shader_binary **binary_out,
1215 bool keep_shader_info,
1216 bool multiview, bool use_aco)
1217 {
1218 struct radv_nir_compiler_options options = {0};
1219
1220 options.explicit_scratch_args = use_aco;
1221 options.key.has_multiview_view_index = multiview;
1222
1223 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1224 info, &options, true, keep_shader_info, use_aco, binary_out);
1225 }
1226
1227 void
1228 radv_shader_variant_destroy(struct radv_device *device,
1229 struct radv_shader_variant *variant)
1230 {
1231 if (!p_atomic_dec_zero(&variant->ref_count))
1232 return;
1233
1234 mtx_lock(&device->shader_slab_mutex);
1235 list_del(&variant->slab_list);
1236 mtx_unlock(&device->shader_slab_mutex);
1237
1238 free(variant->spirv);
1239 free(variant->nir_string);
1240 free(variant->disasm_string);
1241 free(variant->ir_string);
1242 free(variant);
1243 }
1244
1245 const char *
1246 radv_get_shader_name(struct radv_shader_info *info,
1247 gl_shader_stage stage)
1248 {
1249 switch (stage) {
1250 case MESA_SHADER_VERTEX:
1251 if (info->vs.as_ls)
1252 return "Vertex Shader as LS";
1253 else if (info->vs.as_es)
1254 return "Vertex Shader as ES";
1255 else if (info->is_ngg)
1256 return "Vertex Shader as ESGS";
1257 else
1258 return "Vertex Shader as VS";
1259 case MESA_SHADER_TESS_CTRL:
1260 return "Tessellation Control Shader";
1261 case MESA_SHADER_TESS_EVAL:
1262 if (info->tes.as_es)
1263 return "Tessellation Evaluation Shader as ES";
1264 else if (info->is_ngg)
1265 return "Tessellation Evaluation Shader as ESGS";
1266 else
1267 return "Tessellation Evaluation Shader as VS";
1268 case MESA_SHADER_GEOMETRY:
1269 return "Geometry Shader";
1270 case MESA_SHADER_FRAGMENT:
1271 return "Pixel Shader";
1272 case MESA_SHADER_COMPUTE:
1273 return "Compute Shader";
1274 default:
1275 return "Unknown shader";
1276 };
1277 }
1278
1279 unsigned
1280 radv_get_max_workgroup_size(enum chip_class chip_class,
1281 gl_shader_stage stage,
1282 const unsigned *sizes)
1283 {
1284 switch (stage) {
1285 case MESA_SHADER_TESS_CTRL:
1286 return chip_class >= GFX7 ? 128 : 64;
1287 case MESA_SHADER_GEOMETRY:
1288 return chip_class >= GFX9 ? 128 : 64;
1289 case MESA_SHADER_COMPUTE:
1290 break;
1291 default:
1292 return 0;
1293 }
1294
1295 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1296 return max_workgroup_size;
1297 }
1298
1299 unsigned
1300 radv_get_max_waves(struct radv_device *device,
1301 struct radv_shader_variant *variant,
1302 gl_shader_stage stage)
1303 {
1304 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1305 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1306 uint8_t wave_size = variant->info.wave_size;
1307 struct ac_shader_config *conf = &variant->config;
1308 unsigned max_simd_waves;
1309 unsigned lds_per_wave = 0;
1310
1311 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1312
1313 if (stage == MESA_SHADER_FRAGMENT) {
1314 lds_per_wave = conf->lds_size * lds_increment +
1315 align(variant->info.ps.num_interp * 48,
1316 lds_increment);
1317 } else if (stage == MESA_SHADER_COMPUTE) {
1318 unsigned max_workgroup_size =
1319 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1320 lds_per_wave = (conf->lds_size * lds_increment) /
1321 DIV_ROUND_UP(max_workgroup_size, wave_size);
1322 }
1323
1324 if (conf->num_sgprs) {
1325 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1326 max_simd_waves =
1327 MIN2(max_simd_waves,
1328 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1329 sgprs);
1330 }
1331
1332 if (conf->num_vgprs) {
1333 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1334 max_simd_waves =
1335 MIN2(max_simd_waves,
1336 RADV_NUM_PHYSICAL_VGPRS / vgprs);
1337 }
1338
1339 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1340 * that PS can use.
1341 */
1342 if (lds_per_wave)
1343 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1344
1345 return max_simd_waves;
1346 }
1347
1348 static void
1349 generate_shader_stats(struct radv_device *device,
1350 struct radv_shader_variant *variant,
1351 gl_shader_stage stage,
1352 struct _mesa_string_buffer *buf)
1353 {
1354 struct ac_shader_config *conf = &variant->config;
1355 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1356
1357 if (stage == MESA_SHADER_FRAGMENT) {
1358 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1359 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1360 "SPI_PS_INPUT_ENA = 0x%04x\n",
1361 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1362 }
1363
1364 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1365 "SGPRS: %d\n"
1366 "VGPRS: %d\n"
1367 "Spilled SGPRs: %d\n"
1368 "Spilled VGPRs: %d\n"
1369 "PrivMem VGPRS: %d\n"
1370 "Code Size: %d bytes\n"
1371 "LDS: %d blocks\n"
1372 "Scratch: %d bytes per wave\n"
1373 "Max Waves: %d\n"
1374 "********************\n\n\n",
1375 conf->num_sgprs, conf->num_vgprs,
1376 conf->spilled_sgprs, conf->spilled_vgprs,
1377 variant->info.private_mem_vgprs, variant->exec_size,
1378 conf->lds_size, conf->scratch_bytes_per_wave,
1379 max_simd_waves);
1380 }
1381
1382 void
1383 radv_shader_dump_stats(struct radv_device *device,
1384 struct radv_shader_variant *variant,
1385 gl_shader_stage stage,
1386 FILE *file)
1387 {
1388 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1389
1390 generate_shader_stats(device, variant, stage, buf);
1391
1392 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1393 fprintf(file, "%s", buf->buf);
1394
1395 _mesa_string_buffer_destroy(buf);
1396 }
1397
1398 VkResult
1399 radv_GetShaderInfoAMD(VkDevice _device,
1400 VkPipeline _pipeline,
1401 VkShaderStageFlagBits shaderStage,
1402 VkShaderInfoTypeAMD infoType,
1403 size_t* pInfoSize,
1404 void* pInfo)
1405 {
1406 RADV_FROM_HANDLE(radv_device, device, _device);
1407 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1408 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1409 struct radv_shader_variant *variant = pipeline->shaders[stage];
1410 struct _mesa_string_buffer *buf;
1411 VkResult result = VK_SUCCESS;
1412
1413 /* Spec doesn't indicate what to do if the stage is invalid, so just
1414 * return no info for this. */
1415 if (!variant)
1416 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1417
1418 switch (infoType) {
1419 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1420 if (!pInfo) {
1421 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1422 } else {
1423 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1424 struct ac_shader_config *conf = &variant->config;
1425
1426 VkShaderStatisticsInfoAMD statistics = {};
1427 statistics.shaderStageMask = shaderStage;
1428 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1429 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1430 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1431
1432 if (stage == MESA_SHADER_COMPUTE) {
1433 unsigned *local_size = variant->info.cs.block_size;
1434 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1435
1436 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1437 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1438
1439 statistics.computeWorkGroupSize[0] = local_size[0];
1440 statistics.computeWorkGroupSize[1] = local_size[1];
1441 statistics.computeWorkGroupSize[2] = local_size[2];
1442 } else {
1443 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1444 }
1445
1446 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1447 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1448 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1449 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1450 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1451
1452 size_t size = *pInfoSize;
1453 *pInfoSize = sizeof(statistics);
1454
1455 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1456
1457 if (size < *pInfoSize)
1458 result = VK_INCOMPLETE;
1459 }
1460
1461 break;
1462 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1463 buf = _mesa_string_buffer_create(NULL, 1024);
1464
1465 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1466 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1467 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1468 generate_shader_stats(device, variant, stage, buf);
1469
1470 /* Need to include the null terminator. */
1471 size_t length = buf->length + 1;
1472
1473 if (!pInfo) {
1474 *pInfoSize = length;
1475 } else {
1476 size_t size = *pInfoSize;
1477 *pInfoSize = length;
1478
1479 memcpy(pInfo, buf->buf, MIN2(size, length));
1480
1481 if (size < length)
1482 result = VK_INCOMPLETE;
1483 }
1484
1485 _mesa_string_buffer_destroy(buf);
1486 break;
1487 default:
1488 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1489 result = VK_ERROR_FEATURE_NOT_PRESENT;
1490 break;
1491 }
1492
1493 return result;
1494 }