2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
48 #include "aco_interface.h"
50 #include "util/string_buffer.h"
52 static const struct nir_shader_compiler_options nir_options_llvm
= {
53 .vertex_id_zero_based
= true,
58 .lower_device_index_to_zero
= true,
62 .lower_bitfield_insert_to_bitfield_select
= true,
63 .lower_bitfield_extract
= true,
65 .lower_pack_snorm_2x16
= true,
66 .lower_pack_snorm_4x8
= true,
67 .lower_pack_unorm_2x16
= true,
68 .lower_pack_unorm_4x8
= true,
69 .lower_unpack_snorm_2x16
= true,
70 .lower_unpack_snorm_4x8
= true,
71 .lower_unpack_unorm_2x16
= true,
72 .lower_unpack_unorm_4x8
= true,
73 .lower_extract_byte
= true,
74 .lower_extract_word
= true,
77 .lower_mul_2x32_64
= true,
79 .max_unroll_iterations
= 32,
80 .use_interpolated_input_intrinsics
= true,
81 /* nir_lower_int64() isn't actually called for the LLVM backend, but
82 * this helps the loop unrolling heuristics. */
83 .lower_int64_options
= nir_lower_imul64
|
84 nir_lower_imul_high64
|
85 nir_lower_imul_2x32_64
|
91 static const struct nir_shader_compiler_options nir_options_aco
= {
92 .vertex_id_zero_based
= true,
97 .lower_device_index_to_zero
= true,
100 .lower_bitfield_insert_to_bitfield_select
= true,
101 .lower_bitfield_extract
= true,
102 .lower_pack_snorm_2x16
= true,
103 .lower_pack_snorm_4x8
= true,
104 .lower_pack_unorm_2x16
= true,
105 .lower_pack_unorm_4x8
= true,
106 .lower_unpack_snorm_2x16
= true,
107 .lower_unpack_snorm_4x8
= true,
108 .lower_unpack_unorm_2x16
= true,
109 .lower_unpack_unorm_4x8
= true,
110 .lower_unpack_half_2x16
= true,
111 .lower_extract_byte
= true,
112 .lower_extract_word
= true,
115 .lower_mul_2x32_64
= true,
116 .lower_rotate
= true,
117 .max_unroll_iterations
= 32,
118 .use_interpolated_input_intrinsics
= true,
119 .lower_int64_options
= nir_lower_imul64
|
120 nir_lower_imul_high64
|
121 nir_lower_imul_2x32_64
|
129 radv_can_dump_shader(struct radv_device
*device
,
130 struct radv_shader_module
*module
,
131 bool is_gs_copy_shader
)
133 if (!(device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
))
136 return !module
->nir
||
137 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_META_SHADERS
);
139 return is_gs_copy_shader
;
143 radv_can_dump_shader_stats(struct radv_device
*device
,
144 struct radv_shader_module
*module
)
146 /* Only dump non-meta shader stats. */
147 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
&&
148 module
&& !module
->nir
;
151 VkResult
radv_CreateShaderModule(
153 const VkShaderModuleCreateInfo
* pCreateInfo
,
154 const VkAllocationCallbacks
* pAllocator
,
155 VkShaderModule
* pShaderModule
)
157 RADV_FROM_HANDLE(radv_device
, device
, _device
);
158 struct radv_shader_module
*module
;
160 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
161 assert(pCreateInfo
->flags
== 0);
163 module
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
164 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
165 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
167 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
169 vk_object_base_init(&device
->vk
, &module
->base
,
170 VK_OBJECT_TYPE_SHADER_MODULE
);
173 module
->size
= pCreateInfo
->codeSize
;
174 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
176 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
178 *pShaderModule
= radv_shader_module_to_handle(module
);
183 void radv_DestroyShaderModule(
185 VkShaderModule _module
,
186 const VkAllocationCallbacks
* pAllocator
)
188 RADV_FROM_HANDLE(radv_device
, device
, _device
);
189 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
194 vk_object_base_finish(&module
->base
);
195 vk_free2(&device
->vk
.alloc
, pAllocator
, module
);
199 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
203 unsigned lower_flrp
=
204 (shader
->options
->lower_flrp16
? 16 : 0) |
205 (shader
->options
->lower_flrp32
? 32 : 0) |
206 (shader
->options
->lower_flrp64
? 64 : 0);
211 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_function_temp
);
212 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
214 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
215 NIR_PASS_V(shader
, nir_lower_pack
);
218 /* Only run this pass in the first call to
219 * radv_optimize_nir. Later calls assume that we've
220 * lowered away any copy_deref instructions and we
221 * don't want to introduce any more.
223 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
226 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
227 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
228 NIR_PASS(progress
, shader
, nir_remove_dead_variables
,
229 nir_var_function_temp
| nir_var_shader_in
| nir_var_shader_out
,
232 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
, NULL
, NULL
);
233 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
235 NIR_PASS(progress
, shader
, nir_copy_prop
);
236 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
237 NIR_PASS(progress
, shader
, nir_opt_dce
);
238 if (nir_opt_trivial_continues(shader
)) {
240 NIR_PASS(progress
, shader
, nir_copy_prop
);
241 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
242 NIR_PASS(progress
, shader
, nir_opt_dce
);
244 NIR_PASS(progress
, shader
, nir_opt_if
, true);
245 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
246 NIR_PASS(progress
, shader
, nir_opt_cse
);
247 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
248 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
249 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
251 if (lower_flrp
!= 0) {
252 bool lower_flrp_progress
= false;
253 NIR_PASS(lower_flrp_progress
,
257 false /* always_precise */,
258 shader
->options
->lower_ffma
);
259 if (lower_flrp_progress
) {
260 NIR_PASS(progress
, shader
,
261 nir_opt_constant_folding
);
265 /* Nothing should rematerialize any flrps, so we only
266 * need to do this lowering once.
271 NIR_PASS(progress
, shader
, nir_opt_undef
);
272 if (shader
->options
->max_unroll_iterations
) {
273 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
275 } while (progress
&& !optimize_conservatively
);
277 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
278 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
279 NIR_PASS(progress
, shader
, nir_opt_move
, nir_move_load_ubo
);
283 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
285 assert(glsl_type_is_vector_or_scalar(type
));
287 uint32_t comp_size
= glsl_type_is_boolean(type
) ? 4 : glsl_get_bit_size(type
) / 8;
288 unsigned length
= glsl_get_vector_elements(type
);
289 *size
= comp_size
* length
,
294 radv_shader_compile_to_nir(struct radv_device
*device
,
295 struct radv_shader_module
*module
,
296 const char *entrypoint_name
,
297 gl_shader_stage stage
,
298 const VkSpecializationInfo
*spec_info
,
299 const VkPipelineCreateFlags flags
,
300 const struct radv_pipeline_layout
*layout
,
301 unsigned subgroup_size
, unsigned ballot_bit_size
)
304 const nir_shader_compiler_options
*nir_options
=
305 device
->physical_device
->use_aco
? &nir_options_aco
:
309 /* Some things such as our meta clear/blit code will give us a NIR
310 * shader directly. In that case, we just ignore the SPIR-V entirely
311 * and just use the NIR shader */
313 nir
->options
= nir_options
;
314 nir_validate_shader(nir
, "in internal shader");
316 assert(exec_list_length(&nir
->functions
) == 1);
318 uint32_t *spirv
= (uint32_t *) module
->data
;
319 assert(module
->size
% 4 == 0);
321 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
322 radv_print_spirv(module
->data
, module
->size
, stderr
);
324 uint32_t num_spec_entries
= 0;
325 struct nir_spirv_specialization
*spec_entries
= NULL
;
326 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
327 num_spec_entries
= spec_info
->mapEntryCount
;
328 spec_entries
= calloc(num_spec_entries
, sizeof(*spec_entries
));
329 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
330 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
331 const void *data
= spec_info
->pData
+ entry
.offset
;
332 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
334 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
335 switch (entry
.size
) {
337 spec_entries
[i
].value
.u64
= *(const uint64_t *)data
;
340 spec_entries
[i
].value
.u32
= *(const uint32_t *)data
;
343 spec_entries
[i
].value
.u16
= *(const uint16_t *)data
;
346 spec_entries
[i
].value
.u8
= *(const uint8_t *)data
;
349 assert(!"Invalid spec constant size");
354 bool int8_int16_enable
= !device
->physical_device
->use_aco
||
355 device
->physical_device
->rad_info
.chip_class
>= GFX8
;
356 const struct spirv_to_nir_options spirv_options
= {
357 .lower_ubo_ssbo_access_to_offsets
= true,
359 .amd_fragment_mask
= true,
360 .amd_gcn_shader
= true,
361 .amd_image_gather_bias_lod
= true,
362 .amd_image_read_write_lod
= true,
363 .amd_shader_ballot
= device
->physical_device
->use_shader_ballot
,
364 .amd_shader_explicit_vertex_parameter
= true,
365 .amd_trinary_minmax
= true,
366 .demote_to_helper_invocation
= true,
367 .derivative_group
= true,
368 .descriptor_array_dynamic_indexing
= true,
369 .descriptor_array_non_uniform_indexing
= true,
370 .descriptor_indexing
= true,
371 .device_group
= true,
372 .draw_parameters
= true,
373 .float_controls
= true,
374 .float16
= device
->physical_device
->rad_info
.has_packed_math_16bit
&& !device
->physical_device
->use_aco
,
376 .geometry_streams
= true,
377 .image_ms_array
= true,
378 .image_read_without_format
= true,
379 .image_write_without_format
= true,
380 .int8
= int8_int16_enable
,
381 .int16
= int8_int16_enable
,
383 .int64_atomics
= true,
386 .physical_storage_buffer_address
= true,
387 .post_depth_coverage
= true,
388 .runtime_descriptor_array
= true,
389 .shader_clock
= true,
390 .shader_viewport_index_layer
= true,
391 .stencil_export
= true,
392 .storage_8bit
= true,
393 .storage_16bit
= true,
394 .storage_image_ms
= true,
395 .subgroup_arithmetic
= true,
396 .subgroup_ballot
= true,
397 .subgroup_basic
= true,
398 .subgroup_quad
= true,
399 .subgroup_shuffle
= true,
400 .subgroup_vote
= true,
401 .tessellation
= true,
402 .transform_feedback
= true,
403 .variable_pointers
= true,
405 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
406 .ssbo_addr_format
= nir_address_format_32bit_index_offset
,
407 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
408 .push_const_addr_format
= nir_address_format_logical
,
409 .shared_addr_format
= nir_address_format_32bit_offset
,
410 .frag_coord_is_sysval
= true,
412 nir
= spirv_to_nir(spirv
, module
->size
/ 4,
413 spec_entries
, num_spec_entries
,
414 stage
, entrypoint_name
,
415 &spirv_options
, nir_options
);
416 assert(nir
->info
.stage
== stage
);
417 nir_validate_shader(nir
, "after spirv_to_nir");
421 /* We have to lower away local constant initializers right before we
422 * inline functions. That way they get properly initialized at the top
423 * of the function and not at the top of its caller.
425 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_function_temp
);
426 NIR_PASS_V(nir
, nir_lower_returns
);
427 NIR_PASS_V(nir
, nir_inline_functions
);
428 NIR_PASS_V(nir
, nir_opt_deref
);
430 /* Pick off the single entrypoint that we want */
431 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
432 if (func
->is_entrypoint
)
433 func
->name
= ralloc_strdup(func
, "main");
435 exec_node_remove(&func
->node
);
437 assert(exec_list_length(&nir
->functions
) == 1);
439 /* Make sure we lower constant initializers on output variables so that
440 * nir_remove_dead_variables below sees the corresponding stores
442 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_shader_out
);
444 /* Now that we've deleted all but the main function, we can go ahead and
445 * lower the rest of the constant initializers.
447 NIR_PASS_V(nir
, nir_lower_variable_initializers
, ~0);
449 /* Split member structs. We do this before lower_io_to_temporaries so that
450 * it doesn't lower system values to temporaries by accident.
452 NIR_PASS_V(nir
, nir_split_var_copies
);
453 NIR_PASS_V(nir
, nir_split_per_member_structs
);
455 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
456 device
->physical_device
->use_aco
)
457 NIR_PASS_V(nir
, nir_lower_io_to_vector
, nir_var_shader_out
);
458 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
459 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
461 NIR_PASS_V(nir
, nir_remove_dead_variables
,
462 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
| nir_var_mem_shared
,
465 NIR_PASS_V(nir
, nir_propagate_invariant
);
467 NIR_PASS_V(nir
, nir_lower_system_values
);
468 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
469 NIR_PASS_V(nir
, radv_nir_lower_ycbcr_textures
, layout
);
470 if (device
->instance
->debug_flags
& RADV_DEBUG_DISCARD_TO_DEMOTE
)
471 NIR_PASS_V(nir
, nir_lower_discard_to_demote
);
474 /* Vulkan uses the separate-shader linking model */
475 nir
->info
.separate_shader
= true;
477 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
479 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
480 nir_lower_gs_intrinsics(nir
, true);
482 static const nir_lower_tex_options tex_options
= {
484 .lower_tg4_offsets
= true,
487 nir_lower_tex(nir
, &tex_options
);
489 nir_lower_vars_to_ssa(nir
);
491 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
492 nir
->info
.stage
== MESA_SHADER_GEOMETRY
||
493 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
494 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
495 nir_shader_get_entrypoint(nir
), true, true);
496 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
497 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
498 nir_shader_get_entrypoint(nir
), true, false);
501 nir_split_var_copies(nir
);
503 nir_lower_global_vars_to_local(nir
);
504 nir_remove_dead_variables(nir
, nir_var_function_temp
, NULL
);
505 bool gfx7minus
= device
->physical_device
->rad_info
.chip_class
<= GFX7
;
506 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
507 .subgroup_size
= subgroup_size
,
508 .ballot_bit_size
= ballot_bit_size
,
509 .lower_to_scalar
= 1,
510 .lower_subgroup_masks
= 1,
512 .lower_shuffle_to_32bit
= 1,
513 .lower_vote_eq_to_ballot
= 1,
514 .lower_quad_broadcast_dynamic
= 1,
515 .lower_quad_broadcast_dynamic_to_const
= gfx7minus
,
518 nir_lower_load_const_to_scalar(nir
);
520 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
521 radv_optimize_nir(nir
, false, true);
523 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
524 * to remove any copies introduced by nir_opt_find_array_copies().
526 nir_lower_var_copies(nir
);
528 /* Lower deref operations for compute shared memory. */
529 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
) {
530 NIR_PASS_V(nir
, nir_lower_vars_to_explicit_types
,
531 nir_var_mem_shared
, shared_var_info
);
532 NIR_PASS_V(nir
, nir_lower_explicit_io
,
533 nir_var_mem_shared
, nir_address_format_32bit_offset
);
536 /* Lower large variables that are always constant with load_constant
537 * intrinsics, which get turned into PC-relative loads from a data
538 * section next to the shader.
540 NIR_PASS_V(nir
, nir_opt_large_constants
,
541 glsl_get_natural_size_align_bytes
, 16);
543 /* Indirect lowering must be called after the radv_optimize_nir() loop
544 * has been called at least once. Otherwise indirect lowering can
545 * bloat the instruction count of the loop and cause it to be
546 * considered too large for unrolling.
548 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
549 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
555 type_size_vec4(const struct glsl_type
*type
, bool bindless
)
557 return glsl_count_attribute_slots(type
, false);
560 static nir_variable
*
561 find_layer_in_var(nir_shader
*nir
)
563 nir_foreach_variable(var
, &nir
->inputs
) {
564 if (var
->data
.location
== VARYING_SLOT_LAYER
) {
570 nir_variable_create(nir
, nir_var_shader_in
, glsl_int_type(), "layer id");
571 var
->data
.location
= VARYING_SLOT_LAYER
;
572 var
->data
.interpolation
= INTERP_MODE_FLAT
;
576 /* We use layered rendering to implement multiview, which means we need to map
577 * view_index to gl_Layer. The attachment lowering also uses needs to know the
578 * layer so that it can sample from the correct layer. The code generates a
579 * load from the layer_id sysval, but since we don't have a way to get at this
580 * information from the fragment shader, we also need to lower this to the
581 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
582 * slot, before lowering io, so that nir_assign_var_locations() will give the
583 * LAYER varying the correct driver_location.
587 lower_view_index(nir_shader
*nir
)
589 bool progress
= false;
590 nir_function_impl
*entry
= nir_shader_get_entrypoint(nir
);
592 nir_builder_init(&b
, entry
);
594 nir_variable
*layer
= NULL
;
595 nir_foreach_block(block
, entry
) {
596 nir_foreach_instr_safe(instr
, block
) {
597 if (instr
->type
!= nir_instr_type_intrinsic
)
600 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
601 if (load
->intrinsic
!= nir_intrinsic_load_view_index
&&
602 load
->intrinsic
!= nir_intrinsic_load_layer_id
)
606 layer
= find_layer_in_var(nir
);
608 b
.cursor
= nir_before_instr(instr
);
609 nir_ssa_def
*def
= nir_load_var(&b
, layer
);
610 nir_ssa_def_rewrite_uses(&load
->dest
.ssa
,
611 nir_src_for_ssa(def
));
613 nir_instr_remove(instr
);
622 radv_lower_fs_io(nir_shader
*nir
)
624 NIR_PASS_V(nir
, lower_view_index
);
625 nir_assign_io_var_locations(&nir
->inputs
, &nir
->num_inputs
,
626 MESA_SHADER_FRAGMENT
);
628 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_in
, type_size_vec4
, 0);
630 /* This pass needs actual constants */
631 nir_opt_constant_folding(nir
);
633 NIR_PASS_V(nir
, nir_io_add_const_offset_to_base
, nir_var_shader_in
);
638 radv_alloc_shader_memory(struct radv_device
*device
,
639 struct radv_shader_variant
*shader
)
641 mtx_lock(&device
->shader_slab_mutex
);
642 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
644 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
645 if (s
->bo_offset
- offset
>= shader
->code_size
) {
646 shader
->bo
= slab
->bo
;
647 shader
->bo_offset
= offset
;
648 list_addtail(&shader
->slab_list
, &s
->slab_list
);
649 mtx_unlock(&device
->shader_slab_mutex
);
650 return slab
->ptr
+ offset
;
652 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
654 if (offset
<= slab
->size
&& slab
->size
- offset
>= shader
->code_size
) {
655 shader
->bo
= slab
->bo
;
656 shader
->bo_offset
= offset
;
657 list_addtail(&shader
->slab_list
, &slab
->shaders
);
658 mtx_unlock(&device
->shader_slab_mutex
);
659 return slab
->ptr
+ offset
;
663 mtx_unlock(&device
->shader_slab_mutex
);
664 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
666 slab
->size
= MAX2(256 * 1024, shader
->code_size
);
667 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
669 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
670 (device
->physical_device
->rad_info
.cpdma_prefetch_writes_memory
?
671 0 : RADEON_FLAG_READ_ONLY
),
672 RADV_BO_PRIORITY_SHADER
);
673 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
674 list_inithead(&slab
->shaders
);
676 mtx_lock(&device
->shader_slab_mutex
);
677 list_add(&slab
->slabs
, &device
->shader_slabs
);
679 shader
->bo
= slab
->bo
;
680 shader
->bo_offset
= 0;
681 list_add(&shader
->slab_list
, &slab
->shaders
);
682 mtx_unlock(&device
->shader_slab_mutex
);
687 radv_destroy_shader_slabs(struct radv_device
*device
)
689 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
690 device
->ws
->buffer_destroy(slab
->bo
);
693 mtx_destroy(&device
->shader_slab_mutex
);
696 /* For the UMR disassembler. */
697 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
698 #define DEBUGGER_NUM_MARKERS 5
701 radv_get_shader_binary_size(size_t code_size
)
703 return code_size
+ DEBUGGER_NUM_MARKERS
* 4;
706 static void radv_postprocess_config(const struct radv_physical_device
*pdevice
,
707 const struct ac_shader_config
*config_in
,
708 const struct radv_shader_info
*info
,
709 gl_shader_stage stage
,
710 struct ac_shader_config
*config_out
)
712 bool scratch_enabled
= config_in
->scratch_bytes_per_wave
> 0;
713 unsigned vgpr_comp_cnt
= 0;
714 unsigned num_input_vgprs
= info
->num_input_vgprs
;
716 if (stage
== MESA_SHADER_FRAGMENT
) {
717 num_input_vgprs
= ac_get_fs_input_vgpr_cnt(config_in
, NULL
, NULL
);
720 unsigned num_vgprs
= MAX2(config_in
->num_vgprs
, num_input_vgprs
);
721 /* +3 for scratch wave offset and VCC */
722 unsigned num_sgprs
= MAX2(config_in
->num_sgprs
, info
->num_input_sgprs
+ 3);
723 unsigned num_shared_vgprs
= config_in
->num_shared_vgprs
;
724 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
725 assert((pdevice
->rad_info
.chip_class
>= GFX10
&& num_shared_vgprs
% 8 == 0)
726 || (pdevice
->rad_info
.chip_class
< GFX10
&& num_shared_vgprs
== 0));
727 unsigned num_shared_vgpr_blocks
= num_shared_vgprs
/ 8;
729 *config_out
= *config_in
;
730 config_out
->num_vgprs
= num_vgprs
;
731 config_out
->num_sgprs
= num_sgprs
;
732 config_out
->num_shared_vgprs
= num_shared_vgprs
;
734 config_out
->rsrc2
= S_00B12C_USER_SGPR(info
->num_user_sgprs
) |
735 S_00B12C_SCRATCH_EN(scratch_enabled
);
737 if (!pdevice
->use_ngg_streamout
) {
738 config_out
->rsrc2
|= S_00B12C_SO_BASE0_EN(!!info
->so
.strides
[0]) |
739 S_00B12C_SO_BASE1_EN(!!info
->so
.strides
[1]) |
740 S_00B12C_SO_BASE2_EN(!!info
->so
.strides
[2]) |
741 S_00B12C_SO_BASE3_EN(!!info
->so
.strides
[3]) |
742 S_00B12C_SO_EN(!!info
->so
.num_outputs
);
745 config_out
->rsrc1
= S_00B848_VGPRS((num_vgprs
- 1) /
746 (info
->wave_size
== 32 ? 8 : 4)) |
747 S_00B848_DX10_CLAMP(1) |
748 S_00B848_FLOAT_MODE(config_out
->float_mode
);
750 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
751 config_out
->rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(info
->num_user_sgprs
>> 5);
753 config_out
->rsrc1
|= S_00B228_SGPRS((num_sgprs
- 1) / 8);
754 config_out
->rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(info
->num_user_sgprs
>> 5);
758 case MESA_SHADER_TESS_EVAL
:
760 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
761 config_out
->rsrc2
|= S_00B22C_OC_LDS_EN(1);
762 } else if (info
->tes
.as_es
) {
763 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
764 vgpr_comp_cnt
= info
->uses_prim_id
? 3 : 2;
766 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
768 bool enable_prim_id
= info
->tes
.export_prim_id
|| info
->uses_prim_id
;
769 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
771 config_out
->rsrc1
|= S_00B128_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
772 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
774 config_out
->rsrc2
|= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
776 case MESA_SHADER_TESS_CTRL
:
777 if (pdevice
->rad_info
.chip_class
>= GFX9
) {
778 /* We need at least 2 components for LS.
779 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
780 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
782 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
783 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 3 : 1;
785 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 2 : 1;
788 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
790 config_out
->rsrc1
|= S_00B428_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
791 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
792 config_out
->rsrc2
|= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
794 case MESA_SHADER_VERTEX
:
796 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
797 } else if (info
->vs
.as_ls
) {
798 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
799 /* We need at least 2 components for LS.
800 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
801 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
803 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 2 : 1;
804 } else if (info
->vs
.as_es
) {
805 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
806 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
807 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 1 : 0;
809 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
810 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
811 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
813 if (info
->vs
.needs_instance_id
&& pdevice
->rad_info
.chip_class
>= GFX10
) {
815 } else if (info
->vs
.export_prim_id
) {
817 } else if (info
->vs
.needs_instance_id
) {
823 config_out
->rsrc1
|= S_00B128_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
825 config_out
->rsrc2
|= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
827 case MESA_SHADER_FRAGMENT
:
828 config_out
->rsrc1
|= S_00B028_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
829 config_out
->rsrc2
|= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
831 case MESA_SHADER_GEOMETRY
:
832 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
833 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
834 config_out
->rsrc2
|= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
836 case MESA_SHADER_COMPUTE
:
837 config_out
->rsrc1
|= S_00B848_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
838 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
840 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
841 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
842 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
843 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
844 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
845 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
846 S_00B84C_LDS_SIZE(config_in
->lds_size
);
847 config_out
->rsrc3
|= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
851 unreachable("unsupported shader type");
855 if (pdevice
->rad_info
.chip_class
>= GFX10
&& info
->is_ngg
&&
856 (stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
|| stage
== MESA_SHADER_GEOMETRY
)) {
857 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
858 gl_shader_stage es_stage
= stage
;
859 if (stage
== MESA_SHADER_GEOMETRY
)
860 es_stage
= info
->gs
.es_type
;
862 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
863 if (es_stage
== MESA_SHADER_VERTEX
) {
864 es_vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 3 : 0;
865 } else if (es_stage
== MESA_SHADER_TESS_EVAL
) {
866 bool enable_prim_id
= info
->tes
.export_prim_id
|| info
->uses_prim_id
;
867 es_vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
869 unreachable("Unexpected ES shader stage");
871 bool tes_triangles
= stage
== MESA_SHADER_TESS_EVAL
&&
872 info
->tes
.primitive_mode
>= 4; /* GL_TRIANGLES */
873 if (info
->uses_invocation_id
|| stage
== MESA_SHADER_VERTEX
) {
874 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
875 } else if (info
->uses_prim_id
) {
876 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
877 } else if (info
->gs
.vertices_in
>= 3 || tes_triangles
) {
878 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
880 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
883 config_out
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
) |
884 S_00B228_WGP_MODE(1);
885 config_out
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
886 S_00B22C_LDS_SIZE(config_in
->lds_size
) |
887 S_00B22C_OC_LDS_EN(es_stage
== MESA_SHADER_TESS_EVAL
);
888 } else if (pdevice
->rad_info
.chip_class
>= GFX9
&&
889 stage
== MESA_SHADER_GEOMETRY
) {
890 unsigned es_type
= info
->gs
.es_type
;
891 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
893 if (es_type
== MESA_SHADER_VERTEX
) {
894 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
895 if (info
->vs
.needs_instance_id
) {
896 es_vgpr_comp_cnt
= pdevice
->rad_info
.chip_class
>= GFX10
? 3 : 1;
898 es_vgpr_comp_cnt
= 0;
900 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
901 es_vgpr_comp_cnt
= info
->uses_prim_id
? 3 : 2;
903 unreachable("invalid shader ES type");
906 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
907 * VGPR[0:4] are always loaded.
909 if (info
->uses_invocation_id
) {
910 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
911 } else if (info
->uses_prim_id
) {
912 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
913 } else if (info
->gs
.vertices_in
>= 3) {
914 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
916 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
919 config_out
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
920 config_out
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
921 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
922 } else if (pdevice
->rad_info
.chip_class
>= GFX9
&&
923 stage
== MESA_SHADER_TESS_CTRL
) {
924 config_out
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
926 config_out
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
930 struct radv_shader_variant
*
931 radv_shader_variant_create(struct radv_device
*device
,
932 const struct radv_shader_binary
*binary
,
933 bool keep_shader_info
)
935 struct ac_shader_config config
= {0};
936 struct ac_rtld_binary rtld_binary
= {0};
937 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
941 variant
->ref_count
= 1;
943 if (binary
->type
== RADV_BINARY_TYPE_RTLD
) {
944 struct ac_rtld_symbol lds_symbols
[2];
945 unsigned num_lds_symbols
= 0;
946 const char *elf_data
= (const char *)((struct radv_shader_binary_rtld
*)binary
)->data
;
947 size_t elf_size
= ((struct radv_shader_binary_rtld
*)binary
)->elf_size
;
949 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
950 (binary
->stage
== MESA_SHADER_GEOMETRY
|| binary
->info
.is_ngg
) &&
951 !binary
->is_gs_copy_shader
) {
952 /* We add this symbol even on LLVM <= 8 to ensure that
953 * shader->config.lds_size is set correctly below.
955 struct ac_rtld_symbol
*sym
= &lds_symbols
[num_lds_symbols
++];
956 sym
->name
= "esgs_ring";
957 sym
->size
= binary
->info
.ngg_info
.esgs_ring_size
;
958 sym
->align
= 64 * 1024;
961 if (binary
->info
.is_ngg
&&
962 binary
->stage
== MESA_SHADER_GEOMETRY
) {
963 struct ac_rtld_symbol
*sym
= &lds_symbols
[num_lds_symbols
++];
964 sym
->name
= "ngg_emit";
965 sym
->size
= binary
->info
.ngg_info
.ngg_emit_size
* 4;
969 struct ac_rtld_open_info open_info
= {
970 .info
= &device
->physical_device
->rad_info
,
971 .shader_type
= binary
->stage
,
972 .wave_size
= binary
->info
.wave_size
,
974 .elf_ptrs
= &elf_data
,
975 .elf_sizes
= &elf_size
,
976 .num_shared_lds_symbols
= num_lds_symbols
,
977 .shared_lds_symbols
= lds_symbols
,
980 if (!ac_rtld_open(&rtld_binary
, open_info
)) {
985 if (!ac_rtld_read_config(&device
->physical_device
->rad_info
,
986 &rtld_binary
, &config
)) {
987 ac_rtld_close(&rtld_binary
);
992 if (rtld_binary
.lds_size
> 0) {
993 unsigned alloc_granularity
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
994 config
.lds_size
= align(rtld_binary
.lds_size
, alloc_granularity
) / alloc_granularity
;
997 variant
->code_size
= rtld_binary
.rx_size
;
998 variant
->exec_size
= rtld_binary
.exec_size
;
1000 assert(binary
->type
== RADV_BINARY_TYPE_LEGACY
);
1001 config
= ((struct radv_shader_binary_legacy
*)binary
)->config
;
1002 variant
->code_size
= radv_get_shader_binary_size(((struct radv_shader_binary_legacy
*)binary
)->code_size
);
1003 variant
->exec_size
= ((struct radv_shader_binary_legacy
*)binary
)->exec_size
;
1006 variant
->info
= binary
->info
;
1007 radv_postprocess_config(device
->physical_device
, &config
, &binary
->info
,
1008 binary
->stage
, &variant
->config
);
1010 if (radv_device_use_secure_compile(device
->instance
)) {
1011 if (binary
->type
== RADV_BINARY_TYPE_RTLD
)
1012 ac_rtld_close(&rtld_binary
);
1017 void *dest_ptr
= radv_alloc_shader_memory(device
, variant
);
1019 if (binary
->type
== RADV_BINARY_TYPE_RTLD
) {
1020 struct radv_shader_binary_rtld
* bin
= (struct radv_shader_binary_rtld
*)binary
;
1021 struct ac_rtld_upload_info info
= {
1022 .binary
= &rtld_binary
,
1023 .rx_va
= radv_buffer_get_va(variant
->bo
) + variant
->bo_offset
,
1027 if (!ac_rtld_upload(&info
)) {
1028 radv_shader_variant_destroy(device
, variant
);
1029 ac_rtld_close(&rtld_binary
);
1033 if (keep_shader_info
||
1034 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
)) {
1035 const char *disasm_data
;
1037 if (!ac_rtld_get_section_by_name(&rtld_binary
, ".AMDGPU.disasm", &disasm_data
, &disasm_size
)) {
1038 radv_shader_variant_destroy(device
, variant
);
1039 ac_rtld_close(&rtld_binary
);
1043 variant
->ir_string
= bin
->llvm_ir_size
? strdup((const char*)(bin
->data
+ bin
->elf_size
)) : NULL
;
1044 variant
->disasm_string
= malloc(disasm_size
+ 1);
1045 memcpy(variant
->disasm_string
, disasm_data
, disasm_size
);
1046 variant
->disasm_string
[disasm_size
] = 0;
1049 ac_rtld_close(&rtld_binary
);
1051 struct radv_shader_binary_legacy
* bin
= (struct radv_shader_binary_legacy
*)binary
;
1052 memcpy(dest_ptr
, bin
->data
+ bin
->stats_size
, bin
->code_size
);
1054 /* Add end-of-code markers for the UMR disassembler. */
1055 uint32_t *ptr32
= (uint32_t *)dest_ptr
+ bin
->code_size
/ 4;
1056 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
1057 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
1059 variant
->ir_string
= bin
->ir_size
? strdup((const char*)(bin
->data
+ bin
->stats_size
+ bin
->code_size
)) : NULL
;
1060 variant
->disasm_string
= bin
->disasm_size
? strdup((const char*)(bin
->data
+ bin
->stats_size
+ bin
->code_size
+ bin
->ir_size
)) : NULL
;
1062 if (bin
->stats_size
) {
1063 variant
->statistics
= calloc(bin
->stats_size
, 1);
1064 memcpy(variant
->statistics
, bin
->data
, bin
->stats_size
);
1071 radv_dump_nir_shaders(struct nir_shader
* const *shaders
,
1077 FILE *f
= open_memstream(&data
, &size
);
1079 for (int i
= 0; i
< shader_count
; ++i
)
1080 nir_print_shader(shaders
[i
], f
);
1084 ret
= malloc(size
+ 1);
1086 memcpy(ret
, data
, size
);
1093 static struct radv_shader_variant
*
1094 shader_variant_compile(struct radv_device
*device
,
1095 struct radv_shader_module
*module
,
1096 struct nir_shader
* const *shaders
,
1098 gl_shader_stage stage
,
1099 struct radv_shader_info
*info
,
1100 struct radv_nir_compiler_options
*options
,
1101 bool gs_copy_shader
,
1102 bool keep_shader_info
,
1103 bool keep_statistic_info
,
1104 struct radv_shader_binary
**binary_out
)
1106 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
1107 struct radv_shader_binary
*binary
= NULL
;
1109 options
->family
= chip_family
;
1110 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
1111 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
1112 options
->dump_preoptir
= options
->dump_shader
&&
1113 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
1114 options
->record_ir
= keep_shader_info
;
1115 options
->record_stats
= keep_statistic_info
;
1116 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
1117 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
1118 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
1119 options
->has_ls_vgpr_init_bug
= device
->physical_device
->rad_info
.has_ls_vgpr_init_bug
;
1120 options
->use_ngg_streamout
= device
->physical_device
->use_ngg_streamout
;
1122 struct radv_shader_args args
= {};
1123 args
.options
= options
;
1124 args
.shader_info
= info
;
1125 args
.is_gs_copy_shader
= gs_copy_shader
;
1126 radv_declare_shader_args(&args
,
1127 gs_copy_shader
? MESA_SHADER_VERTEX
1128 : shaders
[shader_count
- 1]->info
.stage
,
1130 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
1131 : MESA_SHADER_VERTEX
);
1133 if (!device
->physical_device
->use_aco
||
1134 options
->dump_shader
|| options
->record_ir
)
1135 ac_init_llvm_once();
1137 if (device
->physical_device
->use_aco
) {
1138 aco_compile_shader(shader_count
, shaders
, &binary
, &args
);
1140 llvm_compile_shader(device
, shader_count
, shaders
, &binary
, &args
);
1143 binary
->info
= *info
;
1145 struct radv_shader_variant
*variant
= radv_shader_variant_create(device
, binary
,
1152 if (options
->dump_shader
) {
1153 fprintf(stderr
, "%s", radv_get_shader_name(info
, shaders
[0]->info
.stage
));
1154 for (int i
= 1; i
< shader_count
; ++i
)
1155 fprintf(stderr
, " + %s", radv_get_shader_name(info
, shaders
[i
]->info
.stage
));
1157 fprintf(stderr
, "\ndisasm:\n%s\n", variant
->disasm_string
);
1161 if (keep_shader_info
) {
1162 variant
->nir_string
= radv_dump_nir_shaders(shaders
, shader_count
);
1163 if (!gs_copy_shader
&& !module
->nir
) {
1164 variant
->spirv
= malloc(module
->size
);
1165 if (!variant
->spirv
) {
1171 memcpy(variant
->spirv
, module
->data
, module
->size
);
1172 variant
->spirv_size
= module
->size
;
1177 *binary_out
= binary
;
1184 struct radv_shader_variant
*
1185 radv_shader_variant_compile(struct radv_device
*device
,
1186 struct radv_shader_module
*module
,
1187 struct nir_shader
*const *shaders
,
1189 struct radv_pipeline_layout
*layout
,
1190 const struct radv_shader_variant_key
*key
,
1191 struct radv_shader_info
*info
,
1192 bool keep_shader_info
, bool keep_statistic_info
,
1193 struct radv_shader_binary
**binary_out
)
1195 struct radv_nir_compiler_options options
= {0};
1197 options
.layout
= layout
;
1201 options
.explicit_scratch_args
= device
->physical_device
->use_aco
;
1202 options
.robust_buffer_access
= device
->robust_buffer_access
;
1204 return shader_variant_compile(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
, info
,
1205 &options
, false, keep_shader_info
, keep_statistic_info
, binary_out
);
1208 struct radv_shader_variant
*
1209 radv_create_gs_copy_shader(struct radv_device
*device
,
1210 struct nir_shader
*shader
,
1211 struct radv_shader_info
*info
,
1212 struct radv_shader_binary
**binary_out
,
1213 bool keep_shader_info
, bool keep_statistic_info
,
1216 struct radv_nir_compiler_options options
= {0};
1218 options
.explicit_scratch_args
= device
->physical_device
->use_aco
;
1219 options
.key
.has_multiview_view_index
= multiview
;
1221 return shader_variant_compile(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
1222 info
, &options
, true, keep_shader_info
, keep_statistic_info
, binary_out
);
1226 radv_shader_variant_destroy(struct radv_device
*device
,
1227 struct radv_shader_variant
*variant
)
1229 if (!p_atomic_dec_zero(&variant
->ref_count
))
1232 mtx_lock(&device
->shader_slab_mutex
);
1233 list_del(&variant
->slab_list
);
1234 mtx_unlock(&device
->shader_slab_mutex
);
1236 free(variant
->spirv
);
1237 free(variant
->nir_string
);
1238 free(variant
->disasm_string
);
1239 free(variant
->ir_string
);
1240 free(variant
->statistics
);
1245 radv_get_shader_name(struct radv_shader_info
*info
,
1246 gl_shader_stage stage
)
1249 case MESA_SHADER_VERTEX
:
1251 return "Vertex Shader as LS";
1252 else if (info
->vs
.as_es
)
1253 return "Vertex Shader as ES";
1254 else if (info
->is_ngg
)
1255 return "Vertex Shader as ESGS";
1257 return "Vertex Shader as VS";
1258 case MESA_SHADER_TESS_CTRL
:
1259 return "Tessellation Control Shader";
1260 case MESA_SHADER_TESS_EVAL
:
1261 if (info
->tes
.as_es
)
1262 return "Tessellation Evaluation Shader as ES";
1263 else if (info
->is_ngg
)
1264 return "Tessellation Evaluation Shader as ESGS";
1266 return "Tessellation Evaluation Shader as VS";
1267 case MESA_SHADER_GEOMETRY
:
1268 return "Geometry Shader";
1269 case MESA_SHADER_FRAGMENT
:
1270 return "Pixel Shader";
1271 case MESA_SHADER_COMPUTE
:
1272 return "Compute Shader";
1274 return "Unknown shader";
1279 radv_get_max_workgroup_size(enum chip_class chip_class
,
1280 gl_shader_stage stage
,
1281 const unsigned *sizes
)
1284 case MESA_SHADER_TESS_CTRL
:
1285 return chip_class
>= GFX7
? 128 : 64;
1286 case MESA_SHADER_GEOMETRY
:
1287 return chip_class
>= GFX9
? 128 : 64;
1288 case MESA_SHADER_COMPUTE
:
1294 unsigned max_workgroup_size
= sizes
[0] * sizes
[1] * sizes
[2];
1295 return max_workgroup_size
;
1299 radv_get_max_waves(struct radv_device
*device
,
1300 struct radv_shader_variant
*variant
,
1301 gl_shader_stage stage
)
1303 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
1304 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
1305 uint8_t wave_size
= variant
->info
.wave_size
;
1306 struct ac_shader_config
*conf
= &variant
->config
;
1307 unsigned max_simd_waves
;
1308 unsigned lds_per_wave
= 0;
1310 max_simd_waves
= device
->physical_device
->rad_info
.max_wave64_per_simd
;
1312 if (stage
== MESA_SHADER_FRAGMENT
) {
1313 lds_per_wave
= conf
->lds_size
* lds_increment
+
1314 align(variant
->info
.ps
.num_interp
* 48,
1316 } else if (stage
== MESA_SHADER_COMPUTE
) {
1317 unsigned max_workgroup_size
=
1318 radv_get_max_workgroup_size(chip_class
, stage
, variant
->info
.cs
.block_size
);
1319 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
1320 DIV_ROUND_UP(max_workgroup_size
, wave_size
);
1323 if (conf
->num_sgprs
) {
1324 unsigned sgprs
= align(conf
->num_sgprs
, chip_class
>= GFX8
? 16 : 8);
1326 MIN2(max_simd_waves
,
1327 device
->physical_device
->rad_info
.num_physical_sgprs_per_simd
/
1331 if (conf
->num_vgprs
) {
1332 unsigned vgprs
= align(conf
->num_vgprs
, wave_size
== 32 ? 8 : 4);
1334 MIN2(max_simd_waves
,
1335 device
->physical_device
->rad_info
.num_physical_wave64_vgprs_per_simd
/ vgprs
);
1338 unsigned max_lds_per_simd
= device
->physical_device
->rad_info
.lds_size_per_workgroup
/ device
->physical_device
->rad_info
.num_simd_per_compute_unit
;
1340 max_simd_waves
= MIN2(max_simd_waves
, max_lds_per_simd
/ lds_per_wave
);
1342 return max_simd_waves
;
1346 generate_shader_stats(struct radv_device
*device
,
1347 struct radv_shader_variant
*variant
,
1348 gl_shader_stage stage
,
1349 struct _mesa_string_buffer
*buf
)
1351 struct ac_shader_config
*conf
= &variant
->config
;
1352 unsigned max_simd_waves
= radv_get_max_waves(device
, variant
, stage
);
1354 if (stage
== MESA_SHADER_FRAGMENT
) {
1355 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
1356 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1357 "SPI_PS_INPUT_ENA = 0x%04x\n",
1358 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
1361 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
1364 "Spilled SGPRs: %d\n"
1365 "Spilled VGPRs: %d\n"
1366 "PrivMem VGPRS: %d\n"
1367 "Code Size: %d bytes\n"
1369 "Scratch: %d bytes per wave\n"
1371 conf
->num_sgprs
, conf
->num_vgprs
,
1372 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
1373 variant
->info
.private_mem_vgprs
, variant
->exec_size
,
1374 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
1377 if (variant
->statistics
) {
1378 _mesa_string_buffer_printf(buf
, "*** COMPILER STATS ***\n");
1379 for (unsigned i
= 0; i
< variant
->statistics
->count
; i
++) {
1380 struct radv_compiler_statistic_info
*info
= &variant
->statistics
->infos
[i
];
1381 uint32_t value
= variant
->statistics
->values
[i
];
1382 _mesa_string_buffer_printf(buf
, "%s: %lu\n", info
->name
, value
);
1386 _mesa_string_buffer_printf(buf
, "********************\n\n\n");
1390 radv_shader_dump_stats(struct radv_device
*device
,
1391 struct radv_shader_variant
*variant
,
1392 gl_shader_stage stage
,
1395 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
1397 generate_shader_stats(device
, variant
, stage
, buf
);
1399 fprintf(file
, "\n%s:\n", radv_get_shader_name(&variant
->info
, stage
));
1400 fprintf(file
, "%s", buf
->buf
);
1402 _mesa_string_buffer_destroy(buf
);
1406 radv_GetShaderInfoAMD(VkDevice _device
,
1407 VkPipeline _pipeline
,
1408 VkShaderStageFlagBits shaderStage
,
1409 VkShaderInfoTypeAMD infoType
,
1413 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1414 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
1415 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
1416 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
1417 struct _mesa_string_buffer
*buf
;
1418 VkResult result
= VK_SUCCESS
;
1420 /* Spec doesn't indicate what to do if the stage is invalid, so just
1421 * return no info for this. */
1423 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1426 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
1428 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
1430 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
1431 struct ac_shader_config
*conf
= &variant
->config
;
1433 VkShaderStatisticsInfoAMD statistics
= {};
1434 statistics
.shaderStageMask
= shaderStage
;
1435 statistics
.numPhysicalVgprs
= device
->physical_device
->rad_info
.num_physical_wave64_vgprs_per_simd
;
1436 statistics
.numPhysicalSgprs
= device
->physical_device
->rad_info
.num_physical_sgprs_per_simd
;
1437 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
1439 if (stage
== MESA_SHADER_COMPUTE
) {
1440 unsigned *local_size
= variant
->info
.cs
.block_size
;
1441 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
1443 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
1444 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
1446 statistics
.computeWorkGroupSize
[0] = local_size
[0];
1447 statistics
.computeWorkGroupSize
[1] = local_size
[1];
1448 statistics
.computeWorkGroupSize
[2] = local_size
[2];
1450 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
1453 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
1454 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
1455 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
1456 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
1457 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
1459 size_t size
= *pInfoSize
;
1460 *pInfoSize
= sizeof(statistics
);
1462 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
1464 if (size
< *pInfoSize
)
1465 result
= VK_INCOMPLETE
;
1469 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
1470 buf
= _mesa_string_buffer_create(NULL
, 1024);
1472 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(&variant
->info
, stage
));
1473 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->ir_string
);
1474 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
1475 generate_shader_stats(device
, variant
, stage
, buf
);
1477 /* Need to include the null terminator. */
1478 size_t length
= buf
->length
+ 1;
1481 *pInfoSize
= length
;
1483 size_t size
= *pInfoSize
;
1484 *pInfoSize
= length
;
1486 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
1489 result
= VK_INCOMPLETE
;
1492 _mesa_string_buffer_destroy(buf
);
1495 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1496 result
= VK_ERROR_FEATURE_NOT_PRESENT
;