src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "radv_shader_helper.h"
  34 #include "nir/nir.h"
  35 #include "nir/nir_builder.h"
  36 #include "spirv/nir_spirv.h"
  37
  38 #include <llvm-c/Core.h>
  39 #include <llvm-c/TargetMachine.h>
  40 #include <llvm-c/Support.h>
  41
  42 #include "sid.h"
  43 #include "gfx9d.h"
  44 #include "ac_binary.h"
  45 #include "ac_llvm_util.h"
  46 #include "ac_nir_to_llvm.h"
  47 #include "vk_format.h"
  48 #include "util/debug.h"
  49 #include "ac_exp_param.h"
  50
  51 #include "util/string_buffer.h"
  52
  53 static const struct nir_shader_compiler_options nir_options = {
  54         .vertex_id_zero_based = true,
  55         .lower_scmp = true,
  56         .lower_flrp16 = true,
  57         .lower_flrp32 = true,
  58         .lower_flrp64 = true,
  59         .lower_device_index_to_zero = true,
  60         .lower_fsat = true,
  61         .lower_fdiv = true,
  62         .lower_sub = true,
  63         .lower_pack_snorm_2x16 = true,
  64         .lower_pack_snorm_4x8 = true,
  65         .lower_pack_unorm_2x16 = true,
  66         .lower_pack_unorm_4x8 = true,
  67         .lower_unpack_snorm_2x16 = true,
  68         .lower_unpack_snorm_4x8 = true,
  69         .lower_unpack_unorm_2x16 = true,
  70         .lower_unpack_unorm_4x8 = true,
  71         .lower_extract_byte = true,
  72         .lower_extract_word = true,
  73         .lower_ffma = true,
  74         .lower_fpow = true,
  75         .lower_mul_2x32_64 = true,
  76         .max_unroll_iterations = 32
  77 };
  78
  79 VkResult radv_CreateShaderModule(
  80         VkDevice                                    _device,
  81         const VkShaderModuleCreateInfo*             pCreateInfo,
  82         const VkAllocationCallbacks*                pAllocator,
  83         VkShaderModule*                             pShaderModule)
  84 {
  85         RADV_FROM_HANDLE(radv_device, device, _device);
  86         struct radv_shader_module *module;
  87
  88         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  89         assert(pCreateInfo->flags == 0);
  90
  91         module = vk_alloc2(&device->alloc, pAllocator,
  92                              sizeof(*module) + pCreateInfo->codeSize, 8,
  93                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  94         if (module == NULL)
  95                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
  96
  97         module->nir = NULL;
  98         module->size = pCreateInfo->codeSize;
  99         memcpy(module->data, pCreateInfo->pCode, module->size);
 100
 101         _mesa_sha1_compute(module->data, module->size, module->sha1);
 102
 103         *pShaderModule = radv_shader_module_to_handle(module);
 104
 105         return VK_SUCCESS;
 106 }
 107
 108 void radv_DestroyShaderModule(
 109         VkDevice                                    _device,
 110         VkShaderModule                              _module,
 111         const VkAllocationCallbacks*                pAllocator)
 112 {
 113         RADV_FROM_HANDLE(radv_device, device, _device);
 114         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 115
 116         if (!module)
 117                 return;
 118
 119         vk_free2(&device->alloc, pAllocator, module);
 120 }
 121
 122 void
 123 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 124                   bool allow_copies)
 125 {
 126         bool progress;
 127
 128         do {
 129                 progress = false;
 130
 131                 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
 132                 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
 133
 134                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 135                 NIR_PASS_V(shader, nir_lower_pack);
 136
 137                 if (allow_copies) {
 138                         /* Only run this pass in the first call to
 139                          * radv_optimize_nir.  Later calls assume that we've
 140                          * lowered away any copy_deref instructions and we
 141                          *  don't want to introduce any more.
 142                         */
 143                         NIR_PASS(progress, shader, nir_opt_find_array_copies);
 144                 }
 145
 146                 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
 147                 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
 148
 149                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 150                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 151
 152                 NIR_PASS(progress, shader, nir_copy_prop);
 153                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 154                 NIR_PASS(progress, shader, nir_opt_dce);
 155                 if (nir_opt_trivial_continues(shader)) {
 156                         progress = true;
 157                         NIR_PASS(progress, shader, nir_copy_prop);
 158                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 159                         NIR_PASS(progress, shader, nir_opt_dce);
 160                 }
 161                 NIR_PASS(progress, shader, nir_opt_if, true);
 162                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 163                 NIR_PASS(progress, shader, nir_opt_cse);
 164                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
 165                 NIR_PASS(progress, shader, nir_opt_algebraic);
 166                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 167                 NIR_PASS(progress, shader, nir_opt_undef);
 168                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 169                 if (shader->options->max_unroll_iterations) {
 170                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 171                 }
 172         } while (progress && !optimize_conservatively);
 173
 174         NIR_PASS(progress, shader, nir_opt_shrink_load);
 175         NIR_PASS(progress, shader, nir_opt_move_load_ubo);
 176 }
 177
 178 nir_shader *
 179 radv_shader_compile_to_nir(struct radv_device *device,
 180                            struct radv_shader_module *module,
 181                            const char *entrypoint_name,
 182                            gl_shader_stage stage,
 183                            const VkSpecializationInfo *spec_info,
 184                            const VkPipelineCreateFlags flags)
 185 {
 186         nir_shader *nir;
 187         nir_function *entry_point;
 188         if (module->nir) {
 189                 /* Some things such as our meta clear/blit code will give us a NIR
 190                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 191                  * and just use the NIR shader */
 192                 nir = module->nir;
 193                 nir->options = &nir_options;
 194                 nir_validate_shader(nir, "in internal shader");
 195
 196                 assert(exec_list_length(&nir->functions) == 1);
 197                 struct exec_node *node = exec_list_get_head(&nir->functions);
 198                 entry_point = exec_node_data(nir_function, node, node);
 199         } else {
 200                 uint32_t *spirv = (uint32_t *) module->data;
 201                 assert(module->size % 4 == 0);
 202
 203                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 204                         radv_print_spirv(spirv, module->size, stderr);
 205
 206                 uint32_t num_spec_entries = 0;
 207                 struct nir_spirv_specialization *spec_entries = NULL;
 208                 if (spec_info && spec_info->mapEntryCount > 0) {
 209                         num_spec_entries = spec_info->mapEntryCount;
 210                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 211                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 212                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 213                                 const void *data = spec_info->pData + entry.offset;
 214                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 215
 216                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 217                                 if (spec_info->dataSize == 8)
 218                                         spec_entries[i].data64 = *(const uint64_t *)data;
 219                                 else
 220                                         spec_entries[i].data32 = *(const uint32_t *)data;
 221                         }
 222                 }
 223                 const struct spirv_to_nir_options spirv_options = {
 224                         .lower_ubo_ssbo_access_to_offsets = true,
 225                         .caps = {
 226                                 .derivative_group = true,
 227                                 .descriptor_array_dynamic_indexing = true,
 228                                 .device_group = true,
 229                                 .draw_parameters = true,
 230                                 .float16 = true,
 231                                 .float64 = true,
 232                                 .gcn_shader = true,
 233                                 .geometry_streams = true,
 234                                 .image_read_without_format = true,
 235                                 .image_write_without_format = true,
 236                                 .int8 = true,
 237                                 .int16 = true,
 238                                 .int64 = true,
 239                                 .int64_atomics = true,
 240                                 .multiview = true,
 241                                 .physical_storage_buffer_address = true,
 242                                 .runtime_descriptor_array = true,
 243                                 .shader_viewport_index_layer = true,
 244                                 .stencil_export = true,
 245                                 .storage_8bit = true,
 246                                 .storage_16bit = true,
 247                                 .storage_image_ms = true,
 248                                 .subgroup_arithmetic = true,
 249                                 .subgroup_ballot = true,
 250                                 .subgroup_basic = true,
 251                                 .subgroup_quad = true,
 252                                 .subgroup_shuffle = true,
 253                                 .subgroup_vote = true,
 254                                 .tessellation = true,
 255                                 .transform_feedback = true,
 256                                 .trinary_minmax = true,
 257                                 .variable_pointers = true,
 258                         },
 259                         .ubo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT, 2),
 260                         .ssbo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT, 2),
 261                         .phys_ssbo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT64, 1),
 262                         .push_const_ptr_type = glsl_uint_type(),
 263                         .shared_ptr_type = glsl_uint_type(),
 264                 };
 265                 entry_point = spirv_to_nir(spirv, module->size / 4,
 266                                            spec_entries, num_spec_entries,
 267                                            stage, entrypoint_name,
 268                                            &spirv_options, &nir_options);
 269                 nir = entry_point->shader;
 270                 assert(nir->info.stage == stage);
 271                 nir_validate_shader(nir, "after spirv_to_nir");
 272
 273                 free(spec_entries);
 274
 275                 /* We have to lower away local constant initializers right before we
 276                  * inline functions.  That way they get properly initialized at the top
 277                  * of the function and not at the top of its caller.
 278                  */
 279                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
 280                 NIR_PASS_V(nir, nir_lower_returns);
 281                 NIR_PASS_V(nir, nir_inline_functions);
 282                 NIR_PASS_V(nir, nir_opt_deref);
 283
 284                 /* Pick off the single entrypoint that we want */
 285                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 286                         if (func != entry_point)
 287                                 exec_node_remove(&func->node);
 288                 }
 289                 assert(exec_list_length(&nir->functions) == 1);
 290                 entry_point->name = ralloc_strdup(entry_point, "main");
 291
 292                 /* Make sure we lower constant initializers on output variables so that
 293                  * nir_remove_dead_variables below sees the corresponding stores
 294                  */
 295                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
 296
 297                 /* Now that we've deleted all but the main function, we can go ahead and
 298                  * lower the rest of the constant initializers.
 299                  */
 300                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 301
 302                 /* Split member structs.  We do this before lower_io_to_temporaries so that
 303                  * it doesn't lower system values to temporaries by accident.
 304                  */
 305                 NIR_PASS_V(nir, nir_split_var_copies);
 306                 NIR_PASS_V(nir, nir_split_per_member_structs);
 307
 308                 NIR_PASS_V(nir, nir_remove_dead_variables,
 309                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 310
 311                 NIR_PASS_V(nir, nir_lower_system_values);
 312                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 313         }
 314
 315         /* Vulkan uses the separate-shader linking model */
 316         nir->info.separate_shader = true;
 317
 318         nir_shader_gather_info(nir, entry_point->impl);
 319
 320         static const nir_lower_tex_options tex_options = {
 321           .lower_txp = ~0,
 322           .lower_tg4_offsets = true,
 323         };
 324
 325         nir_lower_tex(nir, &tex_options);
 326
 327         nir_lower_vars_to_ssa(nir);
 328
 329         if (nir->info.stage == MESA_SHADER_VERTEX ||
 330             nir->info.stage == MESA_SHADER_GEOMETRY) {
 331                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 332                            nir_shader_get_entrypoint(nir), true, true);
 333         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
 334                    nir->info.stage == MESA_SHADER_FRAGMENT) {
 335                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 336                            nir_shader_get_entrypoint(nir), true, false);
 337         }
 338
 339         nir_split_var_copies(nir);
 340
 341         nir_lower_global_vars_to_local(nir);
 342         nir_remove_dead_variables(nir, nir_var_function_temp);
 343         nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 344                         .subgroup_size = 64,
 345                         .ballot_bit_size = 64,
 346                         .lower_to_scalar = 1,
 347                         .lower_subgroup_masks = 1,
 348                         .lower_shuffle = 1,
 349                         .lower_shuffle_to_32bit = 1,
 350                         .lower_vote_eq_to_ballot = 1,
 351                 });
 352
 353         nir_lower_load_const_to_scalar(nir);
 354
 355         if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
 356                 radv_optimize_nir(nir, false, true);
 357
 358         /* We call nir_lower_var_copies() after the first radv_optimize_nir()
 359          * to remove any copies introduced by nir_opt_find_array_copies().
 360          */
 361         nir_lower_var_copies(nir);
 362
 363         /* Indirect lowering must be called after the radv_optimize_nir() loop
 364          * has been called at least once. Otherwise indirect lowering can
 365          * bloat the instruction count of the loop and cause it to be
 366          * considered too large for unrolling.
 367          */
 368         ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
 369         radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
 370
 371         return nir;
 372 }
 373
 374 void *
 375 radv_alloc_shader_memory(struct radv_device *device,
 376                          struct radv_shader_variant *shader)
 377 {
 378         mtx_lock(&device->shader_slab_mutex);
 379         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 380                 uint64_t offset = 0;
 381                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 382                         if (s->bo_offset - offset >= shader->code_size) {
 383                                 shader->bo = slab->bo;
 384                                 shader->bo_offset = offset;
 385                                 list_addtail(&shader->slab_list, &s->slab_list);
 386                                 mtx_unlock(&device->shader_slab_mutex);
 387                                 return slab->ptr + offset;
 388                         }
 389                         offset = align_u64(s->bo_offset + s->code_size, 256);
 390                 }
 391                 if (slab->size - offset >= shader->code_size) {
 392                         shader->bo = slab->bo;
 393                         shader->bo_offset = offset;
 394                         list_addtail(&shader->slab_list, &slab->shaders);
 395                         mtx_unlock(&device->shader_slab_mutex);
 396                         return slab->ptr + offset;
 397                 }
 398         }
 399
 400         mtx_unlock(&device->shader_slab_mutex);
 401         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 402
 403         slab->size = 256 * 1024;
 404         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 405                                              RADEON_DOMAIN_VRAM,
 406                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 407                                              (device->physical_device->cpdma_prefetch_writes_memory ?
 408                                                      0 : RADEON_FLAG_READ_ONLY),
 409                                              RADV_BO_PRIORITY_SHADER);
 410         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 411         list_inithead(&slab->shaders);
 412
 413         mtx_lock(&device->shader_slab_mutex);
 414         list_add(&slab->slabs, &device->shader_slabs);
 415
 416         shader->bo = slab->bo;
 417         shader->bo_offset = 0;
 418         list_add(&shader->slab_list, &slab->shaders);
 419         mtx_unlock(&device->shader_slab_mutex);
 420         return slab->ptr;
 421 }
 422
 423 void
 424 radv_destroy_shader_slabs(struct radv_device *device)
 425 {
 426         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 427                 device->ws->buffer_destroy(slab->bo);
 428                 free(slab);
 429         }
 430         mtx_destroy(&device->shader_slab_mutex);
 431 }
 432
 433 /* For the UMR disassembler. */
 434 #define DEBUGGER_END_OF_CODE_MARKER    0xbf9f0000 /* invalid instruction */
 435 #define DEBUGGER_NUM_MARKERS           5
 436
 437 static unsigned
 438 radv_get_shader_binary_size(struct ac_shader_binary *binary)
 439 {
 440         return binary->code_size + DEBUGGER_NUM_MARKERS * 4;
 441 }
 442
 443 static void
 444 radv_fill_shader_variant(struct radv_device *device,
 445                          struct radv_shader_variant *variant,
 446                          struct ac_shader_binary *binary,
 447                          gl_shader_stage stage)
 448 {
 449         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 450         struct radv_shader_info *info = &variant->info.info;
 451         unsigned vgpr_comp_cnt = 0;
 452
 453         variant->code_size = radv_get_shader_binary_size(binary);
 454         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 455                          S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
 456                          S_00B12C_SCRATCH_EN(scratch_enabled) |
 457                          S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
 458                          S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
 459                          S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
 460                          S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
 461                          S_00B12C_SO_EN(!!info->so.num_outputs);
 462
 463         variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 464                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 465                 S_00B848_DX10_CLAMP(1) |
 466                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 467
 468         switch (stage) {
 469         case MESA_SHADER_TESS_EVAL:
 470                 vgpr_comp_cnt = 3;
 471                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 472                 break;
 473         case MESA_SHADER_TESS_CTRL:
 474                 if (device->physical_device->rad_info.chip_class >= GFX9) {
 475                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 476                 } else {
 477                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 478                 }
 479                 break;
 480         case MESA_SHADER_VERTEX:
 481         case MESA_SHADER_GEOMETRY:
 482                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 483                 break;
 484         case MESA_SHADER_FRAGMENT:
 485                 break;
 486         case MESA_SHADER_COMPUTE:
 487                 variant->rsrc2 |=
 488                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 489                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 490                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 491                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 492                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 493                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 494                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 495                 break;
 496         default:
 497                 unreachable("unsupported shader type");
 498                 break;
 499         }
 500
 501         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 502             stage == MESA_SHADER_GEOMETRY) {
 503                 unsigned es_type = variant->info.gs.es_type;
 504                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 505
 506                 if (es_type == MESA_SHADER_VERTEX) {
 507                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 508                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 509                         es_vgpr_comp_cnt = 3;
 510                 } else {
 511                         unreachable("invalid shader ES type");
 512                 }
 513
 514                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 515                  * VGPR[0:4] are always loaded.
 516                  */
 517                 if (info->uses_invocation_id) {
 518                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 519                 } else if (info->uses_prim_id) {
 520                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 521                 } else if (variant->info.gs.vertices_in >= 3) {
 522                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 523                 } else {
 524                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 525                 }
 526
 527                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 528                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 529                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 530         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 531                    stage == MESA_SHADER_TESS_CTRL) {
 532                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 533         } else {
 534                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 535         }
 536
 537         void *ptr = radv_alloc_shader_memory(device, variant);
 538         memcpy(ptr, binary->code, binary->code_size);
 539
 540         /* Add end-of-code markers for the UMR disassembler. */
 541        uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4;
 542        for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
 543                 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
 544
 545 }
 546
 547 static void radv_init_llvm_target()
 548 {
 549         LLVMInitializeAMDGPUTargetInfo();
 550         LLVMInitializeAMDGPUTarget();
 551         LLVMInitializeAMDGPUTargetMC();
 552         LLVMInitializeAMDGPUAsmPrinter();
 553
 554         /* For inline assembly. */
 555         LLVMInitializeAMDGPUAsmParser();
 556
 557         /* Workaround for bug in llvm 4.0 that causes image intrinsics
 558          * to disappear.
 559          * https://reviews.llvm.org/D26348
 560          *
 561          * Workaround for bug in llvm that causes the GPU to hang in presence
 562          * of nested loops because there is an exec mask issue. The proper
 563          * solution is to fix LLVM but this might require a bunch of work.
 564          * https://bugs.llvm.org/show_bug.cgi?id=37744
 565          *
 566          * "mesa" is the prefix for error messages.
 567          */
 568         if (HAVE_LLVM >= 0x0800) {
 569                 const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
 570                 LLVMParseCommandLineOptions(2, argv, NULL);
 571
 572         } else {
 573                 const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
 574                                         "-amdgpu-skip-threshold=1" };
 575                 LLVMParseCommandLineOptions(3, argv, NULL);
 576         }
 577 }
 578
 579 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
 580
 581 static void radv_init_llvm_once(void)
 582 {
 583         call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
 584 }
 585
 586 static struct radv_shader_variant *
 587 shader_variant_create(struct radv_device *device,
 588                       struct radv_shader_module *module,
 589                       struct nir_shader * const *shaders,
 590                       int shader_count,
 591                       gl_shader_stage stage,
 592                       struct radv_nir_compiler_options *options,
 593                       bool gs_copy_shader,
 594                       void **code_out,
 595                       unsigned *code_size_out)
 596 {
 597         enum radeon_family chip_family = device->physical_device->rad_info.family;
 598         enum ac_target_machine_options tm_options = 0;
 599         struct radv_shader_variant *variant;
 600         struct ac_shader_binary binary;
 601         struct ac_llvm_compiler ac_llvm;
 602         bool thread_compiler;
 603         variant = calloc(1, sizeof(struct radv_shader_variant));
 604         if (!variant)
 605                 return NULL;
 606
 607         options->family = chip_family;
 608         options->chip_class = device->physical_device->rad_info.chip_class;
 609         options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
 610         options->dump_preoptir = options->dump_shader &&
 611                                  device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
 612         options->record_llvm_ir = device->keep_shader_info;
 613         options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
 614         options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
 615         options->address32_hi = device->physical_device->rad_info.address32_hi;
 616
 617         if (options->supports_spill)
 618                 tm_options |= AC_TM_SUPPORTS_SPILL;
 619         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 620                 tm_options |= AC_TM_SISCHED;
 621         if (options->check_ir)
 622                 tm_options |= AC_TM_CHECK_IR;
 623
 624         thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
 625         radv_init_llvm_once();
 626         radv_init_llvm_compiler(&ac_llvm,
 627                                 thread_compiler,
 628                                 chip_family, tm_options);
 629         if (gs_copy_shader) {
 630                 assert(shader_count == 1);
 631                 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
 632                                             &variant->config, &variant->info,
 633                                             options);
 634         } else {
 635                 radv_compile_nir_shader(&ac_llvm, &binary, &variant->config,
 636                                         &variant->info, shaders, shader_count,
 637                                         options);
 638         }
 639
 640         radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
 641
 642         radv_fill_shader_variant(device, variant, &binary, stage);
 643
 644         if (code_out) {
 645                 *code_out = binary.code;
 646                 *code_size_out = binary.code_size;
 647         } else
 648                 free(binary.code);
 649         free(binary.config);
 650         free(binary.rodata);
 651         free(binary.global_symbol_offsets);
 652         free(binary.relocs);
 653         variant->ref_count = 1;
 654
 655         if (device->keep_shader_info) {
 656                 variant->disasm_string = binary.disasm_string;
 657                 variant->llvm_ir_string = binary.llvm_ir_string;
 658                 if (!gs_copy_shader && !module->nir) {
 659                         variant->nir = *shaders;
 660                         variant->spirv = (uint32_t *)module->data;
 661                         variant->spirv_size = module->size;
 662                 }
 663         } else {
 664                 free(binary.disasm_string);
 665         }
 666
 667         return variant;
 668 }
 669
 670 struct radv_shader_variant *
 671 radv_shader_variant_create(struct radv_device *device,
 672                            struct radv_shader_module *module,
 673                            struct nir_shader *const *shaders,
 674                            int shader_count,
 675                            struct radv_pipeline_layout *layout,
 676                            const struct radv_shader_variant_key *key,
 677                            void **code_out,
 678                            unsigned *code_size_out)
 679 {
 680         struct radv_nir_compiler_options options = {0};
 681
 682         options.layout = layout;
 683         if (key)
 684                 options.key = *key;
 685
 686         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 687         options.supports_spill = true;
 688
 689         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 690                                      &options, false, code_out, code_size_out);
 691 }
 692
 693 struct radv_shader_variant *
 694 radv_create_gs_copy_shader(struct radv_device *device,
 695                            struct nir_shader *shader,
 696                            void **code_out,
 697                            unsigned *code_size_out,
 698                            bool multiview)
 699 {
 700         struct radv_nir_compiler_options options = {0};
 701
 702         options.key.has_multiview_view_index = multiview;
 703
 704         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 705                                      &options, true, code_out, code_size_out);
 706 }
 707
 708 void
 709 radv_shader_variant_destroy(struct radv_device *device,
 710                             struct radv_shader_variant *variant)
 711 {
 712         if (!p_atomic_dec_zero(&variant->ref_count))
 713                 return;
 714
 715         mtx_lock(&device->shader_slab_mutex);
 716         list_del(&variant->slab_list);
 717         mtx_unlock(&device->shader_slab_mutex);
 718
 719         ralloc_free(variant->nir);
 720         free(variant->disasm_string);
 721         free(variant->llvm_ir_string);
 722         free(variant);
 723 }
 724
 725 const char *
 726 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 727 {
 728         switch (stage) {
 729         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 730         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 731         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 732         case MESA_SHADER_COMPUTE: return "Compute Shader";
 733         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 734         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 735         default:
 736                 return "Unknown shader";
 737         };
 738 }
 739
 740 static void
 741 generate_shader_stats(struct radv_device *device,
 742                       struct radv_shader_variant *variant,
 743                       gl_shader_stage stage,
 744                       struct _mesa_string_buffer *buf)
 745 {
 746         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 747         unsigned lds_increment = chip_class >= CIK ? 512 : 256;
 748         struct ac_shader_config *conf;
 749         unsigned max_simd_waves;
 750         unsigned lds_per_wave = 0;
 751
 752         max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
 753
 754         conf = &variant->config;
 755
 756         if (stage == MESA_SHADER_FRAGMENT) {
 757                 lds_per_wave = conf->lds_size * lds_increment +
 758                                align(variant->info.fs.num_interp * 48,
 759                                      lds_increment);
 760         } else if (stage == MESA_SHADER_COMPUTE) {
 761                 unsigned max_workgroup_size =
 762                                 radv_nir_get_max_workgroup_size(chip_class, variant->nir);
 763                 lds_per_wave = (conf->lds_size * lds_increment) /
 764                                DIV_ROUND_UP(max_workgroup_size, 64);
 765         }
 766
 767         if (conf->num_sgprs)
 768                 max_simd_waves =
 769                         MIN2(max_simd_waves,
 770                              ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs);
 771
 772         if (conf->num_vgprs)
 773                 max_simd_waves =
 774                         MIN2(max_simd_waves,
 775                              RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
 776
 777         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 778          * that PS can use.
 779          */
 780         if (lds_per_wave)
 781                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 782
 783         if (stage == MESA_SHADER_FRAGMENT) {
 784                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 785                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 786                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 787                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 788         }
 789
 790         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 791                                    "SGPRS: %d\n"
 792                                    "VGPRS: %d\n"
 793                                    "Spilled SGPRs: %d\n"
 794                                    "Spilled VGPRs: %d\n"
 795                                    "PrivMem VGPRS: %d\n"
 796                                    "Code Size: %d bytes\n"
 797                                    "LDS: %d blocks\n"
 798                                    "Scratch: %d bytes per wave\n"
 799                                    "Max Waves: %d\n"
 800                                    "********************\n\n\n",
 801                                    conf->num_sgprs, conf->num_vgprs,
 802                                    conf->spilled_sgprs, conf->spilled_vgprs,
 803                                    variant->info.private_mem_vgprs, variant->code_size,
 804                                    conf->lds_size, conf->scratch_bytes_per_wave,
 805                                    max_simd_waves);
 806 }
 807
 808 void
 809 radv_shader_dump_stats(struct radv_device *device,
 810                        struct radv_shader_variant *variant,
 811                        gl_shader_stage stage,
 812                        FILE *file)
 813 {
 814         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 815
 816         generate_shader_stats(device, variant, stage, buf);
 817
 818         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 819         fprintf(file, "%s", buf->buf);
 820
 821         _mesa_string_buffer_destroy(buf);
 822 }
 823
 824 VkResult
 825 radv_GetShaderInfoAMD(VkDevice _device,
 826                       VkPipeline _pipeline,
 827                       VkShaderStageFlagBits shaderStage,
 828                       VkShaderInfoTypeAMD infoType,
 829                       size_t* pInfoSize,
 830                       void* pInfo)
 831 {
 832         RADV_FROM_HANDLE(radv_device, device, _device);
 833         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 834         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 835         struct radv_shader_variant *variant = pipeline->shaders[stage];
 836         struct _mesa_string_buffer *buf;
 837         VkResult result = VK_SUCCESS;
 838
 839         /* Spec doesn't indicate what to do if the stage is invalid, so just
 840          * return no info for this. */
 841         if (!variant)
 842                 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
 843
 844         switch (infoType) {
 845         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 846                 if (!pInfo) {
 847                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 848                 } else {
 849                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 850                         struct ac_shader_config *conf = &variant->config;
 851
 852                         VkShaderStatisticsInfoAMD statistics = {};
 853                         statistics.shaderStageMask = shaderStage;
 854                         statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
 855                         statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class);
 856                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 857
 858                         if (stage == MESA_SHADER_COMPUTE) {
 859                                 unsigned *local_size = variant->nir->info.cs.local_size;
 860                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 861
 862                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 863                                                                ceil((double)workgroup_size / statistics.numPhysicalVgprs);
 864
 865                                 statistics.computeWorkGroupSize[0] = local_size[0];
 866                                 statistics.computeWorkGroupSize[1] = local_size[1];
 867                                 statistics.computeWorkGroupSize[2] = local_size[2];
 868                         } else {
 869                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 870                         }
 871
 872                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 873                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 874                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 875                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 876                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 877
 878                         size_t size = *pInfoSize;
 879                         *pInfoSize = sizeof(statistics);
 880
 881                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 882
 883                         if (size < *pInfoSize)
 884                                 result = VK_INCOMPLETE;
 885                 }
 886
 887                 break;
 888         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 889                 buf = _mesa_string_buffer_create(NULL, 1024);
 890
 891                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 892                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
 893                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 894                 generate_shader_stats(device, variant, stage, buf);
 895
 896                 /* Need to include the null terminator. */
 897                 size_t length = buf->length + 1;
 898
 899                 if (!pInfo) {
 900                         *pInfoSize = length;
 901                 } else {
 902                         size_t size = *pInfoSize;
 903                         *pInfoSize = length;
 904
 905                         memcpy(pInfo, buf->buf, MIN2(size, length));
 906
 907                         if (size < length)
 908                                 result = VK_INCOMPLETE;
 909                 }
 910
 911                 _mesa_string_buffer_destroy(buf);
 912                 break;
 913         default:
 914                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 915                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 916                 break;
 917         }
 918
 919         return result;
 920 }