src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "nir/nir.h"
  34 #include "nir/nir_builder.h"
  35 #include "spirv/nir_spirv.h"
  36
  37 #include <llvm-c/Core.h>
  38 #include <llvm-c/TargetMachine.h>
  39
  40 #include "sid.h"
  41 #include "gfx9d.h"
  42 #include "ac_binary.h"
  43 #include "ac_llvm_util.h"
  44 #include "ac_nir_to_llvm.h"
  45 #include "vk_format.h"
  46 #include "util/debug.h"
  47 #include "ac_exp_param.h"
  48
  49 #include "util/string_buffer.h"
  50
  51 static const struct nir_shader_compiler_options nir_options = {
  52         .vertex_id_zero_based = true,
  53         .lower_scmp = true,
  54         .lower_flrp32 = true,
  55         .lower_flrp64 = true,
  56         .lower_device_index_to_zero = true,
  57         .lower_fsat = true,
  58         .lower_fdiv = true,
  59         .lower_sub = true,
  60         .lower_pack_snorm_2x16 = true,
  61         .lower_pack_snorm_4x8 = true,
  62         .lower_pack_unorm_2x16 = true,
  63         .lower_pack_unorm_4x8 = true,
  64         .lower_unpack_snorm_2x16 = true,
  65         .lower_unpack_snorm_4x8 = true,
  66         .lower_unpack_unorm_2x16 = true,
  67         .lower_unpack_unorm_4x8 = true,
  68         .lower_extract_byte = true,
  69         .lower_extract_word = true,
  70         .lower_ffma = true,
  71         .lower_fpow = true,
  72         .vs_inputs_dual_locations = true,
  73         .max_unroll_iterations = 32
  74 };
  75
  76 VkResult radv_CreateShaderModule(
  77         VkDevice                                    _device,
  78         const VkShaderModuleCreateInfo*             pCreateInfo,
  79         const VkAllocationCallbacks*                pAllocator,
  80         VkShaderModule*                             pShaderModule)
  81 {
  82         RADV_FROM_HANDLE(radv_device, device, _device);
  83         struct radv_shader_module *module;
  84
  85         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  86         assert(pCreateInfo->flags == 0);
  87
  88         module = vk_alloc2(&device->alloc, pAllocator,
  89                              sizeof(*module) + pCreateInfo->codeSize, 8,
  90                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  91         if (module == NULL)
  92                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  93
  94         module->nir = NULL;
  95         module->size = pCreateInfo->codeSize;
  96         memcpy(module->data, pCreateInfo->pCode, module->size);
  97
  98         _mesa_sha1_compute(module->data, module->size, module->sha1);
  99
 100         *pShaderModule = radv_shader_module_to_handle(module);
 101
 102         return VK_SUCCESS;
 103 }
 104
 105 void radv_DestroyShaderModule(
 106         VkDevice                                    _device,
 107         VkShaderModule                              _module,
 108         const VkAllocationCallbacks*                pAllocator)
 109 {
 110         RADV_FROM_HANDLE(radv_device, device, _device);
 111         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 112
 113         if (!module)
 114                 return;
 115
 116         vk_free2(&device->alloc, pAllocator, module);
 117 }
 118
 119 void
 120 radv_optimize_nir(struct nir_shader *shader)
 121 {
 122         bool progress;
 123
 124         do {
 125                 progress = false;
 126
 127                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 128                 NIR_PASS_V(shader, nir_lower_64bit_pack);
 129                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 130                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 131
 132                 NIR_PASS(progress, shader, nir_copy_prop);
 133                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 134                 NIR_PASS(progress, shader, nir_opt_dce);
 135                 if (nir_opt_trivial_continues(shader)) {
 136                         progress = true;
 137                         NIR_PASS(progress, shader, nir_copy_prop);
 138                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 139                         NIR_PASS(progress, shader, nir_opt_dce);
 140                 }
 141                 NIR_PASS(progress, shader, nir_opt_if);
 142                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 143                 NIR_PASS(progress, shader, nir_opt_cse);
 144                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
 145                 NIR_PASS(progress, shader, nir_opt_algebraic);
 146                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 147                 NIR_PASS(progress, shader, nir_opt_undef);
 148                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 149                 if (shader->options->max_unroll_iterations) {
 150                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 151                 }
 152         } while (progress);
 153
 154         NIR_PASS(progress, shader, nir_opt_shrink_load);
 155         NIR_PASS(progress, shader, nir_opt_move_load_ubo);
 156 }
 157
 158 nir_shader *
 159 radv_shader_compile_to_nir(struct radv_device *device,
 160                            struct radv_shader_module *module,
 161                            const char *entrypoint_name,
 162                            gl_shader_stage stage,
 163                            const VkSpecializationInfo *spec_info)
 164 {
 165         if (strcmp(entrypoint_name, "main") != 0) {
 166                 radv_finishme("Multiple shaders per module not really supported");
 167         }
 168
 169         nir_shader *nir;
 170         nir_function *entry_point;
 171         if (module->nir) {
 172                 /* Some things such as our meta clear/blit code will give us a NIR
 173                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 174                  * and just use the NIR shader */
 175                 nir = module->nir;
 176                 nir->options = &nir_options;
 177                 nir_validate_shader(nir);
 178
 179                 assert(exec_list_length(&nir->functions) == 1);
 180                 struct exec_node *node = exec_list_get_head(&nir->functions);
 181                 entry_point = exec_node_data(nir_function, node, node);
 182         } else {
 183                 uint32_t *spirv = (uint32_t *) module->data;
 184                 assert(module->size % 4 == 0);
 185
 186                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 187                         radv_print_spirv(spirv, module->size, stderr);
 188
 189                 uint32_t num_spec_entries = 0;
 190                 struct nir_spirv_specialization *spec_entries = NULL;
 191                 if (spec_info && spec_info->mapEntryCount > 0) {
 192                         num_spec_entries = spec_info->mapEntryCount;
 193                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 194                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 195                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 196                                 const void *data = spec_info->pData + entry.offset;
 197                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 198
 199                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 200                                 if (spec_info->dataSize == 8)
 201                                         spec_entries[i].data64 = *(const uint64_t *)data;
 202                                 else
 203                                         spec_entries[i].data32 = *(const uint32_t *)data;
 204                         }
 205                 }
 206                 const struct spirv_to_nir_options spirv_options = {
 207                         .caps = {
 208                                 .device_group = true,
 209                                 .draw_parameters = true,
 210                                 .float64 = true,
 211                                 .image_read_without_format = true,
 212                                 .image_write_without_format = true,
 213                                 .tessellation = true,
 214                                 .int64 = true,
 215                                 .multiview = true,
 216                                 .subgroup_basic = true,
 217                                 .variable_pointers = true,
 218                                 .gcn_shader = true,
 219                                 .trinary_minmax = true,
 220                         },
 221                 };
 222                 entry_point = spirv_to_nir(spirv, module->size / 4,
 223                                            spec_entries, num_spec_entries,
 224                                            stage, entrypoint_name,
 225                                            &spirv_options, &nir_options);
 226                 nir = entry_point->shader;
 227                 assert(nir->info.stage == stage);
 228                 nir_validate_shader(nir);
 229
 230                 free(spec_entries);
 231
 232                 /* We have to lower away local constant initializers right before we
 233                  * inline functions.  That way they get properly initialized at the top
 234                  * of the function and not at the top of its caller.
 235                  */
 236                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
 237                 NIR_PASS_V(nir, nir_lower_returns);
 238                 NIR_PASS_V(nir, nir_inline_functions);
 239
 240                 /* Pick off the single entrypoint that we want */
 241                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 242                         if (func != entry_point)
 243                                 exec_node_remove(&func->node);
 244                 }
 245                 assert(exec_list_length(&nir->functions) == 1);
 246                 entry_point->name = ralloc_strdup(entry_point, "main");
 247
 248                 /* Make sure we lower constant initializers on output variables so that
 249                  * nir_remove_dead_variables below sees the corresponding stores
 250                  */
 251                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
 252
 253                 NIR_PASS_V(nir, nir_remove_dead_variables,
 254                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 255
 256                 /* Now that we've deleted all but the main function, we can go ahead and
 257                  * lower the rest of the constant initializers.
 258                  */
 259                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 260                 NIR_PASS_V(nir, nir_lower_system_values);
 261                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 262         }
 263
 264         /* Vulkan uses the separate-shader linking model */
 265         nir->info.separate_shader = true;
 266
 267         nir_shader_gather_info(nir, entry_point->impl);
 268
 269         static const nir_lower_tex_options tex_options = {
 270           .lower_txp = ~0,
 271         };
 272
 273         nir_lower_tex(nir, &tex_options);
 274
 275         nir_lower_vars_to_ssa(nir);
 276         nir_lower_var_copies(nir);
 277         nir_lower_global_vars_to_local(nir);
 278         nir_remove_dead_variables(nir, nir_var_local);
 279         nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 280                         .subgroup_size = 64,
 281                         .ballot_bit_size = 64,
 282                         .lower_to_scalar = 1,
 283                         .lower_subgroup_masks = 1,
 284                         .lower_shuffle = 1,
 285                         .lower_quad =  1,
 286                 });
 287
 288         radv_optimize_nir(nir);
 289
 290         /* Indirect lowering must be called after the radv_optimize_nir() loop
 291          * has been called at least once. Otherwise indirect lowering can
 292          * bloat the instruction count of the loop and cause it to be
 293          * considered too large for unrolling.
 294          */
 295         ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
 296         radv_optimize_nir(nir);
 297
 298         return nir;
 299 }
 300
 301 void *
 302 radv_alloc_shader_memory(struct radv_device *device,
 303                          struct radv_shader_variant *shader)
 304 {
 305         mtx_lock(&device->shader_slab_mutex);
 306         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 307                 uint64_t offset = 0;
 308                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 309                         if (s->bo_offset - offset >= shader->code_size) {
 310                                 shader->bo = slab->bo;
 311                                 shader->bo_offset = offset;
 312                                 list_addtail(&shader->slab_list, &s->slab_list);
 313                                 mtx_unlock(&device->shader_slab_mutex);
 314                                 return slab->ptr + offset;
 315                         }
 316                         offset = align_u64(s->bo_offset + s->code_size, 256);
 317                 }
 318                 if (slab->size - offset >= shader->code_size) {
 319                         shader->bo = slab->bo;
 320                         shader->bo_offset = offset;
 321                         list_addtail(&shader->slab_list, &slab->shaders);
 322                         mtx_unlock(&device->shader_slab_mutex);
 323                         return slab->ptr + offset;
 324                 }
 325         }
 326
 327         mtx_unlock(&device->shader_slab_mutex);
 328         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 329
 330         slab->size = 256 * 1024;
 331         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 332                                              RADEON_DOMAIN_VRAM,
 333                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 334                                              device->physical_device->cpdma_prefetch_writes_memory ?
 335                                                      0 : RADEON_FLAG_READ_ONLY);
 336         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 337         list_inithead(&slab->shaders);
 338
 339         mtx_lock(&device->shader_slab_mutex);
 340         list_add(&slab->slabs, &device->shader_slabs);
 341
 342         shader->bo = slab->bo;
 343         shader->bo_offset = 0;
 344         list_add(&shader->slab_list, &slab->shaders);
 345         mtx_unlock(&device->shader_slab_mutex);
 346         return slab->ptr;
 347 }
 348
 349 void
 350 radv_destroy_shader_slabs(struct radv_device *device)
 351 {
 352         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 353                 device->ws->buffer_destroy(slab->bo);
 354                 free(slab);
 355         }
 356         mtx_destroy(&device->shader_slab_mutex);
 357 }
 358
 359 static void
 360 radv_fill_shader_variant(struct radv_device *device,
 361                          struct radv_shader_variant *variant,
 362                          struct ac_shader_binary *binary,
 363                          gl_shader_stage stage)
 364 {
 365         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 366         unsigned vgpr_comp_cnt = 0;
 367
 368         if (scratch_enabled && !device->llvm_supports_spill)
 369                 radv_finishme("shader scratch support only available with LLVM 4.0");
 370
 371         variant->code_size = binary->code_size;
 372         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 373                         S_00B12C_SCRATCH_EN(scratch_enabled);
 374
 375         variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 376                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 377                 S_00B848_DX10_CLAMP(1) |
 378                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 379
 380         switch (stage) {
 381         case MESA_SHADER_TESS_EVAL:
 382                 vgpr_comp_cnt = 3;
 383                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 384                 break;
 385         case MESA_SHADER_TESS_CTRL:
 386                 if (device->physical_device->rad_info.chip_class >= GFX9)
 387                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 388                 else
 389                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 390                 break;
 391         case MESA_SHADER_VERTEX:
 392         case MESA_SHADER_GEOMETRY:
 393                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 394                 break;
 395         case MESA_SHADER_FRAGMENT:
 396                 break;
 397         case MESA_SHADER_COMPUTE: {
 398                 struct radv_shader_info *info = &variant->info.info;
 399                 variant->rsrc2 |=
 400                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 401                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 402                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 403                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 404                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 405                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 406                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 407                 break;
 408         }
 409         default:
 410                 unreachable("unsupported shader type");
 411                 break;
 412         }
 413
 414         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 415             stage == MESA_SHADER_GEOMETRY) {
 416                 struct radv_shader_info *info = &variant->info.info;
 417                 unsigned es_type = variant->info.gs.es_type;
 418                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 419
 420                 if (es_type == MESA_SHADER_VERTEX) {
 421                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 422                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 423                         es_vgpr_comp_cnt = 3;
 424                 } else {
 425                         unreachable("invalid shader ES type");
 426                 }
 427
 428                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 429                  * VGPR[0:4] are always loaded.
 430                  */
 431                 if (info->uses_invocation_id)
 432                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 433                 else if (info->uses_prim_id)
 434                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 435                 else if (variant->info.gs.vertices_in >= 3)
 436                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 437                 else
 438                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 439
 440                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 441                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 442                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 443         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 444             stage == MESA_SHADER_TESS_CTRL)
 445                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 446         else
 447                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 448
 449         void *ptr = radv_alloc_shader_memory(device, variant);
 450         memcpy(ptr, binary->code, binary->code_size);
 451 }
 452
 453 static struct radv_shader_variant *
 454 shader_variant_create(struct radv_device *device,
 455                       struct radv_shader_module *module,
 456                       struct nir_shader * const *shaders,
 457                       int shader_count,
 458                       gl_shader_stage stage,
 459                       struct radv_nir_compiler_options *options,
 460                       bool gs_copy_shader,
 461                       void **code_out,
 462                       unsigned *code_size_out)
 463 {
 464         enum radeon_family chip_family = device->physical_device->rad_info.family;
 465         enum ac_target_machine_options tm_options = 0;
 466         struct radv_shader_variant *variant;
 467         struct ac_shader_binary binary;
 468         LLVMTargetMachineRef tm;
 469
 470         variant = calloc(1, sizeof(struct radv_shader_variant));
 471         if (!variant)
 472                 return NULL;
 473
 474         options->family = chip_family;
 475         options->chip_class = device->physical_device->rad_info.chip_class;
 476         options->dump_shader = radv_can_dump_shader(device, module);
 477         options->dump_preoptir = options->dump_shader &&
 478                                  device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
 479         options->record_llvm_ir = device->keep_shader_info;
 480         options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
 481
 482         if (options->supports_spill)
 483                 tm_options |= AC_TM_SUPPORTS_SPILL;
 484         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 485                 tm_options |= AC_TM_SISCHED;
 486         tm = ac_create_target_machine(chip_family, tm_options);
 487
 488         if (gs_copy_shader) {
 489                 assert(shader_count == 1);
 490                 radv_compile_gs_copy_shader(tm, *shaders, &binary,
 491                                             &variant->config, &variant->info,
 492                                             options);
 493         } else {
 494                 radv_compile_nir_shader(tm, &binary, &variant->config,
 495                                         &variant->info, shaders, shader_count,
 496                                         options);
 497         }
 498
 499         LLVMDisposeTargetMachine(tm);
 500
 501         radv_fill_shader_variant(device, variant, &binary, stage);
 502
 503         if (code_out) {
 504                 *code_out = binary.code;
 505                 *code_size_out = binary.code_size;
 506         } else
 507                 free(binary.code);
 508         free(binary.config);
 509         free(binary.rodata);
 510         free(binary.global_symbol_offsets);
 511         free(binary.relocs);
 512         variant->ref_count = 1;
 513
 514         if (device->keep_shader_info) {
 515                 variant->disasm_string = binary.disasm_string;
 516                 variant->llvm_ir_string = binary.llvm_ir_string;
 517                 if (!gs_copy_shader && !module->nir) {
 518                         variant->nir = *shaders;
 519                         variant->spirv = (uint32_t *)module->data;
 520                         variant->spirv_size = module->size;
 521                 }
 522         } else {
 523                 free(binary.disasm_string);
 524         }
 525
 526         return variant;
 527 }
 528
 529 struct radv_shader_variant *
 530 radv_shader_variant_create(struct radv_device *device,
 531                            struct radv_shader_module *module,
 532                            struct nir_shader *const *shaders,
 533                            int shader_count,
 534                            struct radv_pipeline_layout *layout,
 535                            const struct radv_shader_variant_key *key,
 536                            void **code_out,
 537                            unsigned *code_size_out)
 538 {
 539         struct radv_nir_compiler_options options = {0};
 540
 541         options.layout = layout;
 542         if (key)
 543                 options.key = *key;
 544
 545         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 546         options.supports_spill = device->llvm_supports_spill;
 547
 548         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 549                                      &options, false, code_out, code_size_out);
 550 }
 551
 552 struct radv_shader_variant *
 553 radv_create_gs_copy_shader(struct radv_device *device,
 554                            struct nir_shader *shader,
 555                            void **code_out,
 556                            unsigned *code_size_out,
 557                            bool multiview)
 558 {
 559         struct radv_nir_compiler_options options = {0};
 560
 561         options.key.has_multiview_view_index = multiview;
 562
 563         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 564                                      &options, true, code_out, code_size_out);
 565 }
 566
 567 void
 568 radv_shader_variant_destroy(struct radv_device *device,
 569                             struct radv_shader_variant *variant)
 570 {
 571         if (!p_atomic_dec_zero(&variant->ref_count))
 572                 return;
 573
 574         mtx_lock(&device->shader_slab_mutex);
 575         list_del(&variant->slab_list);
 576         mtx_unlock(&device->shader_slab_mutex);
 577
 578         ralloc_free(variant->nir);
 579         free(variant->disasm_string);
 580         free(variant->llvm_ir_string);
 581         free(variant);
 582 }
 583
 584 const char *
 585 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 586 {
 587         switch (stage) {
 588         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 589         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 590         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 591         case MESA_SHADER_COMPUTE: return "Compute Shader";
 592         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 593         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 594         default:
 595                 return "Unknown shader";
 596         };
 597 }
 598
 599 static uint32_t
 600 get_total_sgprs(struct radv_device *device)
 601 {
 602         if (device->physical_device->rad_info.chip_class >= VI)
 603                 return 800;
 604         else
 605                 return 512;
 606 }
 607
 608 static void
 609 generate_shader_stats(struct radv_device *device,
 610                       struct radv_shader_variant *variant,
 611                       gl_shader_stage stage,
 612                       struct _mesa_string_buffer *buf)
 613 {
 614         unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 615         struct ac_shader_config *conf;
 616         unsigned max_simd_waves;
 617         unsigned lds_per_wave = 0;
 618
 619         switch (device->physical_device->rad_info.family) {
 620         /* These always have 8 waves: */
 621         case CHIP_POLARIS10:
 622         case CHIP_POLARIS11:
 623         case CHIP_POLARIS12:
 624                 max_simd_waves = 8;
 625                 break;
 626         default:
 627                 max_simd_waves = 10;
 628         }
 629
 630         conf = &variant->config;
 631
 632         if (stage == MESA_SHADER_FRAGMENT) {
 633                 lds_per_wave = conf->lds_size * lds_increment +
 634                                align(variant->info.fs.num_interp * 48,
 635                                      lds_increment);
 636         }
 637
 638         if (conf->num_sgprs)
 639                 max_simd_waves = MIN2(max_simd_waves, get_total_sgprs(device) / conf->num_sgprs);
 640
 641         if (conf->num_vgprs)
 642                 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
 643
 644         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 645          * that PS can use.
 646          */
 647         if (lds_per_wave)
 648                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 649
 650         if (stage == MESA_SHADER_FRAGMENT) {
 651                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 652                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 653                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 654                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 655         }
 656
 657         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 658                                    "SGPRS: %d\n"
 659                                    "VGPRS: %d\n"
 660                                    "Spilled SGPRs: %d\n"
 661                                    "Spilled VGPRs: %d\n"
 662                                    "PrivMem VGPRS: %d\n"
 663                                    "Code Size: %d bytes\n"
 664                                    "LDS: %d blocks\n"
 665                                    "Scratch: %d bytes per wave\n"
 666                                    "Max Waves: %d\n"
 667                                    "********************\n\n\n",
 668                                    conf->num_sgprs, conf->num_vgprs,
 669                                    conf->spilled_sgprs, conf->spilled_vgprs,
 670                                    variant->info.private_mem_vgprs, variant->code_size,
 671                                    conf->lds_size, conf->scratch_bytes_per_wave,
 672                                    max_simd_waves);
 673 }
 674
 675 void
 676 radv_shader_dump_stats(struct radv_device *device,
 677                        struct radv_shader_variant *variant,
 678                        gl_shader_stage stage,
 679                        FILE *file)
 680 {
 681         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 682
 683         generate_shader_stats(device, variant, stage, buf);
 684
 685         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 686         fprintf(file, "%s", buf->buf);
 687
 688         _mesa_string_buffer_destroy(buf);
 689 }
 690
 691 VkResult
 692 radv_GetShaderInfoAMD(VkDevice _device,
 693                       VkPipeline _pipeline,
 694                       VkShaderStageFlagBits shaderStage,
 695                       VkShaderInfoTypeAMD infoType,
 696                       size_t* pInfoSize,
 697                       void* pInfo)
 698 {
 699         RADV_FROM_HANDLE(radv_device, device, _device);
 700         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 701         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 702         struct radv_shader_variant *variant = pipeline->shaders[stage];
 703         struct _mesa_string_buffer *buf;
 704         VkResult result = VK_SUCCESS;
 705
 706         /* Spec doesn't indicate what to do if the stage is invalid, so just
 707          * return no info for this. */
 708         if (!variant)
 709                 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
 710
 711         switch (infoType) {
 712         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 713                 if (!pInfo) {
 714                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 715                 } else {
 716                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 717                         struct ac_shader_config *conf = &variant->config;
 718
 719                         VkShaderStatisticsInfoAMD statistics = {};
 720                         statistics.shaderStageMask = shaderStage;
 721                         statistics.numPhysicalVgprs = 256;
 722                         statistics.numPhysicalSgprs = get_total_sgprs(device);
 723                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 724
 725                         if (stage == MESA_SHADER_COMPUTE) {
 726                                 unsigned *local_size = variant->nir->info.cs.local_size;
 727                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 728
 729                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 730                                                                ceil(workgroup_size / statistics.numPhysicalVgprs);
 731
 732                                 statistics.computeWorkGroupSize[0] = local_size[0];
 733                                 statistics.computeWorkGroupSize[1] = local_size[1];
 734                                 statistics.computeWorkGroupSize[2] = local_size[2];
 735                         } else {
 736                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 737                         }
 738
 739                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 740                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 741                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 742                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 743                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 744
 745                         size_t size = *pInfoSize;
 746                         *pInfoSize = sizeof(statistics);
 747
 748                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 749
 750                         if (size < *pInfoSize)
 751                                 result = VK_INCOMPLETE;
 752                 }
 753
 754                 break;
 755         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 756                 buf = _mesa_string_buffer_create(NULL, 1024);
 757
 758                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 759                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 760                 generate_shader_stats(device, variant, stage, buf);
 761
 762                 /* Need to include the null terminator. */
 763                 size_t length = buf->length + 1;
 764
 765                 if (!pInfo) {
 766                         *pInfoSize = length;
 767                 } else {
 768                         size_t size = *pInfoSize;
 769                         *pInfoSize = length;
 770
 771                         memcpy(pInfo, buf->buf, MIN2(size, length));
 772
 773                         if (size < length)
 774                                 result = VK_INCOMPLETE;
 775                 }
 776
 777                 _mesa_string_buffer_destroy(buf);
 778                 break;
 779         default:
 780                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 781                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 782                 break;
 783         }
 784
 785         return result;
 786 }