src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "radv_shader_helper.h"
  34 #include "nir/nir.h"
  35 #include "nir/nir_builder.h"
  36 #include "spirv/nir_spirv.h"
  37
  38 #include <llvm-c/Core.h>
  39 #include <llvm-c/TargetMachine.h>
  40 #include <llvm-c/Support.h>
  41
  42 #include "sid.h"
  43 #include "gfx9d.h"
  44 #include "ac_binary.h"
  45 #include "ac_llvm_util.h"
  46 #include "ac_nir_to_llvm.h"
  47 #include "vk_format.h"
  48 #include "util/debug.h"
  49 #include "ac_exp_param.h"
  50
  51 #include "util/string_buffer.h"
  52
  53 static const struct nir_shader_compiler_options nir_options = {
  54         .vertex_id_zero_based = true,
  55         .lower_scmp = true,
  56         .lower_flrp16 = true,
  57         .lower_flrp32 = true,
  58         .lower_flrp64 = true,
  59         .lower_device_index_to_zero = true,
  60         .lower_fsat = true,
  61         .lower_fdiv = true,
  62         .lower_sub = true,
  63         .lower_pack_snorm_2x16 = true,
  64         .lower_pack_snorm_4x8 = true,
  65         .lower_pack_unorm_2x16 = true,
  66         .lower_pack_unorm_4x8 = true,
  67         .lower_unpack_snorm_2x16 = true,
  68         .lower_unpack_snorm_4x8 = true,
  69         .lower_unpack_unorm_2x16 = true,
  70         .lower_unpack_unorm_4x8 = true,
  71         .lower_extract_byte = true,
  72         .lower_extract_word = true,
  73         .lower_ffma = true,
  74         .lower_fpow = true,
  75         .lower_mul_2x32_64 = true,
  76         .max_unroll_iterations = 32
  77 };
  78
  79 VkResult radv_CreateShaderModule(
  80         VkDevice                                    _device,
  81         const VkShaderModuleCreateInfo*             pCreateInfo,
  82         const VkAllocationCallbacks*                pAllocator,
  83         VkShaderModule*                             pShaderModule)
  84 {
  85         RADV_FROM_HANDLE(radv_device, device, _device);
  86         struct radv_shader_module *module;
  87
  88         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  89         assert(pCreateInfo->flags == 0);
  90
  91         module = vk_alloc2(&device->alloc, pAllocator,
  92                              sizeof(*module) + pCreateInfo->codeSize, 8,
  93                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  94         if (module == NULL)
  95                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
  96
  97         module->nir = NULL;
  98         module->size = pCreateInfo->codeSize;
  99         memcpy(module->data, pCreateInfo->pCode, module->size);
 100
 101         _mesa_sha1_compute(module->data, module->size, module->sha1);
 102
 103         *pShaderModule = radv_shader_module_to_handle(module);
 104
 105         return VK_SUCCESS;
 106 }
 107
 108 void radv_DestroyShaderModule(
 109         VkDevice                                    _device,
 110         VkShaderModule                              _module,
 111         const VkAllocationCallbacks*                pAllocator)
 112 {
 113         RADV_FROM_HANDLE(radv_device, device, _device);
 114         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 115
 116         if (!module)
 117                 return;
 118
 119         vk_free2(&device->alloc, pAllocator, module);
 120 }
 121
 122 void
 123 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 124                   bool allow_copies)
 125 {
 126         bool progress;
 127         unsigned lower_flrp =
 128                 (shader->options->lower_flrp16 ? 16 : 0) |
 129                 (shader->options->lower_flrp32 ? 32 : 0) |
 130                 (shader->options->lower_flrp64 ? 64 : 0);
 131
 132         do {
 133                 progress = false;
 134
 135                 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
 136                 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
 137
 138                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 139                 NIR_PASS_V(shader, nir_lower_pack);
 140
 141                 if (allow_copies) {
 142                         /* Only run this pass in the first call to
 143                          * radv_optimize_nir.  Later calls assume that we've
 144                          * lowered away any copy_deref instructions and we
 145                          *  don't want to introduce any more.
 146                         */
 147                         NIR_PASS(progress, shader, nir_opt_find_array_copies);
 148                 }
 149
 150                 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
 151                 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
 152
 153                 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL);
 154                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 155
 156                 NIR_PASS(progress, shader, nir_copy_prop);
 157                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 158                 NIR_PASS(progress, shader, nir_opt_dce);
 159                 if (nir_opt_trivial_continues(shader)) {
 160                         progress = true;
 161                         NIR_PASS(progress, shader, nir_copy_prop);
 162                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 163                         NIR_PASS(progress, shader, nir_opt_dce);
 164                 }
 165                 NIR_PASS(progress, shader, nir_opt_if, true);
 166                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 167                 NIR_PASS(progress, shader, nir_opt_cse);
 168                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
 169                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 170                 NIR_PASS(progress, shader, nir_opt_algebraic);
 171
 172                 if (lower_flrp != 0) {
 173                         bool lower_flrp_progress = false;
 174                         NIR_PASS(lower_flrp_progress,
 175                                  shader,
 176                                  nir_lower_flrp,
 177                                  lower_flrp,
 178                                  false /* always_precise */,
 179                                  shader->options->lower_ffma);
 180                         if (lower_flrp_progress) {
 181                                 NIR_PASS(progress, shader,
 182                                          nir_opt_constant_folding);
 183                                 progress = true;
 184                         }
 185
 186                         /* Nothing should rematerialize any flrps, so we only
 187                          * need to do this lowering once.
 188                          */
 189                         lower_flrp = 0;
 190                 }
 191
 192                 NIR_PASS(progress, shader, nir_opt_undef);
 193                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 194                 if (shader->options->max_unroll_iterations) {
 195                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 196                 }
 197         } while (progress && !optimize_conservatively);
 198
 199         NIR_PASS(progress, shader, nir_opt_shrink_load);
 200         NIR_PASS(progress, shader, nir_opt_move_load_ubo);
 201 }
 202
 203 nir_shader *
 204 radv_shader_compile_to_nir(struct radv_device *device,
 205                            struct radv_shader_module *module,
 206                            const char *entrypoint_name,
 207                            gl_shader_stage stage,
 208                            const VkSpecializationInfo *spec_info,
 209                            const VkPipelineCreateFlags flags,
 210                            const struct radv_pipeline_layout *layout)
 211 {
 212         nir_shader *nir;
 213         nir_function *entry_point;
 214         if (module->nir) {
 215                 /* Some things such as our meta clear/blit code will give us a NIR
 216                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 217                  * and just use the NIR shader */
 218                 nir = module->nir;
 219                 nir->options = &nir_options;
 220                 nir_validate_shader(nir, "in internal shader");
 221
 222                 assert(exec_list_length(&nir->functions) == 1);
 223                 struct exec_node *node = exec_list_get_head(&nir->functions);
 224                 entry_point = exec_node_data(nir_function, node, node);
 225         } else {
 226                 uint32_t *spirv = (uint32_t *) module->data;
 227                 assert(module->size % 4 == 0);
 228
 229                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 230                         radv_print_spirv(spirv, module->size, stderr);
 231
 232                 uint32_t num_spec_entries = 0;
 233                 struct nir_spirv_specialization *spec_entries = NULL;
 234                 if (spec_info && spec_info->mapEntryCount > 0) {
 235                         num_spec_entries = spec_info->mapEntryCount;
 236                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 237                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 238                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 239                                 const void *data = spec_info->pData + entry.offset;
 240                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 241
 242                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 243                                 if (spec_info->dataSize == 8)
 244                                         spec_entries[i].data64 = *(const uint64_t *)data;
 245                                 else
 246                                         spec_entries[i].data32 = *(const uint32_t *)data;
 247                         }
 248                 }
 249                 const struct spirv_to_nir_options spirv_options = {
 250                         .lower_ubo_ssbo_access_to_offsets = true,
 251                         .caps = {
 252                                 .derivative_group = true,
 253                                 .descriptor_array_dynamic_indexing = true,
 254                                 .descriptor_array_non_uniform_indexing = true,
 255                                 .descriptor_indexing = true,
 256                                 .device_group = true,
 257                                 .draw_parameters = true,
 258                                 .float16 = true,
 259                                 .float64 = true,
 260                                 .gcn_shader = true,
 261                                 .geometry_streams = true,
 262                                 .image_read_without_format = true,
 263                                 .image_write_without_format = true,
 264                                 .int8 = true,
 265                                 .int16 = true,
 266                                 .int64 = true,
 267                                 .int64_atomics = true,
 268                                 .multiview = true,
 269                                 .physical_storage_buffer_address = true,
 270                                 .runtime_descriptor_array = true,
 271                                 .shader_viewport_index_layer = true,
 272                                 .stencil_export = true,
 273                                 .storage_8bit = true,
 274                                 .storage_16bit = true,
 275                                 .storage_image_ms = true,
 276                                 .subgroup_arithmetic = true,
 277                                 .subgroup_ballot = true,
 278                                 .subgroup_basic = true,
 279                                 .subgroup_quad = true,
 280                                 .subgroup_shuffle = true,
 281                                 .subgroup_vote = true,
 282                                 .tessellation = true,
 283                                 .transform_feedback = true,
 284                                 .trinary_minmax = true,
 285                                 .variable_pointers = true,
 286                         },
 287                         .ubo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT, 2),
 288                         .ssbo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT, 2),
 289                         .phys_ssbo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT64, 1),
 290                         .push_const_ptr_type = glsl_uint_type(),
 291                         .shared_ptr_type = glsl_uint_type(),
 292                 };
 293                 entry_point = spirv_to_nir(spirv, module->size / 4,
 294                                            spec_entries, num_spec_entries,
 295                                            stage, entrypoint_name,
 296                                            &spirv_options, &nir_options);
 297                 nir = entry_point->shader;
 298                 assert(nir->info.stage == stage);
 299                 nir_validate_shader(nir, "after spirv_to_nir");
 300
 301                 free(spec_entries);
 302
 303                 /* We have to lower away local constant initializers right before we
 304                  * inline functions.  That way they get properly initialized at the top
 305                  * of the function and not at the top of its caller.
 306                  */
 307                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
 308                 NIR_PASS_V(nir, nir_lower_returns);
 309                 NIR_PASS_V(nir, nir_inline_functions);
 310                 NIR_PASS_V(nir, nir_opt_deref);
 311
 312                 /* Pick off the single entrypoint that we want */
 313                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 314                         if (func != entry_point)
 315                                 exec_node_remove(&func->node);
 316                 }
 317                 assert(exec_list_length(&nir->functions) == 1);
 318                 entry_point->name = ralloc_strdup(entry_point, "main");
 319
 320                 /* Make sure we lower constant initializers on output variables so that
 321                  * nir_remove_dead_variables below sees the corresponding stores
 322                  */
 323                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
 324
 325                 /* Now that we've deleted all but the main function, we can go ahead and
 326                  * lower the rest of the constant initializers.
 327                  */
 328                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 329
 330                 /* Split member structs.  We do this before lower_io_to_temporaries so that
 331                  * it doesn't lower system values to temporaries by accident.
 332                  */
 333                 NIR_PASS_V(nir, nir_split_var_copies);
 334                 NIR_PASS_V(nir, nir_split_per_member_structs);
 335
 336                 NIR_PASS_V(nir, nir_remove_dead_variables,
 337                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 338
 339                 NIR_PASS_V(nir, nir_lower_system_values);
 340                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 341                 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
 342         }
 343
 344         /* Vulkan uses the separate-shader linking model */
 345         nir->info.separate_shader = true;
 346
 347         nir_shader_gather_info(nir, entry_point->impl);
 348
 349         static const nir_lower_tex_options tex_options = {
 350           .lower_txp = ~0,
 351           .lower_tg4_offsets = true,
 352         };
 353
 354         nir_lower_tex(nir, &tex_options);
 355
 356         nir_lower_vars_to_ssa(nir);
 357
 358         if (nir->info.stage == MESA_SHADER_VERTEX ||
 359             nir->info.stage == MESA_SHADER_GEOMETRY) {
 360                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 361                            nir_shader_get_entrypoint(nir), true, true);
 362         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
 363                    nir->info.stage == MESA_SHADER_FRAGMENT) {
 364                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 365                            nir_shader_get_entrypoint(nir), true, false);
 366         }
 367
 368         nir_split_var_copies(nir);
 369
 370         nir_lower_global_vars_to_local(nir);
 371         nir_remove_dead_variables(nir, nir_var_function_temp);
 372         nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 373                         .subgroup_size = 64,
 374                         .ballot_bit_size = 64,
 375                         .lower_to_scalar = 1,
 376                         .lower_subgroup_masks = 1,
 377                         .lower_shuffle = 1,
 378                         .lower_shuffle_to_32bit = 1,
 379                         .lower_vote_eq_to_ballot = 1,
 380                 });
 381
 382         nir_lower_load_const_to_scalar(nir);
 383
 384         if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
 385                 radv_optimize_nir(nir, false, true);
 386
 387         /* We call nir_lower_var_copies() after the first radv_optimize_nir()
 388          * to remove any copies introduced by nir_opt_find_array_copies().
 389          */
 390         nir_lower_var_copies(nir);
 391
 392         /* Indirect lowering must be called after the radv_optimize_nir() loop
 393          * has been called at least once. Otherwise indirect lowering can
 394          * bloat the instruction count of the loop and cause it to be
 395          * considered too large for unrolling.
 396          */
 397         ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
 398         radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
 399
 400         return nir;
 401 }
 402
 403 void *
 404 radv_alloc_shader_memory(struct radv_device *device,
 405                          struct radv_shader_variant *shader)
 406 {
 407         mtx_lock(&device->shader_slab_mutex);
 408         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 409                 uint64_t offset = 0;
 410                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 411                         if (s->bo_offset - offset >= shader->code_size) {
 412                                 shader->bo = slab->bo;
 413                                 shader->bo_offset = offset;
 414                                 list_addtail(&shader->slab_list, &s->slab_list);
 415                                 mtx_unlock(&device->shader_slab_mutex);
 416                                 return slab->ptr + offset;
 417                         }
 418                         offset = align_u64(s->bo_offset + s->code_size, 256);
 419                 }
 420                 if (slab->size - offset >= shader->code_size) {
 421                         shader->bo = slab->bo;
 422                         shader->bo_offset = offset;
 423                         list_addtail(&shader->slab_list, &slab->shaders);
 424                         mtx_unlock(&device->shader_slab_mutex);
 425                         return slab->ptr + offset;
 426                 }
 427         }
 428
 429         mtx_unlock(&device->shader_slab_mutex);
 430         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 431
 432         slab->size = 256 * 1024;
 433         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 434                                              RADEON_DOMAIN_VRAM,
 435                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 436                                              (device->physical_device->cpdma_prefetch_writes_memory ?
 437                                                      0 : RADEON_FLAG_READ_ONLY),
 438                                              RADV_BO_PRIORITY_SHADER);
 439         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 440         list_inithead(&slab->shaders);
 441
 442         mtx_lock(&device->shader_slab_mutex);
 443         list_add(&slab->slabs, &device->shader_slabs);
 444
 445         shader->bo = slab->bo;
 446         shader->bo_offset = 0;
 447         list_add(&shader->slab_list, &slab->shaders);
 448         mtx_unlock(&device->shader_slab_mutex);
 449         return slab->ptr;
 450 }
 451
 452 void
 453 radv_destroy_shader_slabs(struct radv_device *device)
 454 {
 455         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 456                 device->ws->buffer_destroy(slab->bo);
 457                 free(slab);
 458         }
 459         mtx_destroy(&device->shader_slab_mutex);
 460 }
 461
 462 /* For the UMR disassembler. */
 463 #define DEBUGGER_END_OF_CODE_MARKER    0xbf9f0000 /* invalid instruction */
 464 #define DEBUGGER_NUM_MARKERS           5
 465
 466 static unsigned
 467 radv_get_shader_binary_size(struct ac_shader_binary *binary)
 468 {
 469         return binary->code_size + DEBUGGER_NUM_MARKERS * 4;
 470 }
 471
 472 static void
 473 radv_fill_shader_variant(struct radv_device *device,
 474                          struct radv_shader_variant *variant,
 475                          struct ac_shader_binary *binary,
 476                          gl_shader_stage stage)
 477 {
 478         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 479         struct radv_shader_info *info = &variant->info.info;
 480         unsigned vgpr_comp_cnt = 0;
 481
 482         variant->code_size = radv_get_shader_binary_size(binary);
 483         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 484                          S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
 485                          S_00B12C_SCRATCH_EN(scratch_enabled) |
 486                          S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
 487                          S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
 488                          S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
 489                          S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
 490                          S_00B12C_SO_EN(!!info->so.num_outputs);
 491
 492         variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 493                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 494                 S_00B848_DX10_CLAMP(1) |
 495                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 496
 497         switch (stage) {
 498         case MESA_SHADER_TESS_EVAL:
 499                 vgpr_comp_cnt = 3;
 500                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 501                 break;
 502         case MESA_SHADER_TESS_CTRL:
 503                 if (device->physical_device->rad_info.chip_class >= GFX9) {
 504                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 505                 } else {
 506                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 507                 }
 508                 break;
 509         case MESA_SHADER_VERTEX:
 510         case MESA_SHADER_GEOMETRY:
 511                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 512                 break;
 513         case MESA_SHADER_FRAGMENT:
 514                 break;
 515         case MESA_SHADER_COMPUTE:
 516                 variant->rsrc2 |=
 517                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 518                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 519                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 520                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 521                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 522                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 523                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 524                 break;
 525         default:
 526                 unreachable("unsupported shader type");
 527                 break;
 528         }
 529
 530         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 531             stage == MESA_SHADER_GEOMETRY) {
 532                 unsigned es_type = variant->info.gs.es_type;
 533                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 534
 535                 if (es_type == MESA_SHADER_VERTEX) {
 536                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 537                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 538                         es_vgpr_comp_cnt = 3;
 539                 } else {
 540                         unreachable("invalid shader ES type");
 541                 }
 542
 543                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 544                  * VGPR[0:4] are always loaded.
 545                  */
 546                 if (info->uses_invocation_id) {
 547                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 548                 } else if (info->uses_prim_id) {
 549                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 550                 } else if (variant->info.gs.vertices_in >= 3) {
 551                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 552                 } else {
 553                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 554                 }
 555
 556                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 557                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 558                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 559         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 560                    stage == MESA_SHADER_TESS_CTRL) {
 561                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 562         } else {
 563                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 564         }
 565
 566         void *ptr = radv_alloc_shader_memory(device, variant);
 567         memcpy(ptr, binary->code, binary->code_size);
 568
 569         /* Add end-of-code markers for the UMR disassembler. */
 570        uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4;
 571        for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
 572                 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
 573
 574 }
 575
 576 static void radv_init_llvm_target()
 577 {
 578         LLVMInitializeAMDGPUTargetInfo();
 579         LLVMInitializeAMDGPUTarget();
 580         LLVMInitializeAMDGPUTargetMC();
 581         LLVMInitializeAMDGPUAsmPrinter();
 582
 583         /* For inline assembly. */
 584         LLVMInitializeAMDGPUAsmParser();
 585
 586         /* Workaround for bug in llvm 4.0 that causes image intrinsics
 587          * to disappear.
 588          * https://reviews.llvm.org/D26348
 589          *
 590          * Workaround for bug in llvm that causes the GPU to hang in presence
 591          * of nested loops because there is an exec mask issue. The proper
 592          * solution is to fix LLVM but this might require a bunch of work.
 593          * https://bugs.llvm.org/show_bug.cgi?id=37744
 594          *
 595          * "mesa" is the prefix for error messages.
 596          */
 597         if (HAVE_LLVM >= 0x0800) {
 598                 const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
 599                 LLVMParseCommandLineOptions(2, argv, NULL);
 600
 601         } else {
 602                 const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
 603                                         "-amdgpu-skip-threshold=1" };
 604                 LLVMParseCommandLineOptions(3, argv, NULL);
 605         }
 606 }
 607
 608 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
 609
 610 static void radv_init_llvm_once(void)
 611 {
 612         call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
 613 }
 614
 615 static struct radv_shader_variant *
 616 shader_variant_create(struct radv_device *device,
 617                       struct radv_shader_module *module,
 618                       struct nir_shader * const *shaders,
 619                       int shader_count,
 620                       gl_shader_stage stage,
 621                       struct radv_nir_compiler_options *options,
 622                       bool gs_copy_shader,
 623                       void **code_out,
 624                       unsigned *code_size_out)
 625 {
 626         enum radeon_family chip_family = device->physical_device->rad_info.family;
 627         enum ac_target_machine_options tm_options = 0;
 628         struct radv_shader_variant *variant;
 629         struct ac_shader_binary binary;
 630         struct ac_llvm_compiler ac_llvm;
 631         bool thread_compiler;
 632         variant = calloc(1, sizeof(struct radv_shader_variant));
 633         if (!variant)
 634                 return NULL;
 635
 636         options->family = chip_family;
 637         options->chip_class = device->physical_device->rad_info.chip_class;
 638         options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
 639         options->dump_preoptir = options->dump_shader &&
 640                                  device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
 641         options->record_llvm_ir = device->keep_shader_info;
 642         options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
 643         options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
 644         options->address32_hi = device->physical_device->rad_info.address32_hi;
 645
 646         if (options->supports_spill)
 647                 tm_options |= AC_TM_SUPPORTS_SPILL;
 648         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 649                 tm_options |= AC_TM_SISCHED;
 650         if (options->check_ir)
 651                 tm_options |= AC_TM_CHECK_IR;
 652
 653         thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
 654         radv_init_llvm_once();
 655         radv_init_llvm_compiler(&ac_llvm,
 656                                 thread_compiler,
 657                                 chip_family, tm_options);
 658         if (gs_copy_shader) {
 659                 assert(shader_count == 1);
 660                 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
 661                                             &variant->config, &variant->info,
 662                                             options);
 663         } else {
 664                 radv_compile_nir_shader(&ac_llvm, &binary, &variant->config,
 665                                         &variant->info, shaders, shader_count,
 666                                         options);
 667         }
 668
 669         radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
 670
 671         radv_fill_shader_variant(device, variant, &binary, stage);
 672
 673         if (code_out) {
 674                 *code_out = binary.code;
 675                 *code_size_out = binary.code_size;
 676         } else
 677                 free(binary.code);
 678         free(binary.config);
 679         free(binary.rodata);
 680         free(binary.global_symbol_offsets);
 681         free(binary.relocs);
 682         variant->ref_count = 1;
 683
 684         if (device->keep_shader_info) {
 685                 variant->disasm_string = binary.disasm_string;
 686                 variant->llvm_ir_string = binary.llvm_ir_string;
 687                 if (!gs_copy_shader && !module->nir) {
 688                         variant->nir = *shaders;
 689                         variant->spirv = (uint32_t *)module->data;
 690                         variant->spirv_size = module->size;
 691                 }
 692         } else {
 693                 free(binary.disasm_string);
 694         }
 695
 696         return variant;
 697 }
 698
 699 struct radv_shader_variant *
 700 radv_shader_variant_create(struct radv_device *device,
 701                            struct radv_shader_module *module,
 702                            struct nir_shader *const *shaders,
 703                            int shader_count,
 704                            struct radv_pipeline_layout *layout,
 705                            const struct radv_shader_variant_key *key,
 706                            void **code_out,
 707                            unsigned *code_size_out)
 708 {
 709         struct radv_nir_compiler_options options = {0};
 710
 711         options.layout = layout;
 712         if (key)
 713                 options.key = *key;
 714
 715         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 716         options.supports_spill = true;
 717
 718         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 719                                      &options, false, code_out, code_size_out);
 720 }
 721
 722 struct radv_shader_variant *
 723 radv_create_gs_copy_shader(struct radv_device *device,
 724                            struct nir_shader *shader,
 725                            void **code_out,
 726                            unsigned *code_size_out,
 727                            bool multiview)
 728 {
 729         struct radv_nir_compiler_options options = {0};
 730
 731         options.key.has_multiview_view_index = multiview;
 732
 733         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 734                                      &options, true, code_out, code_size_out);
 735 }
 736
 737 void
 738 radv_shader_variant_destroy(struct radv_device *device,
 739                             struct radv_shader_variant *variant)
 740 {
 741         if (!p_atomic_dec_zero(&variant->ref_count))
 742                 return;
 743
 744         mtx_lock(&device->shader_slab_mutex);
 745         list_del(&variant->slab_list);
 746         mtx_unlock(&device->shader_slab_mutex);
 747
 748         ralloc_free(variant->nir);
 749         free(variant->disasm_string);
 750         free(variant->llvm_ir_string);
 751         free(variant);
 752 }
 753
 754 const char *
 755 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 756 {
 757         switch (stage) {
 758         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 759         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 760         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 761         case MESA_SHADER_COMPUTE: return "Compute Shader";
 762         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 763         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 764         default:
 765                 return "Unknown shader";
 766         };
 767 }
 768
 769 static void
 770 generate_shader_stats(struct radv_device *device,
 771                       struct radv_shader_variant *variant,
 772                       gl_shader_stage stage,
 773                       struct _mesa_string_buffer *buf)
 774 {
 775         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 776         unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
 777         struct ac_shader_config *conf;
 778         unsigned max_simd_waves;
 779         unsigned lds_per_wave = 0;
 780
 781         max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
 782
 783         conf = &variant->config;
 784
 785         if (stage == MESA_SHADER_FRAGMENT) {
 786                 lds_per_wave = conf->lds_size * lds_increment +
 787                                align(variant->info.fs.num_interp * 48,
 788                                      lds_increment);
 789         } else if (stage == MESA_SHADER_COMPUTE) {
 790                 unsigned max_workgroup_size =
 791                                 radv_nir_get_max_workgroup_size(chip_class, variant->nir);
 792                 lds_per_wave = (conf->lds_size * lds_increment) /
 793                                DIV_ROUND_UP(max_workgroup_size, 64);
 794         }
 795
 796         if (conf->num_sgprs)
 797                 max_simd_waves =
 798                         MIN2(max_simd_waves,
 799                              ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs);
 800
 801         if (conf->num_vgprs)
 802                 max_simd_waves =
 803                         MIN2(max_simd_waves,
 804                              RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
 805
 806         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 807          * that PS can use.
 808          */
 809         if (lds_per_wave)
 810                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 811
 812         if (stage == MESA_SHADER_FRAGMENT) {
 813                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 814                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 815                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 816                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 817         }
 818
 819         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 820                                    "SGPRS: %d\n"
 821                                    "VGPRS: %d\n"
 822                                    "Spilled SGPRs: %d\n"
 823                                    "Spilled VGPRs: %d\n"
 824                                    "PrivMem VGPRS: %d\n"
 825                                    "Code Size: %d bytes\n"
 826                                    "LDS: %d blocks\n"
 827                                    "Scratch: %d bytes per wave\n"
 828                                    "Max Waves: %d\n"
 829                                    "********************\n\n\n",
 830                                    conf->num_sgprs, conf->num_vgprs,
 831                                    conf->spilled_sgprs, conf->spilled_vgprs,
 832                                    variant->info.private_mem_vgprs, variant->code_size,
 833                                    conf->lds_size, conf->scratch_bytes_per_wave,
 834                                    max_simd_waves);
 835 }
 836
 837 void
 838 radv_shader_dump_stats(struct radv_device *device,
 839                        struct radv_shader_variant *variant,
 840                        gl_shader_stage stage,
 841                        FILE *file)
 842 {
 843         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 844
 845         generate_shader_stats(device, variant, stage, buf);
 846
 847         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 848         fprintf(file, "%s", buf->buf);
 849
 850         _mesa_string_buffer_destroy(buf);
 851 }
 852
 853 VkResult
 854 radv_GetShaderInfoAMD(VkDevice _device,
 855                       VkPipeline _pipeline,
 856                       VkShaderStageFlagBits shaderStage,
 857                       VkShaderInfoTypeAMD infoType,
 858                       size_t* pInfoSize,
 859                       void* pInfo)
 860 {
 861         RADV_FROM_HANDLE(radv_device, device, _device);
 862         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 863         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 864         struct radv_shader_variant *variant = pipeline->shaders[stage];
 865         struct _mesa_string_buffer *buf;
 866         VkResult result = VK_SUCCESS;
 867
 868         /* Spec doesn't indicate what to do if the stage is invalid, so just
 869          * return no info for this. */
 870         if (!variant)
 871                 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
 872
 873         switch (infoType) {
 874         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 875                 if (!pInfo) {
 876                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 877                 } else {
 878                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
 879                         struct ac_shader_config *conf = &variant->config;
 880
 881                         VkShaderStatisticsInfoAMD statistics = {};
 882                         statistics.shaderStageMask = shaderStage;
 883                         statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
 884                         statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class);
 885                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 886
 887                         if (stage == MESA_SHADER_COMPUTE) {
 888                                 unsigned *local_size = variant->nir->info.cs.local_size;
 889                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 890
 891                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 892                                                                ceil((double)workgroup_size / statistics.numPhysicalVgprs);
 893
 894                                 statistics.computeWorkGroupSize[0] = local_size[0];
 895                                 statistics.computeWorkGroupSize[1] = local_size[1];
 896                                 statistics.computeWorkGroupSize[2] = local_size[2];
 897                         } else {
 898                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 899                         }
 900
 901                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 902                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 903                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 904                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 905                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 906
 907                         size_t size = *pInfoSize;
 908                         *pInfoSize = sizeof(statistics);
 909
 910                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 911
 912                         if (size < *pInfoSize)
 913                                 result = VK_INCOMPLETE;
 914                 }
 915
 916                 break;
 917         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 918                 buf = _mesa_string_buffer_create(NULL, 1024);
 919
 920                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 921                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
 922                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 923                 generate_shader_stats(device, variant, stage, buf);
 924
 925                 /* Need to include the null terminator. */
 926                 size_t length = buf->length + 1;
 927
 928                 if (!pInfo) {
 929                         *pInfoSize = length;
 930                 } else {
 931                         size_t size = *pInfoSize;
 932                         *pInfoSize = length;
 933
 934                         memcpy(pInfo, buf->buf, MIN2(size, length));
 935
 936                         if (size < length)
 937                                 result = VK_INCOMPLETE;
 938                 }
 939
 940                 _mesa_string_buffer_destroy(buf);
 941                 break;
 942         default:
 943                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 944                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 945                 break;
 946         }
 947
 948         return result;
 949 }