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radv/llvm: expose VK_EXT_shader_demote_to_helper_invocation with LLVM 9+
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .max_unroll_iterations = 32,
80 .use_interpolated_input_intrinsics = true,
81 /* nir_lower_int64() isn't actually called for the LLVM backend, but
82 * this helps the loop unrolling heuristics. */
83 .lower_int64_options = nir_lower_imul64 |
84 nir_lower_imul_high64 |
85 nir_lower_imul_2x32_64 |
86 nir_lower_divmod64 |
87 nir_lower_minmax64 |
88 nir_lower_iabs64,
89 };
90
91 static const struct nir_shader_compiler_options nir_options_aco = {
92 .vertex_id_zero_based = true,
93 .lower_scmp = true,
94 .lower_flrp16 = true,
95 .lower_flrp32 = true,
96 .lower_flrp64 = true,
97 .lower_device_index_to_zero = true,
98 .lower_fdiv = true,
99 .lower_fmod = true,
100 .lower_bitfield_insert_to_bitfield_select = true,
101 .lower_bitfield_extract = true,
102 .lower_pack_snorm_2x16 = true,
103 .lower_pack_snorm_4x8 = true,
104 .lower_pack_unorm_2x16 = true,
105 .lower_pack_unorm_4x8 = true,
106 .lower_unpack_snorm_2x16 = true,
107 .lower_unpack_snorm_4x8 = true,
108 .lower_unpack_unorm_2x16 = true,
109 .lower_unpack_unorm_4x8 = true,
110 .lower_unpack_half_2x16 = true,
111 .lower_extract_byte = true,
112 .lower_extract_word = true,
113 .lower_ffma = true,
114 .lower_fpow = true,
115 .lower_mul_2x32_64 = true,
116 .lower_rotate = true,
117 .max_unroll_iterations = 32,
118 .use_interpolated_input_intrinsics = true,
119 .lower_int64_options = nir_lower_imul64 |
120 nir_lower_imul_high64 |
121 nir_lower_imul_2x32_64 |
122 nir_lower_divmod64 |
123 nir_lower_logic64 |
124 nir_lower_minmax64 |
125 nir_lower_iabs64,
126 };
127
128 bool
129 radv_can_dump_shader(struct radv_device *device,
130 struct radv_shader_module *module,
131 bool is_gs_copy_shader)
132 {
133 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
134 return false;
135 if (module)
136 return !module->nir ||
137 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
138
139 return is_gs_copy_shader;
140 }
141
142 bool
143 radv_can_dump_shader_stats(struct radv_device *device,
144 struct radv_shader_module *module)
145 {
146 /* Only dump non-meta shader stats. */
147 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
148 module && !module->nir;
149 }
150
151 VkResult radv_CreateShaderModule(
152 VkDevice _device,
153 const VkShaderModuleCreateInfo* pCreateInfo,
154 const VkAllocationCallbacks* pAllocator,
155 VkShaderModule* pShaderModule)
156 {
157 RADV_FROM_HANDLE(radv_device, device, _device);
158 struct radv_shader_module *module;
159
160 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
161 assert(pCreateInfo->flags == 0);
162
163 module = vk_alloc2(&device->vk.alloc, pAllocator,
164 sizeof(*module) + pCreateInfo->codeSize, 8,
165 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
166 if (module == NULL)
167 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
168
169 vk_object_base_init(&device->vk, &module->base,
170 VK_OBJECT_TYPE_SHADER_MODULE);
171
172 module->nir = NULL;
173 module->size = pCreateInfo->codeSize;
174 memcpy(module->data, pCreateInfo->pCode, module->size);
175
176 _mesa_sha1_compute(module->data, module->size, module->sha1);
177
178 *pShaderModule = radv_shader_module_to_handle(module);
179
180 return VK_SUCCESS;
181 }
182
183 void radv_DestroyShaderModule(
184 VkDevice _device,
185 VkShaderModule _module,
186 const VkAllocationCallbacks* pAllocator)
187 {
188 RADV_FROM_HANDLE(radv_device, device, _device);
189 RADV_FROM_HANDLE(radv_shader_module, module, _module);
190
191 if (!module)
192 return;
193
194 vk_object_base_finish(&module->base);
195 vk_free2(&device->vk.alloc, pAllocator, module);
196 }
197
198 void
199 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
200 bool allow_copies)
201 {
202 bool progress;
203 unsigned lower_flrp =
204 (shader->options->lower_flrp16 ? 16 : 0) |
205 (shader->options->lower_flrp32 ? 32 : 0) |
206 (shader->options->lower_flrp64 ? 64 : 0);
207
208 do {
209 progress = false;
210
211 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
212 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
213
214 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
215 NIR_PASS_V(shader, nir_lower_pack);
216
217 if (allow_copies) {
218 /* Only run this pass in the first call to
219 * radv_optimize_nir. Later calls assume that we've
220 * lowered away any copy_deref instructions and we
221 * don't want to introduce any more.
222 */
223 NIR_PASS(progress, shader, nir_opt_find_array_copies);
224 }
225
226 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
227 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
228 NIR_PASS(progress, shader, nir_remove_dead_variables,
229 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
230 NULL);
231
232 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
233 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
234
235 NIR_PASS(progress, shader, nir_copy_prop);
236 NIR_PASS(progress, shader, nir_opt_remove_phis);
237 NIR_PASS(progress, shader, nir_opt_dce);
238 if (nir_opt_trivial_continues(shader)) {
239 progress = true;
240 NIR_PASS(progress, shader, nir_copy_prop);
241 NIR_PASS(progress, shader, nir_opt_remove_phis);
242 NIR_PASS(progress, shader, nir_opt_dce);
243 }
244 NIR_PASS(progress, shader, nir_opt_if, true);
245 NIR_PASS(progress, shader, nir_opt_dead_cf);
246 NIR_PASS(progress, shader, nir_opt_cse);
247 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
248 NIR_PASS(progress, shader, nir_opt_constant_folding);
249 NIR_PASS(progress, shader, nir_opt_algebraic);
250
251 if (lower_flrp != 0) {
252 bool lower_flrp_progress = false;
253 NIR_PASS(lower_flrp_progress,
254 shader,
255 nir_lower_flrp,
256 lower_flrp,
257 false /* always_precise */,
258 shader->options->lower_ffma);
259 if (lower_flrp_progress) {
260 NIR_PASS(progress, shader,
261 nir_opt_constant_folding);
262 progress = true;
263 }
264
265 /* Nothing should rematerialize any flrps, so we only
266 * need to do this lowering once.
267 */
268 lower_flrp = 0;
269 }
270
271 NIR_PASS(progress, shader, nir_opt_undef);
272 if (shader->options->max_unroll_iterations) {
273 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
274 }
275 } while (progress && !optimize_conservatively);
276
277 NIR_PASS(progress, shader, nir_opt_conditional_discard);
278 NIR_PASS(progress, shader, nir_opt_shrink_load);
279 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
280 }
281
282 static void
283 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
284 {
285 assert(glsl_type_is_vector_or_scalar(type));
286
287 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
288 unsigned length = glsl_get_vector_elements(type);
289 *size = comp_size * length,
290 *align = comp_size;
291 }
292
293 nir_shader *
294 radv_shader_compile_to_nir(struct radv_device *device,
295 struct radv_shader_module *module,
296 const char *entrypoint_name,
297 gl_shader_stage stage,
298 const VkSpecializationInfo *spec_info,
299 const VkPipelineCreateFlags flags,
300 const struct radv_pipeline_layout *layout,
301 unsigned subgroup_size, unsigned ballot_bit_size)
302 {
303 nir_shader *nir;
304 const nir_shader_compiler_options *nir_options =
305 device->physical_device->use_aco ? &nir_options_aco :
306 &nir_options_llvm;
307
308 if (module->nir) {
309 /* Some things such as our meta clear/blit code will give us a NIR
310 * shader directly. In that case, we just ignore the SPIR-V entirely
311 * and just use the NIR shader */
312 nir = module->nir;
313 nir->options = nir_options;
314 nir_validate_shader(nir, "in internal shader");
315
316 assert(exec_list_length(&nir->functions) == 1);
317 } else {
318 uint32_t *spirv = (uint32_t *) module->data;
319 assert(module->size % 4 == 0);
320
321 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
322 radv_print_spirv(module->data, module->size, stderr);
323
324 uint32_t num_spec_entries = 0;
325 struct nir_spirv_specialization *spec_entries = NULL;
326 if (spec_info && spec_info->mapEntryCount > 0) {
327 num_spec_entries = spec_info->mapEntryCount;
328 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
329 for (uint32_t i = 0; i < num_spec_entries; i++) {
330 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
331 const void *data = spec_info->pData + entry.offset;
332 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
333
334 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
335 switch (entry.size) {
336 case 8:
337 spec_entries[i].value.u64 = *(const uint64_t *)data;
338 break;
339 case 4:
340 spec_entries[i].value.u32 = *(const uint32_t *)data;
341 break;
342 case 2:
343 spec_entries[i].value.u16 = *(const uint16_t *)data;
344 break;
345 case 1:
346 spec_entries[i].value.u8 = *(const uint8_t *)data;
347 break;
348 default:
349 assert(!"Invalid spec constant size");
350 break;
351 }
352 }
353 }
354 bool int8_int16_enable = !device->physical_device->use_aco ||
355 device->physical_device->rad_info.chip_class >= GFX8;
356 const struct spirv_to_nir_options spirv_options = {
357 .lower_ubo_ssbo_access_to_offsets = true,
358 .caps = {
359 .amd_fragment_mask = true,
360 .amd_gcn_shader = true,
361 .amd_image_gather_bias_lod = true,
362 .amd_image_read_write_lod = true,
363 .amd_shader_ballot = device->physical_device->use_shader_ballot,
364 .amd_shader_explicit_vertex_parameter = true,
365 .amd_trinary_minmax = true,
366 .demote_to_helper_invocation = true,
367 .derivative_group = true,
368 .descriptor_array_dynamic_indexing = true,
369 .descriptor_array_non_uniform_indexing = true,
370 .descriptor_indexing = true,
371 .device_group = true,
372 .draw_parameters = true,
373 .float_controls = true,
374 .float16 = device->physical_device->rad_info.has_packed_math_16bit && !device->physical_device->use_aco,
375 .float64 = true,
376 .geometry_streams = true,
377 .image_ms_array = true,
378 .image_read_without_format = true,
379 .image_write_without_format = true,
380 .int8 = int8_int16_enable,
381 .int16 = int8_int16_enable,
382 .int64 = true,
383 .int64_atomics = true,
384 .min_lod = true,
385 .multiview = true,
386 .physical_storage_buffer_address = true,
387 .post_depth_coverage = true,
388 .runtime_descriptor_array = true,
389 .shader_clock = true,
390 .shader_viewport_index_layer = true,
391 .stencil_export = true,
392 .storage_8bit = int8_int16_enable,
393 .storage_16bit = int8_int16_enable,
394 .storage_image_ms = true,
395 .subgroup_arithmetic = true,
396 .subgroup_ballot = true,
397 .subgroup_basic = true,
398 .subgroup_quad = true,
399 .subgroup_shuffle = true,
400 .subgroup_vote = true,
401 .tessellation = true,
402 .transform_feedback = true,
403 .variable_pointers = true,
404 },
405 .ubo_addr_format = nir_address_format_32bit_index_offset,
406 .ssbo_addr_format = nir_address_format_32bit_index_offset,
407 .phys_ssbo_addr_format = nir_address_format_64bit_global,
408 .push_const_addr_format = nir_address_format_logical,
409 .shared_addr_format = nir_address_format_32bit_offset,
410 .frag_coord_is_sysval = true,
411 };
412 nir = spirv_to_nir(spirv, module->size / 4,
413 spec_entries, num_spec_entries,
414 stage, entrypoint_name,
415 &spirv_options, nir_options);
416 assert(nir->info.stage == stage);
417 nir_validate_shader(nir, "after spirv_to_nir");
418
419 free(spec_entries);
420
421 /* We have to lower away local constant initializers right before we
422 * inline functions. That way they get properly initialized at the top
423 * of the function and not at the top of its caller.
424 */
425 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
426 NIR_PASS_V(nir, nir_lower_returns);
427 NIR_PASS_V(nir, nir_inline_functions);
428 NIR_PASS_V(nir, nir_opt_deref);
429
430 /* Pick off the single entrypoint that we want */
431 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
432 if (func->is_entrypoint)
433 func->name = ralloc_strdup(func, "main");
434 else
435 exec_node_remove(&func->node);
436 }
437 assert(exec_list_length(&nir->functions) == 1);
438
439 /* Make sure we lower constant initializers on output variables so that
440 * nir_remove_dead_variables below sees the corresponding stores
441 */
442 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
443
444 /* Now that we've deleted all but the main function, we can go ahead and
445 * lower the rest of the constant initializers.
446 */
447 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
448
449 /* Split member structs. We do this before lower_io_to_temporaries so that
450 * it doesn't lower system values to temporaries by accident.
451 */
452 NIR_PASS_V(nir, nir_split_var_copies);
453 NIR_PASS_V(nir, nir_split_per_member_structs);
454
455 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
456 device->physical_device->use_aco)
457 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
458 if (nir->info.stage == MESA_SHADER_FRAGMENT)
459 NIR_PASS_V(nir, nir_lower_input_attachments, true);
460
461 NIR_PASS_V(nir, nir_remove_dead_variables,
462 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
463 NULL);
464
465 NIR_PASS_V(nir, nir_propagate_invariant);
466
467 NIR_PASS_V(nir, nir_lower_system_values);
468 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
469 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
470 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
471 NIR_PASS_V(nir, nir_lower_discard_to_demote);
472 }
473
474 /* Vulkan uses the separate-shader linking model */
475 nir->info.separate_shader = true;
476
477 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
478
479 if (nir->info.stage == MESA_SHADER_GEOMETRY)
480 nir_lower_gs_intrinsics(nir, true);
481
482 static const nir_lower_tex_options tex_options = {
483 .lower_txp = ~0,
484 .lower_tg4_offsets = true,
485 };
486
487 nir_lower_tex(nir, &tex_options);
488
489 nir_lower_vars_to_ssa(nir);
490
491 if (nir->info.stage == MESA_SHADER_VERTEX ||
492 nir->info.stage == MESA_SHADER_GEOMETRY ||
493 nir->info.stage == MESA_SHADER_FRAGMENT) {
494 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
495 nir_shader_get_entrypoint(nir), true, true);
496 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
497 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
498 nir_shader_get_entrypoint(nir), true, false);
499 }
500
501 nir_split_var_copies(nir);
502
503 nir_lower_global_vars_to_local(nir);
504 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
505 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
506 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
507 .subgroup_size = subgroup_size,
508 .ballot_bit_size = ballot_bit_size,
509 .lower_to_scalar = 1,
510 .lower_subgroup_masks = 1,
511 .lower_shuffle = 1,
512 .lower_shuffle_to_32bit = 1,
513 .lower_vote_eq_to_ballot = 1,
514 .lower_quad_broadcast_dynamic = 1,
515 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
516 });
517
518 nir_lower_load_const_to_scalar(nir);
519
520 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
521 radv_optimize_nir(nir, false, true);
522
523 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
524 * to remove any copies introduced by nir_opt_find_array_copies().
525 */
526 nir_lower_var_copies(nir);
527
528 /* Lower deref operations for compute shared memory. */
529 if (nir->info.stage == MESA_SHADER_COMPUTE) {
530 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
531 nir_var_mem_shared, shared_var_info);
532 NIR_PASS_V(nir, nir_lower_explicit_io,
533 nir_var_mem_shared, nir_address_format_32bit_offset);
534 }
535
536 /* Lower large variables that are always constant with load_constant
537 * intrinsics, which get turned into PC-relative loads from a data
538 * section next to the shader.
539 */
540 NIR_PASS_V(nir, nir_opt_large_constants,
541 glsl_get_natural_size_align_bytes, 16);
542
543 /* Indirect lowering must be called after the radv_optimize_nir() loop
544 * has been called at least once. Otherwise indirect lowering can
545 * bloat the instruction count of the loop and cause it to be
546 * considered too large for unrolling.
547 */
548 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
549 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
550
551 return nir;
552 }
553
554 static int
555 type_size_vec4(const struct glsl_type *type, bool bindless)
556 {
557 return glsl_count_attribute_slots(type, false);
558 }
559
560 static nir_variable *
561 find_layer_in_var(nir_shader *nir)
562 {
563 nir_foreach_variable(var, &nir->inputs) {
564 if (var->data.location == VARYING_SLOT_LAYER) {
565 return var;
566 }
567 }
568
569 nir_variable *var =
570 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
571 var->data.location = VARYING_SLOT_LAYER;
572 var->data.interpolation = INTERP_MODE_FLAT;
573 return var;
574 }
575
576 /* We use layered rendering to implement multiview, which means we need to map
577 * view_index to gl_Layer. The attachment lowering also uses needs to know the
578 * layer so that it can sample from the correct layer. The code generates a
579 * load from the layer_id sysval, but since we don't have a way to get at this
580 * information from the fragment shader, we also need to lower this to the
581 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
582 * slot, before lowering io, so that nir_assign_var_locations() will give the
583 * LAYER varying the correct driver_location.
584 */
585
586 static bool
587 lower_view_index(nir_shader *nir)
588 {
589 bool progress = false;
590 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
591 nir_builder b;
592 nir_builder_init(&b, entry);
593
594 nir_variable *layer = NULL;
595 nir_foreach_block(block, entry) {
596 nir_foreach_instr_safe(instr, block) {
597 if (instr->type != nir_instr_type_intrinsic)
598 continue;
599
600 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
601 if (load->intrinsic != nir_intrinsic_load_view_index &&
602 load->intrinsic != nir_intrinsic_load_layer_id)
603 continue;
604
605 if (!layer)
606 layer = find_layer_in_var(nir);
607
608 b.cursor = nir_before_instr(instr);
609 nir_ssa_def *def = nir_load_var(&b, layer);
610 nir_ssa_def_rewrite_uses(&load->dest.ssa,
611 nir_src_for_ssa(def));
612
613 nir_instr_remove(instr);
614 progress = true;
615 }
616 }
617
618 return progress;
619 }
620
621 void
622 radv_lower_fs_io(nir_shader *nir)
623 {
624 NIR_PASS_V(nir, lower_view_index);
625 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
626 MESA_SHADER_FRAGMENT);
627
628 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
629
630 /* This pass needs actual constants */
631 nir_opt_constant_folding(nir);
632
633 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
634 }
635
636
637 void *
638 radv_alloc_shader_memory(struct radv_device *device,
639 struct radv_shader_variant *shader)
640 {
641 mtx_lock(&device->shader_slab_mutex);
642 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
643 uint64_t offset = 0;
644 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
645 if (s->bo_offset - offset >= shader->code_size) {
646 shader->bo = slab->bo;
647 shader->bo_offset = offset;
648 list_addtail(&shader->slab_list, &s->slab_list);
649 mtx_unlock(&device->shader_slab_mutex);
650 return slab->ptr + offset;
651 }
652 offset = align_u64(s->bo_offset + s->code_size, 256);
653 }
654 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
655 shader->bo = slab->bo;
656 shader->bo_offset = offset;
657 list_addtail(&shader->slab_list, &slab->shaders);
658 mtx_unlock(&device->shader_slab_mutex);
659 return slab->ptr + offset;
660 }
661 }
662
663 mtx_unlock(&device->shader_slab_mutex);
664 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
665
666 slab->size = MAX2(256 * 1024, shader->code_size);
667 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
668 RADEON_DOMAIN_VRAM,
669 RADEON_FLAG_NO_INTERPROCESS_SHARING |
670 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
671 0 : RADEON_FLAG_READ_ONLY),
672 RADV_BO_PRIORITY_SHADER);
673 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
674 list_inithead(&slab->shaders);
675
676 mtx_lock(&device->shader_slab_mutex);
677 list_add(&slab->slabs, &device->shader_slabs);
678
679 shader->bo = slab->bo;
680 shader->bo_offset = 0;
681 list_add(&shader->slab_list, &slab->shaders);
682 mtx_unlock(&device->shader_slab_mutex);
683 return slab->ptr;
684 }
685
686 void
687 radv_destroy_shader_slabs(struct radv_device *device)
688 {
689 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
690 device->ws->buffer_destroy(slab->bo);
691 free(slab);
692 }
693 mtx_destroy(&device->shader_slab_mutex);
694 }
695
696 /* For the UMR disassembler. */
697 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
698 #define DEBUGGER_NUM_MARKERS 5
699
700 static unsigned
701 radv_get_shader_binary_size(size_t code_size)
702 {
703 return code_size + DEBUGGER_NUM_MARKERS * 4;
704 }
705
706 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
707 const struct ac_shader_config *config_in,
708 const struct radv_shader_info *info,
709 gl_shader_stage stage,
710 struct ac_shader_config *config_out)
711 {
712 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
713 unsigned vgpr_comp_cnt = 0;
714 unsigned num_input_vgprs = info->num_input_vgprs;
715
716 if (stage == MESA_SHADER_FRAGMENT) {
717 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
718 }
719
720 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
721 /* +3 for scratch wave offset and VCC */
722 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
723 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
724 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
725 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
726 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
727 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
728
729 *config_out = *config_in;
730 config_out->num_vgprs = num_vgprs;
731 config_out->num_sgprs = num_sgprs;
732 config_out->num_shared_vgprs = num_shared_vgprs;
733
734 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
735 S_00B12C_SCRATCH_EN(scratch_enabled);
736
737 if (!pdevice->use_ngg_streamout) {
738 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
739 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
740 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
741 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
742 S_00B12C_SO_EN(!!info->so.num_outputs);
743 }
744
745 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
746 (info->wave_size == 32 ? 8 : 4)) |
747 S_00B848_DX10_CLAMP(1) |
748 S_00B848_FLOAT_MODE(config_out->float_mode);
749
750 if (pdevice->rad_info.chip_class >= GFX10) {
751 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
752 } else {
753 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
754 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
755 }
756
757 switch (stage) {
758 case MESA_SHADER_TESS_EVAL:
759 if (info->is_ngg) {
760 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
761 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
762 } else if (info->tes.as_es) {
763 assert(pdevice->rad_info.chip_class <= GFX8);
764 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
765
766 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
767 } else {
768 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
769 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
770
771 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
772 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
773 }
774 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
775 break;
776 case MESA_SHADER_TESS_CTRL:
777 if (pdevice->rad_info.chip_class >= GFX9) {
778 /* We need at least 2 components for LS.
779 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
780 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
781 */
782 if (pdevice->rad_info.chip_class >= GFX10) {
783 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
784 } else {
785 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
786 }
787 } else {
788 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
789 }
790 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
791 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
792 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
793 break;
794 case MESA_SHADER_VERTEX:
795 if (info->is_ngg) {
796 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
797 } else if (info->vs.as_ls) {
798 assert(pdevice->rad_info.chip_class <= GFX8);
799 /* We need at least 2 components for LS.
800 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
801 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
802 */
803 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
804 } else if (info->vs.as_es) {
805 assert(pdevice->rad_info.chip_class <= GFX8);
806 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
807 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
808 } else {
809 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
810 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
811 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
812 */
813 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
814 vgpr_comp_cnt = 3;
815 } else if (info->vs.export_prim_id) {
816 vgpr_comp_cnt = 2;
817 } else if (info->vs.needs_instance_id) {
818 vgpr_comp_cnt = 1;
819 } else {
820 vgpr_comp_cnt = 0;
821 }
822
823 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
824 }
825 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
826 break;
827 case MESA_SHADER_FRAGMENT:
828 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
829 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
830 break;
831 case MESA_SHADER_GEOMETRY:
832 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
833 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
834 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
835 break;
836 case MESA_SHADER_COMPUTE:
837 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
838 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
839 config_out->rsrc2 |=
840 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
841 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
842 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
843 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
844 info->cs.uses_thread_id[1] ? 1 : 0) |
845 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
846 S_00B84C_LDS_SIZE(config_in->lds_size);
847 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
848
849 break;
850 default:
851 unreachable("unsupported shader type");
852 break;
853 }
854
855 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
856 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
857 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
858 gl_shader_stage es_stage = stage;
859 if (stage == MESA_SHADER_GEOMETRY)
860 es_stage = info->gs.es_type;
861
862 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
863 if (es_stage == MESA_SHADER_VERTEX) {
864 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
865 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
866 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
867 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
868 } else
869 unreachable("Unexpected ES shader stage");
870
871 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
872 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
873 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
874 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
875 } else if (info->uses_prim_id) {
876 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
877 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
878 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
879 } else {
880 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
881 }
882
883 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
884 S_00B228_WGP_MODE(1);
885 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
886 S_00B22C_LDS_SIZE(config_in->lds_size) |
887 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
888 } else if (pdevice->rad_info.chip_class >= GFX9 &&
889 stage == MESA_SHADER_GEOMETRY) {
890 unsigned es_type = info->gs.es_type;
891 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
892
893 if (es_type == MESA_SHADER_VERTEX) {
894 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
895 if (info->vs.needs_instance_id) {
896 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
897 } else {
898 es_vgpr_comp_cnt = 0;
899 }
900 } else if (es_type == MESA_SHADER_TESS_EVAL) {
901 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
902 } else {
903 unreachable("invalid shader ES type");
904 }
905
906 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
907 * VGPR[0:4] are always loaded.
908 */
909 if (info->uses_invocation_id) {
910 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
911 } else if (info->uses_prim_id) {
912 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
913 } else if (info->gs.vertices_in >= 3) {
914 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
915 } else {
916 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
917 }
918
919 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
920 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
921 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
922 } else if (pdevice->rad_info.chip_class >= GFX9 &&
923 stage == MESA_SHADER_TESS_CTRL) {
924 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
925 } else {
926 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
927 }
928 }
929
930 struct radv_shader_variant *
931 radv_shader_variant_create(struct radv_device *device,
932 const struct radv_shader_binary *binary,
933 bool keep_shader_info)
934 {
935 struct ac_shader_config config = {0};
936 struct ac_rtld_binary rtld_binary = {0};
937 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
938 if (!variant)
939 return NULL;
940
941 variant->ref_count = 1;
942
943 if (binary->type == RADV_BINARY_TYPE_RTLD) {
944 struct ac_rtld_symbol lds_symbols[2];
945 unsigned num_lds_symbols = 0;
946 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
947 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
948
949 if (device->physical_device->rad_info.chip_class >= GFX9 &&
950 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
951 !binary->is_gs_copy_shader) {
952 /* We add this symbol even on LLVM <= 8 to ensure that
953 * shader->config.lds_size is set correctly below.
954 */
955 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
956 sym->name = "esgs_ring";
957 sym->size = binary->info.ngg_info.esgs_ring_size;
958 sym->align = 64 * 1024;
959 }
960
961 if (binary->info.is_ngg &&
962 binary->stage == MESA_SHADER_GEOMETRY) {
963 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
964 sym->name = "ngg_emit";
965 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
966 sym->align = 4;
967 }
968
969 struct ac_rtld_open_info open_info = {
970 .info = &device->physical_device->rad_info,
971 .shader_type = binary->stage,
972 .wave_size = binary->info.wave_size,
973 .num_parts = 1,
974 .elf_ptrs = &elf_data,
975 .elf_sizes = &elf_size,
976 .num_shared_lds_symbols = num_lds_symbols,
977 .shared_lds_symbols = lds_symbols,
978 };
979
980 if (!ac_rtld_open(&rtld_binary, open_info)) {
981 free(variant);
982 return NULL;
983 }
984
985 if (!ac_rtld_read_config(&rtld_binary, &config)) {
986 ac_rtld_close(&rtld_binary);
987 free(variant);
988 return NULL;
989 }
990
991 if (rtld_binary.lds_size > 0) {
992 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
993 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
994 }
995
996 variant->code_size = rtld_binary.rx_size;
997 variant->exec_size = rtld_binary.exec_size;
998 } else {
999 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1000 config = ((struct radv_shader_binary_legacy *)binary)->config;
1001 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1002 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1003 }
1004
1005 variant->info = binary->info;
1006 radv_postprocess_config(device->physical_device, &config, &binary->info,
1007 binary->stage, &variant->config);
1008
1009 if (radv_device_use_secure_compile(device->instance)) {
1010 if (binary->type == RADV_BINARY_TYPE_RTLD)
1011 ac_rtld_close(&rtld_binary);
1012
1013 return variant;
1014 }
1015
1016 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1017
1018 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1019 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1020 struct ac_rtld_upload_info info = {
1021 .binary = &rtld_binary,
1022 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1023 .rx_ptr = dest_ptr,
1024 };
1025
1026 if (!ac_rtld_upload(&info)) {
1027 radv_shader_variant_destroy(device, variant);
1028 ac_rtld_close(&rtld_binary);
1029 return NULL;
1030 }
1031
1032 if (keep_shader_info ||
1033 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1034 const char *disasm_data;
1035 size_t disasm_size;
1036 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1037 radv_shader_variant_destroy(device, variant);
1038 ac_rtld_close(&rtld_binary);
1039 return NULL;
1040 }
1041
1042 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1043 variant->disasm_string = malloc(disasm_size + 1);
1044 memcpy(variant->disasm_string, disasm_data, disasm_size);
1045 variant->disasm_string[disasm_size] = 0;
1046 }
1047
1048 ac_rtld_close(&rtld_binary);
1049 } else {
1050 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1051 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1052
1053 /* Add end-of-code markers for the UMR disassembler. */
1054 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1055 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1056 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1057
1058 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1059 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1060
1061 if (bin->stats_size) {
1062 variant->statistics = calloc(bin->stats_size, 1);
1063 memcpy(variant->statistics, bin->data, bin->stats_size);
1064 }
1065 }
1066 return variant;
1067 }
1068
1069 static char *
1070 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1071 int shader_count)
1072 {
1073 char *data = NULL;
1074 char *ret = NULL;
1075 size_t size = 0;
1076 FILE *f = open_memstream(&data, &size);
1077 if (f) {
1078 for (int i = 0; i < shader_count; ++i)
1079 nir_print_shader(shaders[i], f);
1080 fclose(f);
1081 }
1082
1083 ret = malloc(size + 1);
1084 if (ret) {
1085 memcpy(ret, data, size);
1086 ret[size] = 0;
1087 }
1088 free(data);
1089 return ret;
1090 }
1091
1092 static struct radv_shader_variant *
1093 shader_variant_compile(struct radv_device *device,
1094 struct radv_shader_module *module,
1095 struct nir_shader * const *shaders,
1096 int shader_count,
1097 gl_shader_stage stage,
1098 struct radv_shader_info *info,
1099 struct radv_nir_compiler_options *options,
1100 bool gs_copy_shader,
1101 bool keep_shader_info,
1102 bool keep_statistic_info,
1103 struct radv_shader_binary **binary_out)
1104 {
1105 enum radeon_family chip_family = device->physical_device->rad_info.family;
1106 struct radv_shader_binary *binary = NULL;
1107
1108 options->family = chip_family;
1109 options->chip_class = device->physical_device->rad_info.chip_class;
1110 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1111 options->dump_preoptir = options->dump_shader &&
1112 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1113 options->record_ir = keep_shader_info;
1114 options->record_stats = keep_statistic_info;
1115 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1116 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1117 options->address32_hi = device->physical_device->rad_info.address32_hi;
1118 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1119 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1120
1121 struct radv_shader_args args = {};
1122 args.options = options;
1123 args.shader_info = info;
1124 args.is_gs_copy_shader = gs_copy_shader;
1125 radv_declare_shader_args(&args,
1126 gs_copy_shader ? MESA_SHADER_VERTEX
1127 : shaders[shader_count - 1]->info.stage,
1128 shader_count >= 2,
1129 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1130 : MESA_SHADER_VERTEX);
1131
1132 if (!device->physical_device->use_aco ||
1133 options->dump_shader || options->record_ir)
1134 ac_init_llvm_once();
1135
1136 if (device->physical_device->use_aco) {
1137 aco_compile_shader(shader_count, shaders, &binary, &args);
1138 } else {
1139 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1140 }
1141
1142 binary->info = *info;
1143
1144 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1145 keep_shader_info);
1146 if (!variant) {
1147 free(binary);
1148 return NULL;
1149 }
1150
1151 if (options->dump_shader) {
1152 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1153 for (int i = 1; i < shader_count; ++i)
1154 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1155
1156 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1157 }
1158
1159
1160 if (keep_shader_info) {
1161 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1162 if (!gs_copy_shader && !module->nir) {
1163 variant->spirv = malloc(module->size);
1164 if (!variant->spirv) {
1165 free(variant);
1166 free(binary);
1167 return NULL;
1168 }
1169
1170 memcpy(variant->spirv, module->data, module->size);
1171 variant->spirv_size = module->size;
1172 }
1173 }
1174
1175 if (binary_out)
1176 *binary_out = binary;
1177 else
1178 free(binary);
1179
1180 return variant;
1181 }
1182
1183 struct radv_shader_variant *
1184 radv_shader_variant_compile(struct radv_device *device,
1185 struct radv_shader_module *module,
1186 struct nir_shader *const *shaders,
1187 int shader_count,
1188 struct radv_pipeline_layout *layout,
1189 const struct radv_shader_variant_key *key,
1190 struct radv_shader_info *info,
1191 bool keep_shader_info, bool keep_statistic_info,
1192 struct radv_shader_binary **binary_out)
1193 {
1194 struct radv_nir_compiler_options options = {0};
1195
1196 options.layout = layout;
1197 if (key)
1198 options.key = *key;
1199
1200 options.explicit_scratch_args = device->physical_device->use_aco;
1201 options.robust_buffer_access = device->robust_buffer_access;
1202
1203 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1204 &options, false, keep_shader_info, keep_statistic_info, binary_out);
1205 }
1206
1207 struct radv_shader_variant *
1208 radv_create_gs_copy_shader(struct radv_device *device,
1209 struct nir_shader *shader,
1210 struct radv_shader_info *info,
1211 struct radv_shader_binary **binary_out,
1212 bool keep_shader_info, bool keep_statistic_info,
1213 bool multiview)
1214 {
1215 struct radv_nir_compiler_options options = {0};
1216
1217 options.explicit_scratch_args = device->physical_device->use_aco;
1218 options.key.has_multiview_view_index = multiview;
1219
1220 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1221 info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
1222 }
1223
1224 void
1225 radv_shader_variant_destroy(struct radv_device *device,
1226 struct radv_shader_variant *variant)
1227 {
1228 if (!p_atomic_dec_zero(&variant->ref_count))
1229 return;
1230
1231 mtx_lock(&device->shader_slab_mutex);
1232 list_del(&variant->slab_list);
1233 mtx_unlock(&device->shader_slab_mutex);
1234
1235 free(variant->spirv);
1236 free(variant->nir_string);
1237 free(variant->disasm_string);
1238 free(variant->ir_string);
1239 free(variant->statistics);
1240 free(variant);
1241 }
1242
1243 const char *
1244 radv_get_shader_name(struct radv_shader_info *info,
1245 gl_shader_stage stage)
1246 {
1247 switch (stage) {
1248 case MESA_SHADER_VERTEX:
1249 if (info->vs.as_ls)
1250 return "Vertex Shader as LS";
1251 else if (info->vs.as_es)
1252 return "Vertex Shader as ES";
1253 else if (info->is_ngg)
1254 return "Vertex Shader as ESGS";
1255 else
1256 return "Vertex Shader as VS";
1257 case MESA_SHADER_TESS_CTRL:
1258 return "Tessellation Control Shader";
1259 case MESA_SHADER_TESS_EVAL:
1260 if (info->tes.as_es)
1261 return "Tessellation Evaluation Shader as ES";
1262 else if (info->is_ngg)
1263 return "Tessellation Evaluation Shader as ESGS";
1264 else
1265 return "Tessellation Evaluation Shader as VS";
1266 case MESA_SHADER_GEOMETRY:
1267 return "Geometry Shader";
1268 case MESA_SHADER_FRAGMENT:
1269 return "Pixel Shader";
1270 case MESA_SHADER_COMPUTE:
1271 return "Compute Shader";
1272 default:
1273 return "Unknown shader";
1274 };
1275 }
1276
1277 unsigned
1278 radv_get_max_workgroup_size(enum chip_class chip_class,
1279 gl_shader_stage stage,
1280 const unsigned *sizes)
1281 {
1282 switch (stage) {
1283 case MESA_SHADER_TESS_CTRL:
1284 return chip_class >= GFX7 ? 128 : 64;
1285 case MESA_SHADER_GEOMETRY:
1286 return chip_class >= GFX9 ? 128 : 64;
1287 case MESA_SHADER_COMPUTE:
1288 break;
1289 default:
1290 return 0;
1291 }
1292
1293 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1294 return max_workgroup_size;
1295 }
1296
1297 unsigned
1298 radv_get_max_waves(struct radv_device *device,
1299 struct radv_shader_variant *variant,
1300 gl_shader_stage stage)
1301 {
1302 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1303 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1304 uint8_t wave_size = variant->info.wave_size;
1305 struct ac_shader_config *conf = &variant->config;
1306 unsigned max_simd_waves;
1307 unsigned lds_per_wave = 0;
1308
1309 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1310
1311 if (stage == MESA_SHADER_FRAGMENT) {
1312 lds_per_wave = conf->lds_size * lds_increment +
1313 align(variant->info.ps.num_interp * 48,
1314 lds_increment);
1315 } else if (stage == MESA_SHADER_COMPUTE) {
1316 unsigned max_workgroup_size =
1317 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1318 lds_per_wave = (conf->lds_size * lds_increment) /
1319 DIV_ROUND_UP(max_workgroup_size, wave_size);
1320 }
1321
1322 if (conf->num_sgprs) {
1323 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1324 max_simd_waves =
1325 MIN2(max_simd_waves,
1326 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1327 sgprs);
1328 }
1329
1330 if (conf->num_vgprs) {
1331 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1332 max_simd_waves =
1333 MIN2(max_simd_waves,
1334 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1335 }
1336
1337 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1338 if (lds_per_wave)
1339 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1340
1341 return max_simd_waves;
1342 }
1343
1344 static void
1345 generate_shader_stats(struct radv_device *device,
1346 struct radv_shader_variant *variant,
1347 gl_shader_stage stage,
1348 struct _mesa_string_buffer *buf)
1349 {
1350 struct ac_shader_config *conf = &variant->config;
1351 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1352
1353 if (stage == MESA_SHADER_FRAGMENT) {
1354 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1355 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1356 "SPI_PS_INPUT_ENA = 0x%04x\n",
1357 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1358 }
1359
1360 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1361 "SGPRS: %d\n"
1362 "VGPRS: %d\n"
1363 "Spilled SGPRs: %d\n"
1364 "Spilled VGPRs: %d\n"
1365 "PrivMem VGPRS: %d\n"
1366 "Code Size: %d bytes\n"
1367 "LDS: %d blocks\n"
1368 "Scratch: %d bytes per wave\n"
1369 "Max Waves: %d\n",
1370 conf->num_sgprs, conf->num_vgprs,
1371 conf->spilled_sgprs, conf->spilled_vgprs,
1372 variant->info.private_mem_vgprs, variant->exec_size,
1373 conf->lds_size, conf->scratch_bytes_per_wave,
1374 max_simd_waves);
1375
1376 if (variant->statistics) {
1377 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1378 for (unsigned i = 0; i < variant->statistics->count; i++) {
1379 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1380 uint32_t value = variant->statistics->values[i];
1381 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1382 }
1383 }
1384
1385 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1386 }
1387
1388 void
1389 radv_shader_dump_stats(struct radv_device *device,
1390 struct radv_shader_variant *variant,
1391 gl_shader_stage stage,
1392 FILE *file)
1393 {
1394 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1395
1396 generate_shader_stats(device, variant, stage, buf);
1397
1398 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1399 fprintf(file, "%s", buf->buf);
1400
1401 _mesa_string_buffer_destroy(buf);
1402 }
1403
1404 VkResult
1405 radv_GetShaderInfoAMD(VkDevice _device,
1406 VkPipeline _pipeline,
1407 VkShaderStageFlagBits shaderStage,
1408 VkShaderInfoTypeAMD infoType,
1409 size_t* pInfoSize,
1410 void* pInfo)
1411 {
1412 RADV_FROM_HANDLE(radv_device, device, _device);
1413 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1414 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1415 struct radv_shader_variant *variant = pipeline->shaders[stage];
1416 struct _mesa_string_buffer *buf;
1417 VkResult result = VK_SUCCESS;
1418
1419 /* Spec doesn't indicate what to do if the stage is invalid, so just
1420 * return no info for this. */
1421 if (!variant)
1422 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1423
1424 switch (infoType) {
1425 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1426 if (!pInfo) {
1427 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1428 } else {
1429 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1430 struct ac_shader_config *conf = &variant->config;
1431
1432 VkShaderStatisticsInfoAMD statistics = {};
1433 statistics.shaderStageMask = shaderStage;
1434 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1435 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1436 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1437
1438 if (stage == MESA_SHADER_COMPUTE) {
1439 unsigned *local_size = variant->info.cs.block_size;
1440 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1441
1442 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1443 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1444
1445 statistics.computeWorkGroupSize[0] = local_size[0];
1446 statistics.computeWorkGroupSize[1] = local_size[1];
1447 statistics.computeWorkGroupSize[2] = local_size[2];
1448 } else {
1449 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1450 }
1451
1452 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1453 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1454 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1455 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1456 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1457
1458 size_t size = *pInfoSize;
1459 *pInfoSize = sizeof(statistics);
1460
1461 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1462
1463 if (size < *pInfoSize)
1464 result = VK_INCOMPLETE;
1465 }
1466
1467 break;
1468 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1469 buf = _mesa_string_buffer_create(NULL, 1024);
1470
1471 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1472 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1473 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1474 generate_shader_stats(device, variant, stage, buf);
1475
1476 /* Need to include the null terminator. */
1477 size_t length = buf->length + 1;
1478
1479 if (!pInfo) {
1480 *pInfoSize = length;
1481 } else {
1482 size_t size = *pInfoSize;
1483 *pInfoSize = length;
1484
1485 memcpy(pInfo, buf->buf, MIN2(size, length));
1486
1487 if (size < length)
1488 result = VK_INCOMPLETE;
1489 }
1490
1491 _mesa_string_buffer_destroy(buf);
1492 break;
1493 default:
1494 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1495 result = VK_ERROR_FEATURE_NOT_PRESENT;
1496 break;
1497 }
1498
1499 return result;
1500 }