2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
49 #include "util/string_buffer.h"
51 static const struct nir_shader_compiler_options nir_options
= {
52 .vertex_id_zero_based
= true,
56 .lower_device_index_to_zero
= true,
60 .lower_pack_snorm_2x16
= true,
61 .lower_pack_snorm_4x8
= true,
62 .lower_pack_unorm_2x16
= true,
63 .lower_pack_unorm_4x8
= true,
64 .lower_unpack_snorm_2x16
= true,
65 .lower_unpack_snorm_4x8
= true,
66 .lower_unpack_unorm_2x16
= true,
67 .lower_unpack_unorm_4x8
= true,
68 .lower_extract_byte
= true,
69 .lower_extract_word
= true,
72 .vs_inputs_dual_locations
= true,
73 .max_unroll_iterations
= 32
76 VkResult
radv_CreateShaderModule(
78 const VkShaderModuleCreateInfo
* pCreateInfo
,
79 const VkAllocationCallbacks
* pAllocator
,
80 VkShaderModule
* pShaderModule
)
82 RADV_FROM_HANDLE(radv_device
, device
, _device
);
83 struct radv_shader_module
*module
;
85 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
86 assert(pCreateInfo
->flags
== 0);
88 module
= vk_alloc2(&device
->alloc
, pAllocator
,
89 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
90 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
92 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
95 module
->size
= pCreateInfo
->codeSize
;
96 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
98 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
100 *pShaderModule
= radv_shader_module_to_handle(module
);
105 void radv_DestroyShaderModule(
107 VkShaderModule _module
,
108 const VkAllocationCallbacks
* pAllocator
)
110 RADV_FROM_HANDLE(radv_device
, device
, _device
);
111 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
116 vk_free2(&device
->alloc
, pAllocator
, module
);
120 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
)
127 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
128 NIR_PASS_V(shader
, nir_lower_pack
);
129 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
130 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
132 NIR_PASS(progress
, shader
, nir_copy_prop
);
133 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
134 NIR_PASS(progress
, shader
, nir_opt_dce
);
135 if (nir_opt_trivial_continues(shader
)) {
137 NIR_PASS(progress
, shader
, nir_copy_prop
);
138 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
139 NIR_PASS(progress
, shader
, nir_opt_dce
);
141 NIR_PASS(progress
, shader
, nir_opt_if
);
142 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
143 NIR_PASS(progress
, shader
, nir_opt_cse
);
144 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
145 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
146 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
147 NIR_PASS(progress
, shader
, nir_opt_undef
);
148 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
149 if (shader
->options
->max_unroll_iterations
) {
150 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
152 } while (progress
&& !optimize_conservatively
);
154 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
155 NIR_PASS(progress
, shader
, nir_opt_move_load_ubo
);
159 radv_shader_compile_to_nir(struct radv_device
*device
,
160 struct radv_shader_module
*module
,
161 const char *entrypoint_name
,
162 gl_shader_stage stage
,
163 const VkSpecializationInfo
*spec_info
,
164 const VkPipelineCreateFlags flags
)
167 nir_function
*entry_point
;
169 /* Some things such as our meta clear/blit code will give us a NIR
170 * shader directly. In that case, we just ignore the SPIR-V entirely
171 * and just use the NIR shader */
173 nir
->options
= &nir_options
;
174 nir_validate_shader(nir
);
176 assert(exec_list_length(&nir
->functions
) == 1);
177 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
178 entry_point
= exec_node_data(nir_function
, node
, node
);
180 uint32_t *spirv
= (uint32_t *) module
->data
;
181 assert(module
->size
% 4 == 0);
183 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
184 radv_print_spirv(spirv
, module
->size
, stderr
);
186 uint32_t num_spec_entries
= 0;
187 struct nir_spirv_specialization
*spec_entries
= NULL
;
188 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
189 num_spec_entries
= spec_info
->mapEntryCount
;
190 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
191 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
192 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
193 const void *data
= spec_info
->pData
+ entry
.offset
;
194 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
196 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
197 if (spec_info
->dataSize
== 8)
198 spec_entries
[i
].data64
= *(const uint64_t *)data
;
200 spec_entries
[i
].data32
= *(const uint32_t *)data
;
203 const struct spirv_to_nir_options spirv_options
= {
205 .device_group
= true,
206 .draw_parameters
= true,
208 .image_read_without_format
= true,
209 .image_write_without_format
= true,
210 .tessellation
= true,
213 .subgroup_ballot
= true,
214 .subgroup_basic
= true,
215 .subgroup_quad
= true,
216 .subgroup_shuffle
= true,
217 .subgroup_vote
= true,
218 .variable_pointers
= true,
220 .trinary_minmax
= true,
221 .shader_viewport_index_layer
= true,
222 .descriptor_array_dynamic_indexing
= true,
223 .runtime_descriptor_array
= true,
226 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
227 spec_entries
, num_spec_entries
,
228 stage
, entrypoint_name
,
229 &spirv_options
, &nir_options
);
230 nir
= entry_point
->shader
;
231 assert(nir
->info
.stage
== stage
);
232 nir_validate_shader(nir
);
236 /* We have to lower away local constant initializers right before we
237 * inline functions. That way they get properly initialized at the top
238 * of the function and not at the top of its caller.
240 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
241 NIR_PASS_V(nir
, nir_lower_returns
);
242 NIR_PASS_V(nir
, nir_inline_functions
);
244 /* Pick off the single entrypoint that we want */
245 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
246 if (func
!= entry_point
)
247 exec_node_remove(&func
->node
);
249 assert(exec_list_length(&nir
->functions
) == 1);
250 entry_point
->name
= ralloc_strdup(entry_point
, "main");
252 /* Make sure we lower constant initializers on output variables so that
253 * nir_remove_dead_variables below sees the corresponding stores
255 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
257 NIR_PASS_V(nir
, nir_remove_dead_variables
,
258 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
260 /* Now that we've deleted all but the main function, we can go ahead and
261 * lower the rest of the constant initializers.
263 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
264 NIR_PASS_V(nir
, nir_lower_system_values
);
265 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
268 /* Vulkan uses the separate-shader linking model */
269 nir
->info
.separate_shader
= true;
271 nir_shader_gather_info(nir
, entry_point
->impl
);
273 static const nir_lower_tex_options tex_options
= {
277 nir_lower_tex(nir
, &tex_options
);
279 nir_lower_vars_to_ssa(nir
);
281 nir_split_var_copies(nir
);
282 nir_lower_var_copies(nir
);
284 nir_lower_global_vars_to_local(nir
);
285 nir_remove_dead_variables(nir
, nir_var_local
);
286 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
288 .ballot_bit_size
= 64,
289 .lower_to_scalar
= 1,
290 .lower_subgroup_masks
= 1,
292 .lower_shuffle_to_32bit
= 1,
293 .lower_vote_eq_to_ballot
= 1,
296 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
297 radv_optimize_nir(nir
, false);
299 /* Indirect lowering must be called after the radv_optimize_nir() loop
300 * has been called at least once. Otherwise indirect lowering can
301 * bloat the instruction count of the loop and cause it to be
302 * considered too large for unrolling.
304 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
305 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
);
311 radv_alloc_shader_memory(struct radv_device
*device
,
312 struct radv_shader_variant
*shader
)
314 mtx_lock(&device
->shader_slab_mutex
);
315 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
317 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
318 if (s
->bo_offset
- offset
>= shader
->code_size
) {
319 shader
->bo
= slab
->bo
;
320 shader
->bo_offset
= offset
;
321 list_addtail(&shader
->slab_list
, &s
->slab_list
);
322 mtx_unlock(&device
->shader_slab_mutex
);
323 return slab
->ptr
+ offset
;
325 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
327 if (slab
->size
- offset
>= shader
->code_size
) {
328 shader
->bo
= slab
->bo
;
329 shader
->bo_offset
= offset
;
330 list_addtail(&shader
->slab_list
, &slab
->shaders
);
331 mtx_unlock(&device
->shader_slab_mutex
);
332 return slab
->ptr
+ offset
;
336 mtx_unlock(&device
->shader_slab_mutex
);
337 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
339 slab
->size
= 256 * 1024;
340 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
342 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
343 device
->physical_device
->cpdma_prefetch_writes_memory
?
344 0 : RADEON_FLAG_READ_ONLY
);
345 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
346 list_inithead(&slab
->shaders
);
348 mtx_lock(&device
->shader_slab_mutex
);
349 list_add(&slab
->slabs
, &device
->shader_slabs
);
351 shader
->bo
= slab
->bo
;
352 shader
->bo_offset
= 0;
353 list_add(&shader
->slab_list
, &slab
->shaders
);
354 mtx_unlock(&device
->shader_slab_mutex
);
359 radv_destroy_shader_slabs(struct radv_device
*device
)
361 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
362 device
->ws
->buffer_destroy(slab
->bo
);
365 mtx_destroy(&device
->shader_slab_mutex
);
369 radv_fill_shader_variant(struct radv_device
*device
,
370 struct radv_shader_variant
*variant
,
371 struct ac_shader_binary
*binary
,
372 gl_shader_stage stage
)
374 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
375 struct radv_shader_info
*info
= &variant
->info
.info
;
376 unsigned vgpr_comp_cnt
= 0;
378 variant
->code_size
= binary
->code_size
;
379 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
380 S_00B12C_SCRATCH_EN(scratch_enabled
);
382 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
383 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
384 S_00B848_DX10_CLAMP(1) |
385 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
388 case MESA_SHADER_TESS_EVAL
:
390 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
392 case MESA_SHADER_TESS_CTRL
:
393 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
394 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
396 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
399 case MESA_SHADER_VERTEX
:
400 case MESA_SHADER_GEOMETRY
:
401 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
403 case MESA_SHADER_FRAGMENT
:
405 case MESA_SHADER_COMPUTE
:
407 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
408 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
409 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
410 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
411 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
412 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
413 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
416 unreachable("unsupported shader type");
420 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
421 stage
== MESA_SHADER_GEOMETRY
) {
422 unsigned es_type
= variant
->info
.gs
.es_type
;
423 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
425 if (es_type
== MESA_SHADER_VERTEX
) {
426 es_vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
427 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
428 es_vgpr_comp_cnt
= 3;
430 unreachable("invalid shader ES type");
433 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
434 * VGPR[0:4] are always loaded.
436 if (info
->uses_invocation_id
) {
437 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
438 } else if (info
->uses_prim_id
) {
439 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
440 } else if (variant
->info
.gs
.vertices_in
>= 3) {
441 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
443 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
446 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
447 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
448 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
449 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
450 stage
== MESA_SHADER_TESS_CTRL
) {
451 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
453 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
456 void *ptr
= radv_alloc_shader_memory(device
, variant
);
457 memcpy(ptr
, binary
->code
, binary
->code_size
);
460 static struct radv_shader_variant
*
461 shader_variant_create(struct radv_device
*device
,
462 struct radv_shader_module
*module
,
463 struct nir_shader
* const *shaders
,
465 gl_shader_stage stage
,
466 struct radv_nir_compiler_options
*options
,
469 unsigned *code_size_out
)
471 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
472 enum ac_target_machine_options tm_options
= 0;
473 struct radv_shader_variant
*variant
;
474 struct ac_shader_binary binary
;
475 LLVMTargetMachineRef tm
;
477 variant
= calloc(1, sizeof(struct radv_shader_variant
));
481 options
->family
= chip_family
;
482 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
483 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
484 options
->dump_preoptir
= options
->dump_shader
&&
485 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
486 options
->record_llvm_ir
= device
->keep_shader_info
;
487 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
488 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
490 if (options
->supports_spill
)
491 tm_options
|= AC_TM_SUPPORTS_SPILL
;
492 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
493 tm_options
|= AC_TM_SISCHED
;
494 tm
= ac_create_target_machine(chip_family
, tm_options
, NULL
);
496 if (gs_copy_shader
) {
497 assert(shader_count
== 1);
498 radv_compile_gs_copy_shader(tm
, *shaders
, &binary
,
499 &variant
->config
, &variant
->info
,
502 radv_compile_nir_shader(tm
, &binary
, &variant
->config
,
503 &variant
->info
, shaders
, shader_count
,
507 LLVMDisposeTargetMachine(tm
);
509 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
512 *code_out
= binary
.code
;
513 *code_size_out
= binary
.code_size
;
518 free(binary
.global_symbol_offsets
);
520 variant
->ref_count
= 1;
522 if (device
->keep_shader_info
) {
523 variant
->disasm_string
= binary
.disasm_string
;
524 variant
->llvm_ir_string
= binary
.llvm_ir_string
;
525 if (!gs_copy_shader
&& !module
->nir
) {
526 variant
->nir
= *shaders
;
527 variant
->spirv
= (uint32_t *)module
->data
;
528 variant
->spirv_size
= module
->size
;
531 free(binary
.disasm_string
);
537 struct radv_shader_variant
*
538 radv_shader_variant_create(struct radv_device
*device
,
539 struct radv_shader_module
*module
,
540 struct nir_shader
*const *shaders
,
542 struct radv_pipeline_layout
*layout
,
543 const struct radv_shader_variant_key
*key
,
545 unsigned *code_size_out
)
547 struct radv_nir_compiler_options options
= {0};
549 options
.layout
= layout
;
553 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
554 options
.supports_spill
= true;
556 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
557 &options
, false, code_out
, code_size_out
);
560 struct radv_shader_variant
*
561 radv_create_gs_copy_shader(struct radv_device
*device
,
562 struct nir_shader
*shader
,
564 unsigned *code_size_out
,
567 struct radv_nir_compiler_options options
= {0};
569 options
.key
.has_multiview_view_index
= multiview
;
571 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
572 &options
, true, code_out
, code_size_out
);
576 radv_shader_variant_destroy(struct radv_device
*device
,
577 struct radv_shader_variant
*variant
)
579 if (!p_atomic_dec_zero(&variant
->ref_count
))
582 mtx_lock(&device
->shader_slab_mutex
);
583 list_del(&variant
->slab_list
);
584 mtx_unlock(&device
->shader_slab_mutex
);
586 ralloc_free(variant
->nir
);
587 free(variant
->disasm_string
);
588 free(variant
->llvm_ir_string
);
593 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
596 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
597 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
598 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
599 case MESA_SHADER_COMPUTE
: return "Compute Shader";
600 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
601 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
603 return "Unknown shader";
608 generate_shader_stats(struct radv_device
*device
,
609 struct radv_shader_variant
*variant
,
610 gl_shader_stage stage
,
611 struct _mesa_string_buffer
*buf
)
613 unsigned lds_increment
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
614 struct ac_shader_config
*conf
;
615 unsigned max_simd_waves
;
616 unsigned lds_per_wave
= 0;
618 max_simd_waves
= ac_get_max_simd_waves(device
->physical_device
->rad_info
.family
);
620 conf
= &variant
->config
;
622 if (stage
== MESA_SHADER_FRAGMENT
) {
623 lds_per_wave
= conf
->lds_size
* lds_increment
+
624 align(variant
->info
.fs
.num_interp
* 48,
631 radv_get_num_physical_sgprs(device
->physical_device
) / conf
->num_sgprs
);
636 RADV_NUM_PHYSICAL_VGPRS
/ conf
->num_vgprs
);
638 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
642 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
644 if (stage
== MESA_SHADER_FRAGMENT
) {
645 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
646 "SPI_PS_INPUT_ADDR = 0x%04x\n"
647 "SPI_PS_INPUT_ENA = 0x%04x\n",
648 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
651 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
654 "Spilled SGPRs: %d\n"
655 "Spilled VGPRs: %d\n"
656 "PrivMem VGPRS: %d\n"
657 "Code Size: %d bytes\n"
659 "Scratch: %d bytes per wave\n"
661 "********************\n\n\n",
662 conf
->num_sgprs
, conf
->num_vgprs
,
663 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
664 variant
->info
.private_mem_vgprs
, variant
->code_size
,
665 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
670 radv_shader_dump_stats(struct radv_device
*device
,
671 struct radv_shader_variant
*variant
,
672 gl_shader_stage stage
,
675 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
677 generate_shader_stats(device
, variant
, stage
, buf
);
679 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
680 fprintf(file
, "%s", buf
->buf
);
682 _mesa_string_buffer_destroy(buf
);
686 radv_GetShaderInfoAMD(VkDevice _device
,
687 VkPipeline _pipeline
,
688 VkShaderStageFlagBits shaderStage
,
689 VkShaderInfoTypeAMD infoType
,
693 RADV_FROM_HANDLE(radv_device
, device
, _device
);
694 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
695 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
696 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
697 struct _mesa_string_buffer
*buf
;
698 VkResult result
= VK_SUCCESS
;
700 /* Spec doesn't indicate what to do if the stage is invalid, so just
701 * return no info for this. */
703 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT
);
706 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
708 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
710 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
711 struct ac_shader_config
*conf
= &variant
->config
;
713 VkShaderStatisticsInfoAMD statistics
= {};
714 statistics
.shaderStageMask
= shaderStage
;
715 statistics
.numPhysicalVgprs
= RADV_NUM_PHYSICAL_VGPRS
;
716 statistics
.numPhysicalSgprs
= radv_get_num_physical_sgprs(device
->physical_device
);
717 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
719 if (stage
== MESA_SHADER_COMPUTE
) {
720 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
721 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
723 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
724 ceil(workgroup_size
/ statistics
.numPhysicalVgprs
);
726 statistics
.computeWorkGroupSize
[0] = local_size
[0];
727 statistics
.computeWorkGroupSize
[1] = local_size
[1];
728 statistics
.computeWorkGroupSize
[2] = local_size
[2];
730 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
733 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
734 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
735 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
736 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
737 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
739 size_t size
= *pInfoSize
;
740 *pInfoSize
= sizeof(statistics
);
742 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
744 if (size
< *pInfoSize
)
745 result
= VK_INCOMPLETE
;
749 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
750 buf
= _mesa_string_buffer_create(NULL
, 1024);
752 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
753 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
754 generate_shader_stats(device
, variant
, stage
, buf
);
756 /* Need to include the null terminator. */
757 size_t length
= buf
->length
+ 1;
762 size_t size
= *pInfoSize
;
765 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
768 result
= VK_INCOMPLETE
;
771 _mesa_string_buffer_destroy(buf
);
774 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
775 result
= VK_ERROR_FEATURE_NOT_PRESENT
;