projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: enable SpvCapabilityImageMSArray
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41 #include <llvm-c/Support.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "ac_rtld.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51
52 #include "aco_interface.h"
53
54 #include "util/string_buffer.h"
55
56 static const struct nir_shader_compiler_options nir_options_llvm = {
57 .vertex_id_zero_based = true,
58 .lower_scmp = true,
59 .lower_flrp16 = true,
60 .lower_flrp32 = true,
61 .lower_flrp64 = true,
62 .lower_device_index_to_zero = true,
63 .lower_fsat = true,
64 .lower_fdiv = true,
65 .lower_fmod = true,
66 .lower_bitfield_insert_to_bitfield_select = true,
67 .lower_bitfield_extract = true,
68 .lower_sub = true,
69 .lower_pack_snorm_2x16 = true,
70 .lower_pack_snorm_4x8 = true,
71 .lower_pack_unorm_2x16 = true,
72 .lower_pack_unorm_4x8 = true,
73 .lower_unpack_snorm_2x16 = true,
74 .lower_unpack_snorm_4x8 = true,
75 .lower_unpack_unorm_2x16 = true,
76 .lower_unpack_unorm_4x8 = true,
77 .lower_extract_byte = true,
78 .lower_extract_word = true,
79 .lower_ffma = true,
80 .lower_fpow = true,
81 .lower_mul_2x32_64 = true,
82 .lower_rotate = true,
83 .max_unroll_iterations = 32,
84 .use_interpolated_input_intrinsics = true,
85 /* nir_lower_int64() isn't actually called for the LLVM backend, but
86 * this helps the loop unrolling heuristics. */
87 .lower_int64_options = nir_lower_imul64 |
88 nir_lower_imul_high64 |
89 nir_lower_imul_2x32_64 |
90 nir_lower_divmod64 |
91 nir_lower_minmax64 |
92 nir_lower_iabs64,
93 };
94
95 static const struct nir_shader_compiler_options nir_options_aco = {
96 .vertex_id_zero_based = true,
97 .lower_scmp = true,
98 .lower_flrp16 = true,
99 .lower_flrp32 = true,
100 .lower_flrp64 = true,
101 .lower_device_index_to_zero = true,
102 .lower_fdiv = true,
103 .lower_fmod = true,
104 .lower_bitfield_insert_to_bitfield_select = true,
105 .lower_bitfield_extract = true,
106 .lower_pack_snorm_2x16 = true,
107 .lower_pack_snorm_4x8 = true,
108 .lower_pack_unorm_2x16 = true,
109 .lower_pack_unorm_4x8 = true,
110 .lower_unpack_snorm_2x16 = true,
111 .lower_unpack_snorm_4x8 = true,
112 .lower_unpack_unorm_2x16 = true,
113 .lower_unpack_unorm_4x8 = true,
114 .lower_unpack_half_2x16 = true,
115 .lower_extract_byte = true,
116 .lower_extract_word = true,
117 .lower_ffma = true,
118 .lower_fpow = true,
119 .lower_mul_2x32_64 = true,
120 .lower_rotate = true,
121 .max_unroll_iterations = 32,
122 .use_interpolated_input_intrinsics = true,
123 .lower_int64_options = nir_lower_imul64 |
124 nir_lower_imul_high64 |
125 nir_lower_imul_2x32_64 |
126 nir_lower_divmod64 |
127 nir_lower_logic64 |
128 nir_lower_minmax64 |
129 nir_lower_iabs64,
130 };
131
132 bool
133 radv_can_dump_shader(struct radv_device *device,
134 struct radv_shader_module *module,
135 bool is_gs_copy_shader)
136 {
137 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
138 return false;
139 if (module)
140 return !module->nir ||
141 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
142
143 return is_gs_copy_shader;
144 }
145
146 bool
147 radv_can_dump_shader_stats(struct radv_device *device,
148 struct radv_shader_module *module)
149 {
150 /* Only dump non-meta shader stats. */
151 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
152 module && !module->nir;
153 }
154
155 unsigned shader_io_get_unique_index(gl_varying_slot slot)
156 {
157 /* handle patch indices separate */
158 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
159 return 0;
160 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
161 return 1;
162 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
163 return 2 + (slot - VARYING_SLOT_PATCH0);
164 if (slot == VARYING_SLOT_POS)
165 return 0;
166 if (slot == VARYING_SLOT_PSIZ)
167 return 1;
168 if (slot == VARYING_SLOT_CLIP_DIST0)
169 return 2;
170 if (slot == VARYING_SLOT_CLIP_DIST1)
171 return 3;
172 /* 3 is reserved for clip dist as well */
173 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
174 return 4 + (slot - VARYING_SLOT_VAR0);
175 unreachable("illegal slot in get unique index\n");
176 }
177
178 VkResult radv_CreateShaderModule(
179 VkDevice _device,
180 const VkShaderModuleCreateInfo* pCreateInfo,
181 const VkAllocationCallbacks* pAllocator,
182 VkShaderModule* pShaderModule)
183 {
184 RADV_FROM_HANDLE(radv_device, device, _device);
185 struct radv_shader_module *module;
186
187 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
188 assert(pCreateInfo->flags == 0);
189
190 module = vk_alloc2(&device->alloc, pAllocator,
191 sizeof(*module) + pCreateInfo->codeSize, 8,
192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
193 if (module == NULL)
194 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
195
196 module->nir = NULL;
197 module->size = pCreateInfo->codeSize;
198 memcpy(module->data, pCreateInfo->pCode, module->size);
199
200 _mesa_sha1_compute(module->data, module->size, module->sha1);
201
202 *pShaderModule = radv_shader_module_to_handle(module);
203
204 return VK_SUCCESS;
205 }
206
207 void radv_DestroyShaderModule(
208 VkDevice _device,
209 VkShaderModule _module,
210 const VkAllocationCallbacks* pAllocator)
211 {
212 RADV_FROM_HANDLE(radv_device, device, _device);
213 RADV_FROM_HANDLE(radv_shader_module, module, _module);
214
215 if (!module)
216 return;
217
218 vk_free2(&device->alloc, pAllocator, module);
219 }
220
221 void
222 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
223 bool allow_copies)
224 {
225 bool progress;
226 unsigned lower_flrp =
227 (shader->options->lower_flrp16 ? 16 : 0) |
228 (shader->options->lower_flrp32 ? 32 : 0) |
229 (shader->options->lower_flrp64 ? 64 : 0);
230
231 do {
232 progress = false;
233
234 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
235 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
236
237 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
238 NIR_PASS_V(shader, nir_lower_pack);
239
240 if (allow_copies) {
241 /* Only run this pass in the first call to
242 * radv_optimize_nir. Later calls assume that we've
243 * lowered away any copy_deref instructions and we
244 * don't want to introduce any more.
245 */
246 NIR_PASS(progress, shader, nir_opt_find_array_copies);
247 }
248
249 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
250 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
251 NIR_PASS(progress, shader, nir_remove_dead_variables,
252 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out);
253
254 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
255 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
256
257 NIR_PASS(progress, shader, nir_copy_prop);
258 NIR_PASS(progress, shader, nir_opt_remove_phis);
259 NIR_PASS(progress, shader, nir_opt_dce);
260 if (nir_opt_trivial_continues(shader)) {
261 progress = true;
262 NIR_PASS(progress, shader, nir_copy_prop);
263 NIR_PASS(progress, shader, nir_opt_remove_phis);
264 NIR_PASS(progress, shader, nir_opt_dce);
265 }
266 NIR_PASS(progress, shader, nir_opt_if, true);
267 NIR_PASS(progress, shader, nir_opt_dead_cf);
268 NIR_PASS(progress, shader, nir_opt_cse);
269 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
270 NIR_PASS(progress, shader, nir_opt_constant_folding);
271 NIR_PASS(progress, shader, nir_opt_algebraic);
272
273 if (lower_flrp != 0) {
274 bool lower_flrp_progress = false;
275 NIR_PASS(lower_flrp_progress,
276 shader,
277 nir_lower_flrp,
278 lower_flrp,
279 false /* always_precise */,
280 shader->options->lower_ffma);
281 if (lower_flrp_progress) {
282 NIR_PASS(progress, shader,
283 nir_opt_constant_folding);
284 progress = true;
285 }
286
287 /* Nothing should rematerialize any flrps, so we only
288 * need to do this lowering once.
289 */
290 lower_flrp = 0;
291 }
292
293 NIR_PASS(progress, shader, nir_opt_undef);
294 if (shader->options->max_unroll_iterations) {
295 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
296 }
297 } while (progress && !optimize_conservatively);
298
299 NIR_PASS(progress, shader, nir_opt_conditional_discard);
300 NIR_PASS(progress, shader, nir_opt_shrink_load);
301 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
302 }
303
304 static void
305 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
306 {
307 assert(glsl_type_is_vector_or_scalar(type));
308
309 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
310 unsigned length = glsl_get_vector_elements(type);
311 *size = comp_size * length,
312 *align = comp_size;
313 }
314
315 nir_shader *
316 radv_shader_compile_to_nir(struct radv_device *device,
317 struct radv_shader_module *module,
318 const char *entrypoint_name,
319 gl_shader_stage stage,
320 const VkSpecializationInfo *spec_info,
321 const VkPipelineCreateFlags flags,
322 const struct radv_pipeline_layout *layout,
323 bool use_aco)
324 {
325 nir_shader *nir;
326 const nir_shader_compiler_options *nir_options = use_aco ? &nir_options_aco :
327 &nir_options_llvm;
328 if (module->nir) {
329 /* Some things such as our meta clear/blit code will give us a NIR
330 * shader directly. In that case, we just ignore the SPIR-V entirely
331 * and just use the NIR shader */
332 nir = module->nir;
333 nir->options = nir_options;
334 nir_validate_shader(nir, "in internal shader");
335
336 assert(exec_list_length(&nir->functions) == 1);
337 } else {
338 uint32_t *spirv = (uint32_t *) module->data;
339 assert(module->size % 4 == 0);
340
341 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
342 radv_print_spirv(module->data, module->size, stderr);
343
344 uint32_t num_spec_entries = 0;
345 struct nir_spirv_specialization *spec_entries = NULL;
346 if (spec_info && spec_info->mapEntryCount > 0) {
347 num_spec_entries = spec_info->mapEntryCount;
348 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
349 for (uint32_t i = 0; i < num_spec_entries; i++) {
350 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
351 const void *data = spec_info->pData + entry.offset;
352 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
353
354 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
355 if (spec_info->dataSize == 8)
356 spec_entries[i].data64 = *(const uint64_t *)data;
357 else
358 spec_entries[i].data32 = *(const uint32_t *)data;
359 }
360 }
361 const struct spirv_to_nir_options spirv_options = {
362 .lower_ubo_ssbo_access_to_offsets = true,
363 .caps = {
364 .amd_gcn_shader = true,
365 .amd_shader_ballot = device->physical_device->use_shader_ballot,
366 .amd_trinary_minmax = true,
367 .demote_to_helper_invocation = device->physical_device->use_aco,
368 .derivative_group = true,
369 .descriptor_array_dynamic_indexing = true,
370 .descriptor_array_non_uniform_indexing = true,
371 .descriptor_indexing = true,
372 .device_group = true,
373 .draw_parameters = true,
374 .float_controls = true,
375 .float16 = !device->physical_device->use_aco,
376 .float64 = true,
377 .geometry_streams = true,
378 .image_ms_array = true,
379 .image_read_without_format = true,
380 .image_write_without_format = true,
381 .int8 = !device->physical_device->use_aco,
382 .int16 = !device->physical_device->use_aco,
383 .int64 = true,
384 .int64_atomics = true,
385 .multiview = true,
386 .physical_storage_buffer_address = true,
387 .post_depth_coverage = true,
388 .runtime_descriptor_array = true,
389 .shader_clock = true,
390 .shader_viewport_index_layer = true,
391 .stencil_export = true,
392 .storage_8bit = !device->physical_device->use_aco,
393 .storage_16bit = !device->physical_device->use_aco,
394 .storage_image_ms = true,
395 .subgroup_arithmetic = true,
396 .subgroup_ballot = true,
397 .subgroup_basic = true,
398 .subgroup_quad = true,
399 .subgroup_shuffle = true,
400 .subgroup_vote = true,
401 .tessellation = true,
402 .transform_feedback = true,
403 .variable_pointers = true,
404 },
405 .ubo_addr_format = nir_address_format_32bit_index_offset,
406 .ssbo_addr_format = nir_address_format_32bit_index_offset,
407 .phys_ssbo_addr_format = nir_address_format_64bit_global,
408 .push_const_addr_format = nir_address_format_logical,
409 .shared_addr_format = nir_address_format_32bit_offset,
410 .frag_coord_is_sysval = true,
411 };
412 nir = spirv_to_nir(spirv, module->size / 4,
413 spec_entries, num_spec_entries,
414 stage, entrypoint_name,
415 &spirv_options, nir_options);
416 assert(nir->info.stage == stage);
417 nir_validate_shader(nir, "after spirv_to_nir");
418
419 free(spec_entries);
420
421 /* We have to lower away local constant initializers right before we
422 * inline functions. That way they get properly initialized at the top
423 * of the function and not at the top of its caller.
424 */
425 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
426 NIR_PASS_V(nir, nir_lower_returns);
427 NIR_PASS_V(nir, nir_inline_functions);
428 NIR_PASS_V(nir, nir_opt_deref);
429
430 /* Pick off the single entrypoint that we want */
431 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
432 if (func->is_entrypoint)
433 func->name = ralloc_strdup(func, "main");
434 else
435 exec_node_remove(&func->node);
436 }
437 assert(exec_list_length(&nir->functions) == 1);
438
439 /* Make sure we lower constant initializers on output variables so that
440 * nir_remove_dead_variables below sees the corresponding stores
441 */
442 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
443
444 /* Now that we've deleted all but the main function, we can go ahead and
445 * lower the rest of the constant initializers.
446 */
447 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
448
449 /* Split member structs. We do this before lower_io_to_temporaries so that
450 * it doesn't lower system values to temporaries by accident.
451 */
452 NIR_PASS_V(nir, nir_split_var_copies);
453 NIR_PASS_V(nir, nir_split_per_member_structs);
454
455 if (nir->info.stage == MESA_SHADER_FRAGMENT && use_aco)
456 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
457 if (nir->info.stage == MESA_SHADER_FRAGMENT)
458 NIR_PASS_V(nir, nir_lower_input_attachments, true);
459
460 NIR_PASS_V(nir, nir_remove_dead_variables,
461 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
462
463 NIR_PASS_V(nir, nir_propagate_invariant);
464
465 NIR_PASS_V(nir, nir_lower_system_values);
466 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
467 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
468 }
469
470 /* Vulkan uses the separate-shader linking model */
471 nir->info.separate_shader = true;
472
473 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
474
475 static const nir_lower_tex_options tex_options = {
476 .lower_txp = ~0,
477 .lower_tg4_offsets = true,
478 };
479
480 nir_lower_tex(nir, &tex_options);
481
482 nir_lower_vars_to_ssa(nir);
483
484 if (nir->info.stage == MESA_SHADER_VERTEX ||
485 nir->info.stage == MESA_SHADER_GEOMETRY ||
486 nir->info.stage == MESA_SHADER_FRAGMENT) {
487 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
488 nir_shader_get_entrypoint(nir), true, true);
489 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
490 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
491 nir_shader_get_entrypoint(nir), true, false);
492 }
493
494 nir_split_var_copies(nir);
495
496 nir_lower_global_vars_to_local(nir);
497 nir_remove_dead_variables(nir, nir_var_function_temp);
498 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
499 .subgroup_size = 64,
500 .ballot_bit_size = 64,
501 .lower_to_scalar = 1,
502 .lower_subgroup_masks = 1,
503 .lower_shuffle = 1,
504 .lower_shuffle_to_32bit = 1,
505 .lower_vote_eq_to_ballot = 1,
506 });
507
508 nir_lower_load_const_to_scalar(nir);
509
510 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
511 radv_optimize_nir(nir, false, true);
512
513 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
514 * to remove any copies introduced by nir_opt_find_array_copies().
515 */
516 nir_lower_var_copies(nir);
517
518 /* Lower deref operations for compute shared memory. */
519 if (nir->info.stage == MESA_SHADER_COMPUTE) {
520 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
521 nir_var_mem_shared, shared_var_info);
522 NIR_PASS_V(nir, nir_lower_explicit_io,
523 nir_var_mem_shared, nir_address_format_32bit_offset);
524 }
525
526 /* Lower large variables that are always constant with load_constant
527 * intrinsics, which get turned into PC-relative loads from a data
528 * section next to the shader.
529 */
530 NIR_PASS_V(nir, nir_opt_large_constants,
531 glsl_get_natural_size_align_bytes, 16);
532
533 /* Indirect lowering must be called after the radv_optimize_nir() loop
534 * has been called at least once. Otherwise indirect lowering can
535 * bloat the instruction count of the loop and cause it to be
536 * considered too large for unrolling.
537 */
538 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
539 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
540
541 return nir;
542 }
543
544 static int
545 type_size_vec4(const struct glsl_type *type, bool bindless)
546 {
547 return glsl_count_attribute_slots(type, false);
548 }
549
550 static nir_variable *
551 find_layer_in_var(nir_shader *nir)
552 {
553 nir_foreach_variable(var, &nir->inputs) {
554 if (var->data.location == VARYING_SLOT_LAYER) {
555 return var;
556 }
557 }
558
559 nir_variable *var =
560 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
561 var->data.location = VARYING_SLOT_LAYER;
562 var->data.interpolation = INTERP_MODE_FLAT;
563 return var;
564 }
565
566 /* We use layered rendering to implement multiview, which means we need to map
567 * view_index to gl_Layer. The attachment lowering also uses needs to know the
568 * layer so that it can sample from the correct layer. The code generates a
569 * load from the layer_id sysval, but since we don't have a way to get at this
570 * information from the fragment shader, we also need to lower this to the
571 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
572 * slot, before lowering io, so that nir_assign_var_locations() will give the
573 * LAYER varying the correct driver_location.
574 */
575
576 static bool
577 lower_view_index(nir_shader *nir)
578 {
579 bool progress = false;
580 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
581 nir_builder b;
582 nir_builder_init(&b, entry);
583
584 nir_variable *layer = NULL;
585 nir_foreach_block(block, entry) {
586 nir_foreach_instr_safe(instr, block) {
587 if (instr->type != nir_instr_type_intrinsic)
588 continue;
589
590 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
591 if (load->intrinsic != nir_intrinsic_load_view_index &&
592 load->intrinsic != nir_intrinsic_load_layer_id)
593 continue;
594
595 if (!layer)
596 layer = find_layer_in_var(nir);
597
598 b.cursor = nir_before_instr(instr);
599 nir_ssa_def *def = nir_load_var(&b, layer);
600 nir_ssa_def_rewrite_uses(&load->dest.ssa,
601 nir_src_for_ssa(def));
602
603 nir_instr_remove(instr);
604 progress = true;
605 }
606 }
607
608 return progress;
609 }
610
611 void
612 radv_lower_fs_io(nir_shader *nir)
613 {
614 NIR_PASS_V(nir, lower_view_index);
615 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
616 MESA_SHADER_FRAGMENT);
617
618 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
619
620 /* This pass needs actual constants */
621 nir_opt_constant_folding(nir);
622
623 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
624 }
625
626
627 void *
628 radv_alloc_shader_memory(struct radv_device *device,
629 struct radv_shader_variant *shader)
630 {
631 mtx_lock(&device->shader_slab_mutex);
632 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
633 uint64_t offset = 0;
634 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
635 if (s->bo_offset - offset >= shader->code_size) {
636 shader->bo = slab->bo;
637 shader->bo_offset = offset;
638 list_addtail(&shader->slab_list, &s->slab_list);
639 mtx_unlock(&device->shader_slab_mutex);
640 return slab->ptr + offset;
641 }
642 offset = align_u64(s->bo_offset + s->code_size, 256);
643 }
644 if (slab->size - offset >= shader->code_size) {
645 shader->bo = slab->bo;
646 shader->bo_offset = offset;
647 list_addtail(&shader->slab_list, &slab->shaders);
648 mtx_unlock(&device->shader_slab_mutex);
649 return slab->ptr + offset;
650 }
651 }
652
653 mtx_unlock(&device->shader_slab_mutex);
654 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
655
656 slab->size = 256 * 1024;
657 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
658 RADEON_DOMAIN_VRAM,
659 RADEON_FLAG_NO_INTERPROCESS_SHARING |
660 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
661 0 : RADEON_FLAG_READ_ONLY),
662 RADV_BO_PRIORITY_SHADER);
663 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
664 list_inithead(&slab->shaders);
665
666 mtx_lock(&device->shader_slab_mutex);
667 list_add(&slab->slabs, &device->shader_slabs);
668
669 shader->bo = slab->bo;
670 shader->bo_offset = 0;
671 list_add(&shader->slab_list, &slab->shaders);
672 mtx_unlock(&device->shader_slab_mutex);
673 return slab->ptr;
674 }
675
676 void
677 radv_destroy_shader_slabs(struct radv_device *device)
678 {
679 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
680 device->ws->buffer_destroy(slab->bo);
681 free(slab);
682 }
683 mtx_destroy(&device->shader_slab_mutex);
684 }
685
686 /* For the UMR disassembler. */
687 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
688 #define DEBUGGER_NUM_MARKERS 5
689
690 static unsigned
691 radv_get_shader_binary_size(size_t code_size)
692 {
693 return code_size + DEBUGGER_NUM_MARKERS * 4;
694 }
695
696 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
697 const struct ac_shader_config *config_in,
698 const struct radv_shader_info *info,
699 gl_shader_stage stage,
700 struct ac_shader_config *config_out)
701 {
702 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
703 unsigned vgpr_comp_cnt = 0;
704 unsigned num_input_vgprs = info->num_input_vgprs;
705
706 if (stage == MESA_SHADER_FRAGMENT) {
707 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
708 }
709
710 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
711 /* +3 for scratch wave offset and VCC */
712 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
713 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
714 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
715 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
716 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
717 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
718
719 *config_out = *config_in;
720 config_out->num_vgprs = num_vgprs;
721 config_out->num_sgprs = num_sgprs;
722 config_out->num_shared_vgprs = num_shared_vgprs;
723
724 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
725 S_00B12C_SCRATCH_EN(scratch_enabled);
726
727 if (!pdevice->use_ngg_streamout) {
728 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
729 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
730 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
731 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
732 S_00B12C_SO_EN(!!info->so.num_outputs);
733 }
734
735 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
736 (info->wave_size == 32 ? 8 : 4)) |
737 S_00B848_DX10_CLAMP(1) |
738 S_00B848_FLOAT_MODE(config_out->float_mode);
739
740 if (pdevice->rad_info.chip_class >= GFX10) {
741 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
742 } else {
743 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
744 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
745 }
746
747 switch (stage) {
748 case MESA_SHADER_TESS_EVAL:
749 if (info->is_ngg) {
750 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
751 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
752 } else if (info->tes.as_es) {
753 assert(pdevice->rad_info.chip_class <= GFX8);
754 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
755
756 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
757 } else {
758 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
759 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
760
761 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
762 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
763 }
764 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
765 break;
766 case MESA_SHADER_TESS_CTRL:
767 if (pdevice->rad_info.chip_class >= GFX9) {
768 /* We need at least 2 components for LS.
769 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
770 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
771 */
772 if (pdevice->rad_info.chip_class >= GFX10) {
773 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
774 } else {
775 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
776 }
777 } else {
778 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
779 }
780 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
781 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
782 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
783 break;
784 case MESA_SHADER_VERTEX:
785 if (info->is_ngg) {
786 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
787 } else if (info->vs.as_ls) {
788 assert(pdevice->rad_info.chip_class <= GFX8);
789 /* We need at least 2 components for LS.
790 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
791 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
792 */
793 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
794 } else if (info->vs.as_es) {
795 assert(pdevice->rad_info.chip_class <= GFX8);
796 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
797 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
798 } else {
799 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
800 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
801 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
802 */
803 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
804 vgpr_comp_cnt = 3;
805 } else if (info->vs.export_prim_id) {
806 vgpr_comp_cnt = 2;
807 } else if (info->vs.needs_instance_id) {
808 vgpr_comp_cnt = 1;
809 } else {
810 vgpr_comp_cnt = 0;
811 }
812
813 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
814 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
815 }
816 break;
817 case MESA_SHADER_FRAGMENT:
818 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
819 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
820 break;
821 case MESA_SHADER_GEOMETRY:
822 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
823 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
824 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
825 break;
826 case MESA_SHADER_COMPUTE:
827 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
828 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
829 config_out->rsrc2 |=
830 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
831 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
832 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
833 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
834 info->cs.uses_thread_id[1] ? 1 : 0) |
835 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
836 S_00B84C_LDS_SIZE(config_in->lds_size);
837 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
838
839 break;
840 default:
841 unreachable("unsupported shader type");
842 break;
843 }
844
845 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
846 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
847 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
848 gl_shader_stage es_stage = stage;
849 if (stage == MESA_SHADER_GEOMETRY)
850 es_stage = info->gs.es_type;
851
852 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
853 if (es_stage == MESA_SHADER_VERTEX) {
854 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
855 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
856 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
857 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
858 } else
859 unreachable("Unexpected ES shader stage");
860
861 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
862 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
863 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
864 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
865 } else if (info->uses_prim_id) {
866 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
867 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
868 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
869 } else {
870 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
871 }
872
873 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
874 S_00B228_WGP_MODE(1);
875 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
876 S_00B22C_LDS_SIZE(config_in->lds_size) |
877 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
878 } else if (pdevice->rad_info.chip_class >= GFX9 &&
879 stage == MESA_SHADER_GEOMETRY) {
880 unsigned es_type = info->gs.es_type;
881 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
882
883 if (es_type == MESA_SHADER_VERTEX) {
884 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
885 if (info->vs.needs_instance_id) {
886 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
887 } else {
888 es_vgpr_comp_cnt = 0;
889 }
890 } else if (es_type == MESA_SHADER_TESS_EVAL) {
891 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
892 } else {
893 unreachable("invalid shader ES type");
894 }
895
896 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
897 * VGPR[0:4] are always loaded.
898 */
899 if (info->uses_invocation_id) {
900 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
901 } else if (info->uses_prim_id) {
902 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
903 } else if (info->gs.vertices_in >= 3) {
904 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
905 } else {
906 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
907 }
908
909 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
910 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
911 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
912 } else if (pdevice->rad_info.chip_class >= GFX9 &&
913 stage == MESA_SHADER_TESS_CTRL) {
914 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
915 } else {
916 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
917 }
918 }
919
920 struct radv_shader_variant *
921 radv_shader_variant_create(struct radv_device *device,
922 const struct radv_shader_binary *binary,
923 bool keep_shader_info)
924 {
925 struct ac_shader_config config = {0};
926 struct ac_rtld_binary rtld_binary = {0};
927 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
928 if (!variant)
929 return NULL;
930
931 variant->ref_count = 1;
932
933 if (binary->type == RADV_BINARY_TYPE_RTLD) {
934 struct ac_rtld_symbol lds_symbols[2];
935 unsigned num_lds_symbols = 0;
936 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
937 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
938
939 if (device->physical_device->rad_info.chip_class >= GFX9 &&
940 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
941 !binary->is_gs_copy_shader) {
942 /* We add this symbol even on LLVM <= 8 to ensure that
943 * shader->config.lds_size is set correctly below.
944 */
945 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
946 sym->name = "esgs_ring";
947 sym->size = binary->info.ngg_info.esgs_ring_size;
948 sym->align = 64 * 1024;
949 }
950
951 if (binary->info.is_ngg &&
952 binary->stage == MESA_SHADER_GEOMETRY) {
953 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
954 sym->name = "ngg_emit";
955 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
956 sym->align = 4;
957 }
958
959 struct ac_rtld_open_info open_info = {
960 .info = &device->physical_device->rad_info,
961 .shader_type = binary->stage,
962 .wave_size = binary->info.wave_size,
963 .num_parts = 1,
964 .elf_ptrs = &elf_data,
965 .elf_sizes = &elf_size,
966 .num_shared_lds_symbols = num_lds_symbols,
967 .shared_lds_symbols = lds_symbols,
968 };
969
970 if (!ac_rtld_open(&rtld_binary, open_info)) {
971 free(variant);
972 return NULL;
973 }
974
975 if (!ac_rtld_read_config(&rtld_binary, &config)) {
976 ac_rtld_close(&rtld_binary);
977 free(variant);
978 return NULL;
979 }
980
981 /* Enable 64-bit and 16-bit denormals, because there is no performance
982 * cost.
983 *
984 * If denormals are enabled, all floating-point output modifiers are
985 * ignored.
986 *
987 * Don't enable denormals for 32-bit floats, because:
988 * - Floating-point output modifiers would be ignored by the hw.
989 * - Some opcodes don't support denormals, such as v_mad_f32. We would
990 * have to stop using those.
991 * - GFX6 & GFX7 would be very slow.
992 */
993 config.float_mode |= V_00B028_FP_64_DENORMS;
994
995 if (rtld_binary.lds_size > 0) {
996 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
997 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
998 }
999
1000 variant->code_size = rtld_binary.rx_size;
1001 variant->exec_size = rtld_binary.exec_size;
1002 } else {
1003 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1004 config = ((struct radv_shader_binary_legacy *)binary)->config;
1005 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1006 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1007 }
1008
1009 variant->info = binary->info;
1010 radv_postprocess_config(device->physical_device, &config, &binary->info,
1011 binary->stage, &variant->config);
1012
1013 if (radv_device_use_secure_compile(device->instance)) {
1014 if (binary->type == RADV_BINARY_TYPE_RTLD)
1015 ac_rtld_close(&rtld_binary);
1016
1017 return variant;
1018 }
1019
1020 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1021
1022 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1023 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1024 struct ac_rtld_upload_info info = {
1025 .binary = &rtld_binary,
1026 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1027 .rx_ptr = dest_ptr,
1028 };
1029
1030 if (!ac_rtld_upload(&info)) {
1031 radv_shader_variant_destroy(device, variant);
1032 ac_rtld_close(&rtld_binary);
1033 return NULL;
1034 }
1035
1036 if (keep_shader_info ||
1037 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1038 const char *disasm_data;
1039 size_t disasm_size;
1040 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1041 radv_shader_variant_destroy(device, variant);
1042 ac_rtld_close(&rtld_binary);
1043 return NULL;
1044 }
1045
1046 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1047 variant->disasm_string = malloc(disasm_size + 1);
1048 memcpy(variant->disasm_string, disasm_data, disasm_size);
1049 variant->disasm_string[disasm_size] = 0;
1050 }
1051
1052 ac_rtld_close(&rtld_binary);
1053 } else {
1054 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1055 memcpy(dest_ptr, bin->data, bin->code_size);
1056
1057 /* Add end-of-code markers for the UMR disassembler. */
1058 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1059 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1060 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1061
1062 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
1063 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL;
1064 }
1065 return variant;
1066 }
1067
1068 static char *
1069 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1070 int shader_count)
1071 {
1072 char *data = NULL;
1073 char *ret = NULL;
1074 size_t size = 0;
1075 FILE *f = open_memstream(&data, &size);
1076 if (f) {
1077 for (int i = 0; i < shader_count; ++i)
1078 nir_print_shader(shaders[i], f);
1079 fclose(f);
1080 }
1081
1082 ret = malloc(size + 1);
1083 if (ret) {
1084 memcpy(ret, data, size);
1085 ret[size] = 0;
1086 }
1087 free(data);
1088 return ret;
1089 }
1090
1091 static struct radv_shader_variant *
1092 shader_variant_compile(struct radv_device *device,
1093 struct radv_shader_module *module,
1094 struct nir_shader * const *shaders,
1095 int shader_count,
1096 gl_shader_stage stage,
1097 struct radv_shader_info *info,
1098 struct radv_nir_compiler_options *options,
1099 bool gs_copy_shader,
1100 bool keep_shader_info,
1101 bool use_aco,
1102 struct radv_shader_binary **binary_out)
1103 {
1104 enum radeon_family chip_family = device->physical_device->rad_info.family;
1105 struct radv_shader_binary *binary = NULL;
1106
1107 options->family = chip_family;
1108 options->chip_class = device->physical_device->rad_info.chip_class;
1109 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1110 options->dump_preoptir = options->dump_shader &&
1111 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1112 options->record_ir = keep_shader_info;
1113 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1114 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1115 options->address32_hi = device->physical_device->rad_info.address32_hi;
1116 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1117 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1118
1119 struct radv_shader_args args = {};
1120 args.options = options;
1121 args.shader_info = info;
1122 args.is_gs_copy_shader = gs_copy_shader;
1123 radv_declare_shader_args(&args,
1124 gs_copy_shader ? MESA_SHADER_VERTEX
1125 : shaders[shader_count - 1]->info.stage,
1126 shader_count >= 2,
1127 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1128 : MESA_SHADER_VERTEX);
1129
1130 if (!use_aco || options->dump_shader || options->record_ir)
1131 ac_init_llvm_once();
1132
1133 if (use_aco) {
1134 aco_compile_shader(shader_count, shaders, &binary, &args);
1135 binary->info = *info;
1136 } else {
1137 enum ac_target_machine_options tm_options = 0;
1138 struct ac_llvm_compiler ac_llvm;
1139 bool thread_compiler;
1140
1141 tm_options |= AC_TM_SUPPORTS_SPILL;
1142 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
1143 tm_options |= AC_TM_SISCHED;
1144 if (options->check_ir)
1145 tm_options |= AC_TM_CHECK_IR;
1146 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
1147 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
1148
1149 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
1150 radv_init_llvm_compiler(&ac_llvm,
1151 thread_compiler,
1152 chip_family, tm_options,
1153 info->wave_size);
1154
1155 if (gs_copy_shader) {
1156 assert(shader_count == 1);
1157 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
1158 &args);
1159 } else {
1160 radv_compile_nir_shader(&ac_llvm, &binary, &args,
1161 shaders, shader_count);
1162 }
1163
1164 binary->info = *info;
1165 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
1166 }
1167
1168 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1169 keep_shader_info);
1170 if (!variant) {
1171 free(binary);
1172 return NULL;
1173 }
1174 variant->aco_used = use_aco;
1175
1176 if (options->dump_shader) {
1177 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
1178 }
1179
1180
1181 if (keep_shader_info) {
1182 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1183 if (!gs_copy_shader && !module->nir) {
1184 variant->spirv = malloc(module->size);
1185 if (!variant->spirv) {
1186 free(variant);
1187 free(binary);
1188 return NULL;
1189 }
1190
1191 memcpy(variant->spirv, module->data, module->size);
1192 variant->spirv_size = module->size;
1193 }
1194 }
1195
1196 if (binary_out)
1197 *binary_out = binary;
1198 else
1199 free(binary);
1200
1201 return variant;
1202 }
1203
1204 struct radv_shader_variant *
1205 radv_shader_variant_compile(struct radv_device *device,
1206 struct radv_shader_module *module,
1207 struct nir_shader *const *shaders,
1208 int shader_count,
1209 struct radv_pipeline_layout *layout,
1210 const struct radv_shader_variant_key *key,
1211 struct radv_shader_info *info,
1212 bool keep_shader_info,
1213 bool use_aco,
1214 struct radv_shader_binary **binary_out)
1215 {
1216 struct radv_nir_compiler_options options = {0};
1217
1218 options.layout = layout;
1219 if (key)
1220 options.key = *key;
1221
1222 options.explicit_scratch_args = use_aco;
1223 options.robust_buffer_access = device->robust_buffer_access;
1224
1225 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1226 &options, false, keep_shader_info, use_aco, binary_out);
1227 }
1228
1229 struct radv_shader_variant *
1230 radv_create_gs_copy_shader(struct radv_device *device,
1231 struct nir_shader *shader,
1232 struct radv_shader_info *info,
1233 struct radv_shader_binary **binary_out,
1234 bool keep_shader_info,
1235 bool multiview)
1236 {
1237 struct radv_nir_compiler_options options = {0};
1238
1239 options.key.has_multiview_view_index = multiview;
1240
1241 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1242 info, &options, true, keep_shader_info, false, binary_out);
1243 }
1244
1245 void
1246 radv_shader_variant_destroy(struct radv_device *device,
1247 struct radv_shader_variant *variant)
1248 {
1249 if (!p_atomic_dec_zero(&variant->ref_count))
1250 return;
1251
1252 mtx_lock(&device->shader_slab_mutex);
1253 list_del(&variant->slab_list);
1254 mtx_unlock(&device->shader_slab_mutex);
1255
1256 free(variant->spirv);
1257 free(variant->nir_string);
1258 free(variant->disasm_string);
1259 free(variant->ir_string);
1260 free(variant);
1261 }
1262
1263 const char *
1264 radv_get_shader_name(struct radv_shader_info *info,
1265 gl_shader_stage stage)
1266 {
1267 switch (stage) {
1268 case MESA_SHADER_VERTEX:
1269 if (info->vs.as_ls)
1270 return "Vertex Shader as LS";
1271 else if (info->vs.as_es)
1272 return "Vertex Shader as ES";
1273 else if (info->is_ngg)
1274 return "Vertex Shader as ESGS";
1275 else
1276 return "Vertex Shader as VS";
1277 case MESA_SHADER_TESS_CTRL:
1278 return "Tessellation Control Shader";
1279 case MESA_SHADER_TESS_EVAL:
1280 if (info->tes.as_es)
1281 return "Tessellation Evaluation Shader as ES";
1282 else if (info->is_ngg)
1283 return "Tessellation Evaluation Shader as ESGS";
1284 else
1285 return "Tessellation Evaluation Shader as VS";
1286 case MESA_SHADER_GEOMETRY:
1287 return "Geometry Shader";
1288 case MESA_SHADER_FRAGMENT:
1289 return "Pixel Shader";
1290 case MESA_SHADER_COMPUTE:
1291 return "Compute Shader";
1292 default:
1293 return "Unknown shader";
1294 };
1295 }
1296
1297 unsigned
1298 radv_get_max_workgroup_size(enum chip_class chip_class,
1299 gl_shader_stage stage,
1300 const unsigned *sizes)
1301 {
1302 switch (stage) {
1303 case MESA_SHADER_TESS_CTRL:
1304 return chip_class >= GFX7 ? 128 : 64;
1305 case MESA_SHADER_GEOMETRY:
1306 return chip_class >= GFX9 ? 128 : 64;
1307 case MESA_SHADER_COMPUTE:
1308 break;
1309 default:
1310 return 0;
1311 }
1312
1313 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1314 return max_workgroup_size;
1315 }
1316
1317 unsigned
1318 radv_get_max_waves(struct radv_device *device,
1319 struct radv_shader_variant *variant,
1320 gl_shader_stage stage)
1321 {
1322 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1323 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1324 uint8_t wave_size = variant->info.wave_size;
1325 struct ac_shader_config *conf = &variant->config;
1326 unsigned max_simd_waves;
1327 unsigned lds_per_wave = 0;
1328
1329 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1330
1331 if (stage == MESA_SHADER_FRAGMENT) {
1332 lds_per_wave = conf->lds_size * lds_increment +
1333 align(variant->info.ps.num_interp * 48,
1334 lds_increment);
1335 } else if (stage == MESA_SHADER_COMPUTE) {
1336 unsigned max_workgroup_size =
1337 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1338 lds_per_wave = (conf->lds_size * lds_increment) /
1339 DIV_ROUND_UP(max_workgroup_size, wave_size);
1340 }
1341
1342 if (conf->num_sgprs) {
1343 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1344 max_simd_waves =
1345 MIN2(max_simd_waves,
1346 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1347 sgprs);
1348 }
1349
1350 if (conf->num_vgprs) {
1351 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1352 max_simd_waves =
1353 MIN2(max_simd_waves,
1354 RADV_NUM_PHYSICAL_VGPRS / vgprs);
1355 }
1356
1357 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1358 * that PS can use.
1359 */
1360 if (lds_per_wave)
1361 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1362
1363 return max_simd_waves;
1364 }
1365
1366 static void
1367 generate_shader_stats(struct radv_device *device,
1368 struct radv_shader_variant *variant,
1369 gl_shader_stage stage,
1370 struct _mesa_string_buffer *buf)
1371 {
1372 struct ac_shader_config *conf = &variant->config;
1373 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1374
1375 if (stage == MESA_SHADER_FRAGMENT) {
1376 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1377 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1378 "SPI_PS_INPUT_ENA = 0x%04x\n",
1379 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1380 }
1381
1382 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1383 "SGPRS: %d\n"
1384 "VGPRS: %d\n"
1385 "Spilled SGPRs: %d\n"
1386 "Spilled VGPRs: %d\n"
1387 "PrivMem VGPRS: %d\n"
1388 "Code Size: %d bytes\n"
1389 "LDS: %d blocks\n"
1390 "Scratch: %d bytes per wave\n"
1391 "Max Waves: %d\n"
1392 "********************\n\n\n",
1393 conf->num_sgprs, conf->num_vgprs,
1394 conf->spilled_sgprs, conf->spilled_vgprs,
1395 variant->info.private_mem_vgprs, variant->exec_size,
1396 conf->lds_size, conf->scratch_bytes_per_wave,
1397 max_simd_waves);
1398 }
1399
1400 void
1401 radv_shader_dump_stats(struct radv_device *device,
1402 struct radv_shader_variant *variant,
1403 gl_shader_stage stage,
1404 FILE *file)
1405 {
1406 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1407
1408 generate_shader_stats(device, variant, stage, buf);
1409
1410 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1411 fprintf(file, "%s", buf->buf);
1412
1413 _mesa_string_buffer_destroy(buf);
1414 }
1415
1416 VkResult
1417 radv_GetShaderInfoAMD(VkDevice _device,
1418 VkPipeline _pipeline,
1419 VkShaderStageFlagBits shaderStage,
1420 VkShaderInfoTypeAMD infoType,
1421 size_t* pInfoSize,
1422 void* pInfo)
1423 {
1424 RADV_FROM_HANDLE(radv_device, device, _device);
1425 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1426 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1427 struct radv_shader_variant *variant = pipeline->shaders[stage];
1428 struct _mesa_string_buffer *buf;
1429 VkResult result = VK_SUCCESS;
1430
1431 /* Spec doesn't indicate what to do if the stage is invalid, so just
1432 * return no info for this. */
1433 if (!variant)
1434 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1435
1436 switch (infoType) {
1437 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1438 if (!pInfo) {
1439 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1440 } else {
1441 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1442 struct ac_shader_config *conf = &variant->config;
1443
1444 VkShaderStatisticsInfoAMD statistics = {};
1445 statistics.shaderStageMask = shaderStage;
1446 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1447 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1448 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1449
1450 if (stage == MESA_SHADER_COMPUTE) {
1451 unsigned *local_size = variant->info.cs.block_size;
1452 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1453
1454 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1455 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1456
1457 statistics.computeWorkGroupSize[0] = local_size[0];
1458 statistics.computeWorkGroupSize[1] = local_size[1];
1459 statistics.computeWorkGroupSize[2] = local_size[2];
1460 } else {
1461 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1462 }
1463
1464 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1465 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1466 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1467 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1468 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1469
1470 size_t size = *pInfoSize;
1471 *pInfoSize = sizeof(statistics);
1472
1473 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1474
1475 if (size < *pInfoSize)
1476 result = VK_INCOMPLETE;
1477 }
1478
1479 break;
1480 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1481 buf = _mesa_string_buffer_create(NULL, 1024);
1482
1483 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1484 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1485 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1486 generate_shader_stats(device, variant, stage, buf);
1487
1488 /* Need to include the null terminator. */
1489 size_t length = buf->length + 1;
1490
1491 if (!pInfo) {
1492 *pInfoSize = length;
1493 } else {
1494 size_t size = *pInfoSize;
1495 *pInfoSize = length;
1496
1497 memcpy(pInfo, buf->buf, MIN2(size, length));
1498
1499 if (size < length)
1500 result = VK_INCOMPLETE;
1501 }
1502
1503 _mesa_string_buffer_destroy(buf);
1504 break;
1505 default:
1506 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1507 result = VK_ERROR_FEATURE_NOT_PRESENT;
1508 break;
1509 }
1510
1511 return result;
1512 }