src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "radv_shader_helper.h"
  34 #include "nir/nir.h"
  35 #include "nir/nir_builder.h"
  36 #include "spirv/nir_spirv.h"
  37
  38 #include <llvm-c/Core.h>
  39 #include <llvm-c/TargetMachine.h>
  40 #include <llvm-c/Support.h>
  41
  42 #include "sid.h"
  43 #include "ac_binary.h"
  44 #include "ac_llvm_util.h"
  45 #include "ac_nir_to_llvm.h"
  46 #include "vk_format.h"
  47 #include "util/debug.h"
  48 #include "ac_exp_param.h"
  49
  50 #include "util/string_buffer.h"
  51
  52 static const struct nir_shader_compiler_options nir_options = {
  53         .vertex_id_zero_based = true,
  54         .lower_scmp = true,
  55         .lower_flrp16 = true,
  56         .lower_flrp32 = true,
  57         .lower_flrp64 = true,
  58         .lower_device_index_to_zero = true,
  59         .lower_fsat = true,
  60         .lower_fdiv = true,
  61         .lower_sub = true,
  62         .lower_pack_snorm_2x16 = true,
  63         .lower_pack_snorm_4x8 = true,
  64         .lower_pack_unorm_2x16 = true,
  65         .lower_pack_unorm_4x8 = true,
  66         .lower_unpack_snorm_2x16 = true,
  67         .lower_unpack_snorm_4x8 = true,
  68         .lower_unpack_unorm_2x16 = true,
  69         .lower_unpack_unorm_4x8 = true,
  70         .lower_extract_byte = true,
  71         .lower_extract_word = true,
  72         .lower_ffma = true,
  73         .lower_fpow = true,
  74         .lower_mul_2x32_64 = true,
  75         .max_unroll_iterations = 32
  76 };
  77
  78 VkResult radv_CreateShaderModule(
  79         VkDevice                                    _device,
  80         const VkShaderModuleCreateInfo*             pCreateInfo,
  81         const VkAllocationCallbacks*                pAllocator,
  82         VkShaderModule*                             pShaderModule)
  83 {
  84         RADV_FROM_HANDLE(radv_device, device, _device);
  85         struct radv_shader_module *module;
  86
  87         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  88         assert(pCreateInfo->flags == 0);
  89
  90         module = vk_alloc2(&device->alloc, pAllocator,
  91                              sizeof(*module) + pCreateInfo->codeSize, 8,
  92                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  93         if (module == NULL)
  94                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
  95
  96         module->nir = NULL;
  97         module->size = pCreateInfo->codeSize;
  98         memcpy(module->data, pCreateInfo->pCode, module->size);
  99
 100         _mesa_sha1_compute(module->data, module->size, module->sha1);
 101
 102         *pShaderModule = radv_shader_module_to_handle(module);
 103
 104         return VK_SUCCESS;
 105 }
 106
 107 void radv_DestroyShaderModule(
 108         VkDevice                                    _device,
 109         VkShaderModule                              _module,
 110         const VkAllocationCallbacks*                pAllocator)
 111 {
 112         RADV_FROM_HANDLE(radv_device, device, _device);
 113         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 114
 115         if (!module)
 116                 return;
 117
 118         vk_free2(&device->alloc, pAllocator, module);
 119 }
 120
 121 void
 122 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 123                   bool allow_copies)
 124 {
 125         bool progress;
 126         unsigned lower_flrp =
 127                 (shader->options->lower_flrp16 ? 16 : 0) |
 128                 (shader->options->lower_flrp32 ? 32 : 0) |
 129                 (shader->options->lower_flrp64 ? 64 : 0);
 130
 131         do {
 132                 progress = false;
 133
 134                 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
 135                 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
 136
 137                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 138                 NIR_PASS_V(shader, nir_lower_pack);
 139
 140                 if (allow_copies) {
 141                         /* Only run this pass in the first call to
 142                          * radv_optimize_nir.  Later calls assume that we've
 143                          * lowered away any copy_deref instructions and we
 144                          *  don't want to introduce any more.
 145                         */
 146                         NIR_PASS(progress, shader, nir_opt_find_array_copies);
 147                 }
 148
 149                 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
 150                 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
 151
 152                 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL);
 153                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 154
 155                 NIR_PASS(progress, shader, nir_copy_prop);
 156                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 157                 NIR_PASS(progress, shader, nir_opt_dce);
 158                 if (nir_opt_trivial_continues(shader)) {
 159                         progress = true;
 160                         NIR_PASS(progress, shader, nir_copy_prop);
 161                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 162                         NIR_PASS(progress, shader, nir_opt_dce);
 163                 }
 164                 NIR_PASS(progress, shader, nir_opt_if, true);
 165                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 166                 NIR_PASS(progress, shader, nir_opt_cse);
 167                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
 168                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 169                 NIR_PASS(progress, shader, nir_opt_algebraic);
 170
 171                 if (lower_flrp != 0) {
 172                         bool lower_flrp_progress = false;
 173                         NIR_PASS(lower_flrp_progress,
 174                                  shader,
 175                                  nir_lower_flrp,
 176                                  lower_flrp,
 177                                  false /* always_precise */,
 178                                  shader->options->lower_ffma);
 179                         if (lower_flrp_progress) {
 180                                 NIR_PASS(progress, shader,
 181                                          nir_opt_constant_folding);
 182                                 progress = true;
 183                         }
 184
 185                         /* Nothing should rematerialize any flrps, so we only
 186                          * need to do this lowering once.
 187                          */
 188                         lower_flrp = 0;
 189                 }
 190
 191                 NIR_PASS(progress, shader, nir_opt_undef);
 192                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 193                 if (shader->options->max_unroll_iterations) {
 194                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 195                 }
 196         } while (progress && !optimize_conservatively);
 197
 198         NIR_PASS(progress, shader, nir_opt_shrink_load);
 199         NIR_PASS(progress, shader, nir_opt_move_load_ubo);
 200 }
 201
 202 nir_shader *
 203 radv_shader_compile_to_nir(struct radv_device *device,
 204                            struct radv_shader_module *module,
 205                            const char *entrypoint_name,
 206                            gl_shader_stage stage,
 207                            const VkSpecializationInfo *spec_info,
 208                            const VkPipelineCreateFlags flags,
 209                            const struct radv_pipeline_layout *layout)
 210 {
 211         nir_shader *nir;
 212         if (module->nir) {
 213                 /* Some things such as our meta clear/blit code will give us a NIR
 214                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 215                  * and just use the NIR shader */
 216                 nir = module->nir;
 217                 nir->options = &nir_options;
 218                 nir_validate_shader(nir, "in internal shader");
 219
 220                 assert(exec_list_length(&nir->functions) == 1);
 221         } else {
 222                 uint32_t *spirv = (uint32_t *) module->data;
 223                 assert(module->size % 4 == 0);
 224
 225                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 226                         radv_print_spirv(spirv, module->size, stderr);
 227
 228                 uint32_t num_spec_entries = 0;
 229                 struct nir_spirv_specialization *spec_entries = NULL;
 230                 if (spec_info && spec_info->mapEntryCount > 0) {
 231                         num_spec_entries = spec_info->mapEntryCount;
 232                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 233                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 234                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 235                                 const void *data = spec_info->pData + entry.offset;
 236                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 237
 238                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 239                                 if (spec_info->dataSize == 8)
 240                                         spec_entries[i].data64 = *(const uint64_t *)data;
 241                                 else
 242                                         spec_entries[i].data32 = *(const uint32_t *)data;
 243                         }
 244                 }
 245                 const struct spirv_to_nir_options spirv_options = {
 246                         .lower_ubo_ssbo_access_to_offsets = true,
 247                         .caps = {
 248                                 .derivative_group = true,
 249                                 .descriptor_array_dynamic_indexing = true,
 250                                 .descriptor_array_non_uniform_indexing = true,
 251                                 .descriptor_indexing = true,
 252                                 .device_group = true,
 253                                 .draw_parameters = true,
 254                                 .float16 = true,
 255                                 .float64 = true,
 256                                 .gcn_shader = true,
 257                                 .geometry_streams = true,
 258                                 .image_read_without_format = true,
 259                                 .image_write_without_format = true,
 260                                 .int8 = true,
 261                                 .int16 = true,
 262                                 .int64 = true,
 263                                 .int64_atomics = true,
 264                                 .multiview = true,
 265                                 .physical_storage_buffer_address = true,
 266                                 .runtime_descriptor_array = true,
 267                                 .shader_viewport_index_layer = true,
 268                                 .stencil_export = true,
 269                                 .storage_8bit = true,
 270                                 .storage_16bit = true,
 271                                 .storage_image_ms = true,
 272                                 .subgroup_arithmetic = true,
 273                                 .subgroup_ballot = true,
 274                                 .subgroup_basic = true,
 275                                 .subgroup_quad = true,
 276                                 .subgroup_shuffle = true,
 277                                 .subgroup_vote = true,
 278                                 .tessellation = true,
 279                                 .transform_feedback = true,
 280                                 .trinary_minmax = true,
 281                                 .variable_pointers = true,
 282                         },
 283                         .ubo_addr_format = nir_address_format_32bit_index_offset,
 284                         .ssbo_addr_format = nir_address_format_32bit_index_offset,
 285                         .phys_ssbo_addr_format = nir_address_format_64bit_global,
 286                         .push_const_addr_format = nir_address_format_logical,
 287                         .shared_addr_format = nir_address_format_32bit_offset,
 288                 };
 289                 nir = spirv_to_nir(spirv, module->size / 4,
 290                                    spec_entries, num_spec_entries,
 291                                    stage, entrypoint_name,
 292                                    &spirv_options, &nir_options);
 293                 assert(nir->info.stage == stage);
 294                 nir_validate_shader(nir, "after spirv_to_nir");
 295
 296                 free(spec_entries);
 297
 298                 /* We have to lower away local constant initializers right before we
 299                  * inline functions.  That way they get properly initialized at the top
 300                  * of the function and not at the top of its caller.
 301                  */
 302                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
 303                 NIR_PASS_V(nir, nir_lower_returns);
 304                 NIR_PASS_V(nir, nir_inline_functions);
 305                 NIR_PASS_V(nir, nir_opt_deref);
 306
 307                 /* Pick off the single entrypoint that we want */
 308                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 309                         if (func->is_entrypoint)
 310                                 func->name = ralloc_strdup(func, "main");
 311                         else
 312                                 exec_node_remove(&func->node);
 313                 }
 314                 assert(exec_list_length(&nir->functions) == 1);
 315
 316                 /* Make sure we lower constant initializers on output variables so that
 317                  * nir_remove_dead_variables below sees the corresponding stores
 318                  */
 319                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
 320
 321                 /* Now that we've deleted all but the main function, we can go ahead and
 322                  * lower the rest of the constant initializers.
 323                  */
 324                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 325
 326                 /* Split member structs.  We do this before lower_io_to_temporaries so that
 327                  * it doesn't lower system values to temporaries by accident.
 328                  */
 329                 NIR_PASS_V(nir, nir_split_var_copies);
 330                 NIR_PASS_V(nir, nir_split_per_member_structs);
 331
 332                 NIR_PASS_V(nir, nir_remove_dead_variables,
 333                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 334
 335                 NIR_PASS_V(nir, nir_lower_system_values);
 336                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 337                 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
 338         }
 339
 340         /* Vulkan uses the separate-shader linking model */
 341         nir->info.separate_shader = true;
 342
 343         nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 344
 345         static const nir_lower_tex_options tex_options = {
 346           .lower_txp = ~0,
 347           .lower_tg4_offsets = true,
 348         };
 349
 350         nir_lower_tex(nir, &tex_options);
 351
 352         nir_lower_vars_to_ssa(nir);
 353
 354         if (nir->info.stage == MESA_SHADER_VERTEX ||
 355             nir->info.stage == MESA_SHADER_GEOMETRY) {
 356                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 357                            nir_shader_get_entrypoint(nir), true, true);
 358         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
 359                    nir->info.stage == MESA_SHADER_FRAGMENT) {
 360                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 361                            nir_shader_get_entrypoint(nir), true, false);
 362         }
 363
 364         nir_split_var_copies(nir);
 365
 366         nir_lower_global_vars_to_local(nir);
 367         nir_remove_dead_variables(nir, nir_var_function_temp);
 368         nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 369                         .subgroup_size = 64,
 370                         .ballot_bit_size = 64,
 371                         .lower_to_scalar = 1,
 372                         .lower_subgroup_masks = 1,
 373                         .lower_shuffle = 1,
 374                         .lower_shuffle_to_32bit = 1,
 375                         .lower_vote_eq_to_ballot = 1,
 376                 });
 377
 378         nir_lower_load_const_to_scalar(nir);
 379
 380         if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
 381                 radv_optimize_nir(nir, false, true);
 382
 383         /* We call nir_lower_var_copies() after the first radv_optimize_nir()
 384          * to remove any copies introduced by nir_opt_find_array_copies().
 385          */
 386         nir_lower_var_copies(nir);
 387
 388         /* Indirect lowering must be called after the radv_optimize_nir() loop
 389          * has been called at least once. Otherwise indirect lowering can
 390          * bloat the instruction count of the loop and cause it to be
 391          * considered too large for unrolling.
 392          */
 393         ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
 394         radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
 395
 396         return nir;
 397 }
 398
 399 void *
 400 radv_alloc_shader_memory(struct radv_device *device,
 401                          struct radv_shader_variant *shader)
 402 {
 403         mtx_lock(&device->shader_slab_mutex);
 404         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 405                 uint64_t offset = 0;
 406                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 407                         if (s->bo_offset - offset >= shader->code_size) {
 408                                 shader->bo = slab->bo;
 409                                 shader->bo_offset = offset;
 410                                 list_addtail(&shader->slab_list, &s->slab_list);
 411                                 mtx_unlock(&device->shader_slab_mutex);
 412                                 return slab->ptr + offset;
 413                         }
 414                         offset = align_u64(s->bo_offset + s->code_size, 256);
 415                 }
 416                 if (slab->size - offset >= shader->code_size) {
 417                         shader->bo = slab->bo;
 418                         shader->bo_offset = offset;
 419                         list_addtail(&shader->slab_list, &slab->shaders);
 420                         mtx_unlock(&device->shader_slab_mutex);
 421                         return slab->ptr + offset;
 422                 }
 423         }
 424
 425         mtx_unlock(&device->shader_slab_mutex);
 426         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 427
 428         slab->size = 256 * 1024;
 429         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 430                                              RADEON_DOMAIN_VRAM,
 431                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 432                                              (device->physical_device->cpdma_prefetch_writes_memory ?
 433                                                      0 : RADEON_FLAG_READ_ONLY),
 434                                              RADV_BO_PRIORITY_SHADER);
 435         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 436         list_inithead(&slab->shaders);
 437
 438         mtx_lock(&device->shader_slab_mutex);
 439         list_add(&slab->slabs, &device->shader_slabs);
 440
 441         shader->bo = slab->bo;
 442         shader->bo_offset = 0;
 443         list_add(&shader->slab_list, &slab->shaders);
 444         mtx_unlock(&device->shader_slab_mutex);
 445         return slab->ptr;
 446 }
 447
 448 void
 449 radv_destroy_shader_slabs(struct radv_device *device)
 450 {
 451         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 452                 device->ws->buffer_destroy(slab->bo);
 453                 free(slab);
 454         }
 455         mtx_destroy(&device->shader_slab_mutex);
 456 }
 457
 458 /* For the UMR disassembler. */
 459 #define DEBUGGER_END_OF_CODE_MARKER    0xbf9f0000 /* invalid instruction */
 460 #define DEBUGGER_NUM_MARKERS           5
 461
 462 static unsigned
 463 radv_get_shader_binary_size(struct ac_shader_binary *binary)
 464 {
 465         return binary->code_size + DEBUGGER_NUM_MARKERS * 4;
 466 }
 467
 468 static void
 469 radv_fill_shader_variant(struct radv_device *device,
 470                          struct radv_shader_variant *variant,
 471                          struct ac_shader_binary *binary,
 472                          gl_shader_stage stage)
 473 {
 474         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 475         struct radv_shader_info *info = &variant->info.info;
 476         unsigned vgpr_comp_cnt = 0;
 477
 478         variant->code_size = radv_get_shader_binary_size(binary);
 479         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 480                          S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
 481                          S_00B12C_SCRATCH_EN(scratch_enabled) |
 482                          S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
 483                          S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
 484                          S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
 485                          S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
 486                          S_00B12C_SO_EN(!!info->so.num_outputs);
 487
 488         variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 489                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 490                 S_00B848_DX10_CLAMP(1) |
 491                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 492
 493         switch (stage) {
 494         case MESA_SHADER_TESS_EVAL:
 495                 vgpr_comp_cnt = 3;
 496                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 497                 break;
 498         case MESA_SHADER_TESS_CTRL:
 499                 if (device->physical_device->rad_info.chip_class >= GFX9) {
 500                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 501                 } else {
 502                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 503                 }
 504                 break;
 505         case MESA_SHADER_VERTEX:
 506         case MESA_SHADER_GEOMETRY:
 507                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 508                 break;
 509         case MESA_SHADER_FRAGMENT:
 510                 break;
 511         case MESA_SHADER_COMPUTE:
 512                 variant->rsrc2 |=
 513                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 514                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 515                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 516                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 517                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 518                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 519                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 520                 break;
 521         default:
 522                 unreachable("unsupported shader type");
 523                 break;
 524         }
 525
 526         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 527             stage == MESA_SHADER_GEOMETRY) {
 528                 unsigned es_type = variant->info.gs.es_type;
 529                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 530
 531                 if (es_type == MESA_SHADER_VERTEX) {
 532                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 533                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 534                         es_vgpr_comp_cnt = 3;
 535                 } else {
 536                         unreachable("invalid shader ES type");
 537                 }
 538
 539                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 540                  * VGPR[0:4] are always loaded.
 541                  */
 542                 if (info->uses_invocation_id) {
 543                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 544                 } else if (info->uses_prim_id) {
 545                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 546                 } else if (variant->info.gs.vertices_in >= 3) {
 547                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 548                 } else {
 549                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 550                 }
 551
 552                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 553                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 554                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 555         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 556                    stage == MESA_SHADER_TESS_CTRL) {
 557                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 558         } else {
 559                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 560         }
 561
 562         void *ptr = radv_alloc_shader_memory(device, variant);
 563         memcpy(ptr, binary->code, binary->code_size);
 564
 565         /* Add end-of-code markers for the UMR disassembler. */
 566        uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4;
 567        for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
 568                 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
 569
 570 }
 571
 572 static void radv_init_llvm_target()
 573 {
 574         LLVMInitializeAMDGPUTargetInfo();
 575         LLVMInitializeAMDGPUTarget();
 576         LLVMInitializeAMDGPUTargetMC();
 577         LLVMInitializeAMDGPUAsmPrinter();
 578
 579         /* For inline assembly. */
 580         LLVMInitializeAMDGPUAsmParser();
 581
 582         /* Workaround for bug in llvm 4.0 that causes image intrinsics
 583          * to disappear.
 584          * https://reviews.llvm.org/D26348
 585          *
 586          * Workaround for bug in llvm that causes the GPU to hang in presence
 587          * of nested loops because there is an exec mask issue. The proper
 588          * solution is to fix LLVM but this might require a bunch of work.
 589          * https://bugs.llvm.org/show_bug.cgi?id=37744
 590          *
 591          * "mesa" is the prefix for error messages.
 592          */
 593         if (HAVE_LLVM >= 0x0800) {
 594                 const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
 595                 LLVMParseCommandLineOptions(2, argv, NULL);
 596
 597         } else {
 598                 const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
 599                                         "-amdgpu-skip-threshold=1" };
 600                 LLVMParseCommandLineOptions(3, argv, NULL);
 601         }
 602 }
 603
 604 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
 605
 606 static void radv_init_llvm_once(void)
 607 {
 608         call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
 609 }
 610
 611 static struct radv_shader_variant *
 612 shader_variant_create(struct radv_device *device,
 613                       struct radv_shader_module *module,
 614                       struct nir_shader * const *shaders,
 615                       int shader_count,
 616                       gl_shader_stage stage,
 617                       struct radv_nir_compiler_options *options,
 618                       bool gs_copy_shader,
 619                       void **code_out,
 620                       unsigned *code_size_out)
 621 {
 622         enum radeon_family chip_family = device->physical_device->rad_info.family;
 623         enum ac_target_machine_options tm_options = 0;
 624         struct radv_shader_variant *variant;
 625         struct ac_shader_binary binary;
 626         struct ac_llvm_compiler ac_llvm;
 627         bool thread_compiler;
 628         variant = calloc(1, sizeof(struct radv_shader_variant));
 629         if (!variant)
 630                 return NULL;
 631
 632         options->family = chip_family;
 633         options->chip_class = device->physical_device->rad_info.chip_class;
 634         options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
 635         options->dump_preoptir = options->dump_shader &&
 636                                  device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
 637         options->record_llvm_ir = device->keep_shader_info;
 638         options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
 639         options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
 640         options->address32_hi = device->physical_device->rad_info.address32_hi;
 641
 642         if (options->supports_spill)
 643                 tm_options |= AC_TM_SUPPORTS_SPILL;
 644         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 645                 tm_options |= AC_TM_SISCHED;
 646         if (options->check_ir)
 647                 tm_options |= AC_TM_CHECK_IR;
 648         if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
 649                 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
 650
 651         thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
 652         radv_init_llvm_once();
 653         radv_init_llvm_compiler(&ac_llvm,
 654                                 thread_compiler,
 655                                 chip_family, tm_options);
 656         if (gs_copy_shader) {
 657                 assert(shader_count == 1);
 658                 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
 659                                             &variant->config, &variant->info,
 660                                             options);
 661         } else {
 662                 radv_compile_nir_shader(&ac_llvm, &binary, &variant->config,
 663                                         &variant->info, shaders, shader_count,
 664                                         options);
 665         }
 666
 667         radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
 668
 669         radv_fill_shader_variant(device, variant, &binary, stage);
 670
 671         if (code_out) {
 672                 *code_out = binary.code;
 673                 *code_size_out = binary.code_size;
 674         } else
 675                 free(binary.code);
 676         free(binary.config);
 677         free(binary.rodata);
 678         free(binary.global_symbol_offsets);
 679         free(binary.relocs);
 680         variant->ref_count = 1;
 681
 682         if (device->keep_shader_info) {
 683                 variant->disasm_string = binary.disasm_string;
 684                 variant->llvm_ir_string = binary.llvm_ir_string;
 685                 if (!gs_copy_shader && !module->nir) {
 686                         variant->nir = *shaders;
 687                         variant->spirv = (uint32_t *)module->data;
 688                         variant->spirv_size = module->size;
 689                 }
 690         } else {
 691                 free(binary.disasm_string);
 692         }
 693
 694         return variant;
 695 }
 696
 697 struct radv_shader_variant *
 698 radv_shader_variant_create(struct radv_device *device,
 699                            struct radv_shader_module *module,
 700                            struct nir_shader *const *shaders,
 701                            int shader_count,
 702                            struct radv_pipeline_layout *layout,
 703                            const struct radv_shader_variant_key *key,
 704                            void **code_out,
 705                            unsigned *code_size_out)
 706 {
 707         struct radv_nir_compiler_options options = {0};
 708
 709         options.layout = layout;
 710         if (key)
 711                 options.key = *key;
 712
 713         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 714         options.supports_spill = true;
 715
 716         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 717                                      &options, false, code_out, code_size_out);
 718 }
 719
 720 struct radv_shader_variant *
 721 radv_create_gs_copy_shader(struct radv_device *device,
 722                            struct nir_shader *shader,
 723                            void **code_out,
 724                            unsigned *code_size_out,
 725                            bool multiview)
 726 {
 727         struct radv_nir_compiler_options options = {0};
 728
 729         options.key.has_multiview_view_index = multiview;
 730
 731         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 732                                      &options, true, code_out, code_size_out);
 733 }
 734
 735 void
 736 radv_shader_variant_destroy(struct radv_device *device,
 737                             struct radv_shader_variant *variant)
 738 {
 739         if (!p_atomic_dec_zero(&variant->ref_count))
 740                 return;
 741
 742         mtx_lock(&device->shader_slab_mutex);
 743         list_del(&variant->slab_list);
 744         mtx_unlock(&device->shader_slab_mutex);
 745
 746         ralloc_free(variant->nir);
 747         free(variant->disasm_string);
 748         free(variant->llvm_ir_string);
 749         free(variant);
 750 }
 751
 752 const char *
 753 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 754 {
 755         switch (stage) {
 756         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 757         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 758         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 759         case MESA_SHADER_COMPUTE: return "Compute Shader";
 760         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 761         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 762         default:
 763                 return "Unknown shader";
 764         };
 765 }
 766
 767 static void
 768 generate_shader_stats(struct radv_device *device,
 769                       struct radv_shader_variant *variant,
 770                       gl_shader_stage stage,
 771                       struct _mesa_string_buffer *buf)
 772 {
 773         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 774         unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
 775         struct ac_shader_config *conf;
 776         unsigned max_simd_waves;
 777         unsigned lds_per_wave = 0;
 778
 779         max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
 780
 781         conf = &variant->config;
 782
 783         if (stage == MESA_SHADER_FRAGMENT) {
 784                 lds_per_wave = conf->lds_size * lds_increment +
 785                                align(variant->info.fs.num_interp * 48,
 786                                      lds_increment);
 787         } else if (stage == MESA_SHADER_COMPUTE) {
 788                 unsigned max_workgroup_size =
 789                                 radv_nir_get_max_workgroup_size(chip_class, variant->nir);
 790                 lds_per_wave = (conf->lds_size * lds_increment) /
 791                                DIV_ROUND_UP(max_workgroup_size, 64);
 792         }
 793
 794         if (conf->num_sgprs)
 795                 max_simd_waves =
 796                         MIN2(max_simd_waves,
 797                              ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs);
 798
 799         if (conf->num_vgprs)
 800                 max_simd_waves =
 801                         MIN2(max_simd_waves,
 802                              RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
 803
 804         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 805          * that PS can use.
 806          */
 807         if (lds_per_wave)
 808                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 809
 810         if (stage == MESA_SHADER_FRAGMENT) {
 811                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 812                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 813                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 814                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 815         }
 816
 817         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 818                                    "SGPRS: %d\n"
 819                                    "VGPRS: %d\n"
 820                                    "Spilled SGPRs: %d\n"
 821                                    "Spilled VGPRs: %d\n"
 822                                    "PrivMem VGPRS: %d\n"
 823                                    "Code Size: %d bytes\n"
 824                                    "LDS: %d blocks\n"
 825                                    "Scratch: %d bytes per wave\n"
 826                                    "Max Waves: %d\n"
 827                                    "********************\n\n\n",
 828                                    conf->num_sgprs, conf->num_vgprs,
 829                                    conf->spilled_sgprs, conf->spilled_vgprs,
 830                                    variant->info.private_mem_vgprs, variant->code_size,
 831                                    conf->lds_size, conf->scratch_bytes_per_wave,
 832                                    max_simd_waves);
 833 }
 834
 835 void
 836 radv_shader_dump_stats(struct radv_device *device,
 837                        struct radv_shader_variant *variant,
 838                        gl_shader_stage stage,
 839                        FILE *file)
 840 {
 841         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 842
 843         generate_shader_stats(device, variant, stage, buf);
 844
 845         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 846         fprintf(file, "%s", buf->buf);
 847
 848         _mesa_string_buffer_destroy(buf);
 849 }
 850
 851 VkResult
 852 radv_GetShaderInfoAMD(VkDevice _device,
 853                       VkPipeline _pipeline,
 854                       VkShaderStageFlagBits shaderStage,
 855                       VkShaderInfoTypeAMD infoType,
 856                       size_t* pInfoSize,
 857                       void* pInfo)
 858 {
 859         RADV_FROM_HANDLE(radv_device, device, _device);
 860         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 861         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 862         struct radv_shader_variant *variant = pipeline->shaders[stage];
 863         struct _mesa_string_buffer *buf;
 864         VkResult result = VK_SUCCESS;
 865
 866         /* Spec doesn't indicate what to do if the stage is invalid, so just
 867          * return no info for this. */
 868         if (!variant)
 869                 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
 870
 871         switch (infoType) {
 872         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 873                 if (!pInfo) {
 874                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 875                 } else {
 876                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
 877                         struct ac_shader_config *conf = &variant->config;
 878
 879                         VkShaderStatisticsInfoAMD statistics = {};
 880                         statistics.shaderStageMask = shaderStage;
 881                         statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
 882                         statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class);
 883                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 884
 885                         if (stage == MESA_SHADER_COMPUTE) {
 886                                 unsigned *local_size = variant->nir->info.cs.local_size;
 887                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 888
 889                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 890                                                                ceil((double)workgroup_size / statistics.numPhysicalVgprs);
 891
 892                                 statistics.computeWorkGroupSize[0] = local_size[0];
 893                                 statistics.computeWorkGroupSize[1] = local_size[1];
 894                                 statistics.computeWorkGroupSize[2] = local_size[2];
 895                         } else {
 896                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 897                         }
 898
 899                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 900                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 901                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 902                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 903                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 904
 905                         size_t size = *pInfoSize;
 906                         *pInfoSize = sizeof(statistics);
 907
 908                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 909
 910                         if (size < *pInfoSize)
 911                                 result = VK_INCOMPLETE;
 912                 }
 913
 914                 break;
 915         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 916                 buf = _mesa_string_buffer_create(NULL, 1024);
 917
 918                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 919                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
 920                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 921                 generate_shader_stats(device, variant, stage, buf);
 922
 923                 /* Need to include the null terminator. */
 924                 size_t length = buf->length + 1;
 925
 926                 if (!pInfo) {
 927                         *pInfoSize = length;
 928                 } else {
 929                         size_t size = *pInfoSize;
 930                         *pInfoSize = length;
 931
 932                         memcpy(pInfo, buf->buf, MIN2(size, length));
 933
 934                         if (size < length)
 935                                 result = VK_INCOMPLETE;
 936                 }
 937
 938                 _mesa_string_buffer_destroy(buf);
 939                 break;
 940         default:
 941                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 942                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 943                 break;
 944         }
 945
 946         return result;
 947 }