2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_binary.h"
32 #include "amd_family.h"
33 #include "radv_constants.h"
36 #include "vulkan/vulkan.h"
37 #include "vulkan/util/vk_object.h"
39 #define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
43 struct radv_shader_module
{
44 struct vk_object_base base
;
45 struct nir_shader
*nir
;
46 unsigned char sha1
[20];
52 RADV_ALPHA_ADJUST_NONE
= 0,
53 RADV_ALPHA_ADJUST_SNORM
= 1,
54 RADV_ALPHA_ADJUST_SINT
= 2,
55 RADV_ALPHA_ADJUST_SSCALED
= 3,
58 struct radv_vs_out_key
{
62 uint32_t as_ngg_passthrough
:1;
63 uint32_t export_prim_id
:1;
64 uint32_t export_layer_id
:1;
65 uint32_t export_clip_dists
:1;
66 uint32_t export_viewport_index
:1;
69 struct radv_vs_variant_key
{
70 struct radv_vs_out_key out
;
72 uint32_t instance_rate_inputs
;
73 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
74 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
75 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
76 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
77 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
79 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
80 * so we may need to fix it up. */
81 uint64_t alpha_adjust
;
83 /* For some formats the channels have to be shuffled. */
84 uint32_t post_shuffle
;
86 /* Output primitive type. */
90 struct radv_tes_variant_key
{
91 struct radv_vs_out_key out
;
94 uint8_t tcs_num_outputs
;
97 struct radv_tcs_variant_key
{
98 struct radv_vs_variant_key vs_key
;
99 unsigned primitive_mode
;
100 unsigned input_vertices
;
102 uint32_t tes_reads_tess_factors
:1;
105 struct radv_fs_variant_key
{
107 uint8_t log2_ps_iter_samples
;
114 struct radv_cs_variant_key
{
115 uint8_t subgroup_size
;
118 struct radv_shader_variant_key
{
120 struct radv_vs_variant_key vs
;
121 struct radv_fs_variant_key fs
;
122 struct radv_tes_variant_key tes
;
123 struct radv_tcs_variant_key tcs
;
124 struct radv_cs_variant_key cs
;
126 /* A common prefix of the vs and tes keys. */
127 struct radv_vs_out_key vs_common_out
;
129 bool has_multiview_view_index
;
132 enum radv_compiler_debug_level
{
133 RADV_COMPILER_DEBUG_LEVEL_PERFWARN
,
134 RADV_COMPILER_DEBUG_LEVEL_ERROR
,
137 struct radv_nir_compiler_options
{
138 struct radv_pipeline_layout
*layout
;
139 struct radv_shader_variant_key key
;
140 bool explicit_scratch_args
;
141 bool clamp_shadow_reference
;
142 bool robust_buffer_access
;
148 bool has_ls_vgpr_init_bug
;
149 bool use_ngg_streamout
;
150 bool enable_mrt_output_nan_fixup
;
151 enum radeon_family family
;
152 enum chip_class chip_class
;
153 uint32_t tess_offchip_block_dw_size
;
154 uint32_t address32_hi
;
157 void (*func
)(void *private_data
,
158 enum radv_compiler_debug_level level
,
159 const char *message
);
165 AC_UD_SCRATCH_RING_OFFSETS
= 0,
166 AC_UD_PUSH_CONSTANTS
= 1,
167 AC_UD_INLINE_PUSH_CONSTANTS
= 2,
168 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 3,
169 AC_UD_VIEW_INDEX
= 4,
170 AC_UD_STREAMOUT_BUFFERS
= 5,
171 AC_UD_NGG_GS_STATE
= 6,
172 AC_UD_SHADER_START
= 7,
173 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
174 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
177 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
182 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
185 struct radv_stream_output
{
189 uint8_t component_mask
;
193 struct radv_streamout_info
{
194 uint16_t num_outputs
;
195 struct radv_stream_output outputs
[MAX_SO_OUTPUTS
];
196 uint16_t strides
[MAX_SO_BUFFERS
];
197 uint32_t enabled_stream_buffers_mask
;
200 struct radv_userdata_info
{
205 struct radv_userdata_locations
{
206 struct radv_userdata_info descriptor_sets
[MAX_SETS
];
207 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
208 uint32_t descriptor_sets_enabled
;
211 struct radv_vs_output_info
{
212 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
213 uint8_t clip_dist_mask
;
214 uint8_t cull_dist_mask
;
215 uint8_t param_exports
;
216 bool writes_pointsize
;
218 bool writes_viewport_index
;
220 unsigned pos_exports
;
223 struct radv_es_output_info
{
224 uint32_t esgs_itemsize
;
227 struct gfx9_gs_info
{
228 uint32_t vgt_gs_onchip_cntl
;
229 uint32_t vgt_gs_max_prims_per_subgroup
;
230 uint32_t vgt_esgs_ring_itemsize
;
234 struct gfx10_ngg_info
{
235 uint16_t ngg_emit_size
; /* in dwords */
236 uint32_t hw_max_esverts
;
237 uint32_t max_gsprims
;
238 uint32_t max_out_verts
;
239 uint32_t prim_amp_factor
;
240 uint32_t vgt_esgs_ring_itemsize
;
241 uint32_t esgs_ring_size
;
242 bool max_vert_out_per_gs_instance
;
245 struct radv_shader_info
{
246 bool loads_push_constants
;
247 bool loads_dynamic_offsets
;
248 uint8_t min_push_constant_used
;
249 uint8_t max_push_constant_used
;
250 bool has_only_32bit_push_constants
;
251 bool has_indirect_push_constants
;
252 uint8_t num_inline_push_consts
;
253 uint8_t base_inline_push_consts
;
254 uint32_t desc_set_used_mask
;
255 bool needs_multiview_view_index
;
256 bool uses_invocation_id
;
259 uint8_t ballot_bit_size
;
260 struct radv_userdata_locations user_sgprs_locs
;
261 unsigned num_user_sgprs
;
262 unsigned num_input_sgprs
;
263 unsigned num_input_vgprs
;
264 unsigned private_mem_vgprs
;
265 bool need_indirect_descriptor_sets
;
267 bool is_ngg_passthrough
;
269 uint64_t ls_outputs_written
;
270 uint8_t input_usage_mask
[RADV_VERT_ATTRIB_MAX
];
271 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
272 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
274 bool needs_instance_id
;
275 struct radv_vs_output_info outinfo
;
276 struct radv_es_output_info es_info
;
280 uint8_t num_linked_outputs
;
283 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
284 uint8_t num_stream_output_components
[4];
285 uint8_t output_streams
[VARYING_SLOT_VAR31
+ 1];
288 unsigned gsvs_vertex_size
;
289 unsigned max_gsvs_emit_size
;
290 unsigned vertices_in
;
291 unsigned vertices_out
;
292 unsigned output_prim
;
293 unsigned invocations
;
294 unsigned es_type
; /* GFX9: VS or TES */
295 uint8_t num_linked_inputs
;
298 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
299 struct radv_vs_output_info outinfo
;
300 struct radv_es_output_info es_info
;
302 unsigned primitive_mode
;
303 enum gl_tess_spacing spacing
;
307 uint8_t num_linked_inputs
;
308 uint8_t num_linked_patch_inputs
;
309 uint8_t num_linked_outputs
;
312 bool force_persample
;
313 bool needs_sample_positions
;
317 bool writes_sample_mask
;
321 bool viewport_index_input
;
322 uint8_t num_input_clips_culls
;
324 uint32_t flat_shaded_mask
;
325 uint32_t explicit_shaded_mask
;
326 uint32_t float16_shaded_mask
;
328 uint32_t cb_shader_mask
;
330 bool early_fragment_test
;
331 bool post_depth_coverage
;
332 uint8_t depth_layout
;
336 bool uses_block_id
[3];
337 bool uses_thread_id
[3];
338 bool uses_local_invocation_idx
;
339 unsigned block_size
[3];
342 uint64_t outputs_written
;
343 uint64_t patch_outputs_written
;
344 uint64_t tes_inputs_read
;
345 uint64_t tes_patch_inputs_read
;
346 unsigned tcs_vertices_out
;
347 uint32_t num_patches
;
348 uint32_t num_lds_blocks
;
349 uint8_t num_linked_inputs
;
350 uint8_t num_linked_outputs
;
351 uint8_t num_linked_patch_outputs
;
354 struct radv_streamout_info so
;
356 struct gfx9_gs_info gs_ring_info
;
357 struct gfx10_ngg_info ngg_info
;
359 unsigned float_controls_mode
;
362 enum radv_shader_binary_type
{
363 RADV_BINARY_TYPE_LEGACY
,
364 RADV_BINARY_TYPE_RTLD
367 struct radv_shader_binary
{
368 enum radv_shader_binary_type type
;
369 gl_shader_stage stage
;
370 bool is_gs_copy_shader
;
372 struct radv_shader_info info
;
374 /* Self-referential size so we avoid consistency issues. */
378 struct radv_shader_binary_legacy
{
379 struct radv_shader_binary base
;
380 struct ac_shader_config config
;
384 unsigned disasm_size
;
387 /* data has size of stats_size + code_size + ir_size + disasm_size + 2,
388 * where the +2 is for 0 of the ir strings. */
392 struct radv_shader_binary_rtld
{
393 struct radv_shader_binary base
;
395 unsigned llvm_ir_size
;
399 struct radv_compiler_statistic_info
{
404 struct radv_compiler_statistics
{
406 struct radv_compiler_statistic_info
*infos
;
410 struct radv_shader_variant
{
413 struct radeon_winsys_bo
*bo
;
415 struct ac_shader_config config
;
418 struct radv_shader_info info
;
426 struct radv_compiler_statistics
*statistics
;
428 struct list_head slab_list
;
431 struct radv_shader_slab
{
432 struct list_head slabs
;
433 struct list_head shaders
;
434 struct radeon_winsys_bo
*bo
;
440 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
443 radv_nir_lower_ycbcr_textures(nir_shader
*shader
,
444 const struct radv_pipeline_layout
*layout
);
447 radv_shader_compile_to_nir(struct radv_device
*device
,
448 struct radv_shader_module
*module
,
449 const char *entrypoint_name
,
450 gl_shader_stage stage
,
451 const VkSpecializationInfo
*spec_info
,
452 const VkPipelineCreateFlags flags
,
453 const struct radv_pipeline_layout
*layout
,
454 unsigned subgroup_size
, unsigned ballot_bit_size
);
457 radv_destroy_shader_slabs(struct radv_device
*device
);
460 radv_create_shaders(struct radv_pipeline
*pipeline
,
461 struct radv_device
*device
,
462 struct radv_pipeline_cache
*cache
,
463 const struct radv_pipeline_key
*key
,
464 const VkPipelineShaderStageCreateInfo
**pStages
,
465 const VkPipelineCreateFlags flags
,
466 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
467 VkPipelineCreationFeedbackEXT
**stage_feedbacks
);
469 struct radv_shader_variant
*
470 radv_shader_variant_create(struct radv_device
*device
,
471 const struct radv_shader_binary
*binary
,
472 bool keep_shader_info
);
473 struct radv_shader_variant
*
474 radv_shader_variant_compile(struct radv_device
*device
,
475 struct radv_shader_module
*module
,
476 struct nir_shader
*const *shaders
,
478 struct radv_pipeline_layout
*layout
,
479 const struct radv_shader_variant_key
*key
,
480 struct radv_shader_info
*info
,
481 bool keep_shader_info
, bool keep_statistic_info
,
482 struct radv_shader_binary
**binary_out
);
484 struct radv_shader_variant
*
485 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
486 struct radv_shader_info
*info
,
487 struct radv_shader_binary
**binary_out
,
488 bool multiview
, bool keep_shader_info
,
489 bool keep_statistic_info
);
491 struct radv_shader_variant
*
492 radv_create_trap_handler_shader(struct radv_device
*device
);
495 radv_shader_variant_destroy(struct radv_device
*device
,
496 struct radv_shader_variant
*variant
);
500 radv_get_max_waves(struct radv_device
*device
,
501 struct radv_shader_variant
*variant
,
502 gl_shader_stage stage
);
505 radv_get_max_workgroup_size(enum chip_class chip_class
,
506 gl_shader_stage stage
,
507 const unsigned *sizes
);
510 radv_get_shader_name(struct radv_shader_info
*info
,
511 gl_shader_stage stage
);
514 radv_shader_dump_stats(struct radv_device
*device
,
515 struct radv_shader_variant
*variant
,
516 gl_shader_stage stage
,
520 radv_can_dump_shader(struct radv_device
*device
,
521 struct radv_shader_module
*module
,
522 bool is_gs_copy_shader
);
525 radv_can_dump_shader_stats(struct radv_device
*device
,
526 struct radv_shader_module
*module
);
528 static inline unsigned
529 shader_io_get_unique_index(gl_varying_slot slot
)
531 /* handle patch indices separate */
532 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
534 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
536 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
537 return 2 + (slot
- VARYING_SLOT_PATCH0
);
538 if (slot
== VARYING_SLOT_POS
)
540 if (slot
== VARYING_SLOT_PSIZ
)
542 if (slot
== VARYING_SLOT_CLIP_DIST0
)
544 if (slot
== VARYING_SLOT_CLIP_DIST1
)
546 /* 3 is reserved for clip dist as well */
547 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
548 return 4 + (slot
- VARYING_SLOT_VAR0
);
549 unreachable("illegal slot in get unique index\n");
552 static inline unsigned
553 calculate_tess_lds_size(enum chip_class chip_class
,
554 unsigned tcs_num_input_vertices
,
555 unsigned tcs_num_output_vertices
,
556 unsigned tcs_num_inputs
,
557 unsigned tcs_num_patches
,
558 unsigned tcs_num_outputs
,
559 unsigned tcs_num_patch_outputs
)
561 unsigned input_vertex_size
= tcs_num_inputs
* 16;
562 unsigned output_vertex_size
= tcs_num_outputs
* 16;
564 unsigned input_patch_size
= tcs_num_input_vertices
* input_vertex_size
;
566 unsigned pervertex_output_patch_size
= tcs_num_output_vertices
* output_vertex_size
;
567 unsigned output_patch_size
= pervertex_output_patch_size
+ tcs_num_patch_outputs
* 16;
569 unsigned output_patch0_offset
= input_patch_size
* tcs_num_patches
;
571 unsigned lds_size
= output_patch0_offset
+ output_patch_size
* tcs_num_patches
;
573 if (chip_class
>= GFX7
) {
574 assert(lds_size
<= 65536);
575 lds_size
= align(lds_size
, 512) / 512;
577 assert(lds_size
<= 32768);
578 lds_size
= align(lds_size
, 256) / 256;
584 static inline unsigned
585 get_tcs_num_patches(unsigned tcs_num_input_vertices
,
586 unsigned tcs_num_output_vertices
,
587 unsigned tcs_num_inputs
,
588 unsigned tcs_num_outputs
,
589 unsigned tcs_num_patch_outputs
,
590 unsigned tess_offchip_block_dw_size
,
591 enum chip_class chip_class
,
592 enum radeon_family family
)
594 uint32_t input_vertex_size
= tcs_num_inputs
* 16;
595 uint32_t input_patch_size
= tcs_num_input_vertices
* input_vertex_size
;
596 uint32_t output_vertex_size
= tcs_num_outputs
* 16;
597 uint32_t pervertex_output_patch_size
= tcs_num_output_vertices
* output_vertex_size
;
598 uint32_t output_patch_size
= pervertex_output_patch_size
+ tcs_num_patch_outputs
* 16;
600 /* Ensure that we only need one wave per SIMD so we don't need to check
601 * resource usage. Also ensures that the number of tcs in and out
602 * vertices per threadgroup are at most 256.
604 unsigned num_patches
= 64 / MAX2(tcs_num_input_vertices
, tcs_num_output_vertices
) * 4;
605 /* Make sure that the data fits in LDS. This assumes the shaders only
606 * use LDS for the inputs and outputs.
608 unsigned hardware_lds_size
= 32768;
610 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
611 * threadgroup, even though there is more than 32 KiB LDS.
613 * Test: dEQP-VK.tessellation.shader_input_output.barrier
615 if (chip_class
>= GFX7
&& family
!= CHIP_STONEY
)
616 hardware_lds_size
= 65536;
618 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
619 /* Make sure the output data fits in the offchip buffer */
620 num_patches
= MIN2(num_patches
, (tess_offchip_block_dw_size
* 4) / output_patch_size
);
621 /* Not necessary for correctness, but improves performance. The
622 * specific value is taken from the proprietary driver.
624 num_patches
= MIN2(num_patches
, 40);
626 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
627 if (chip_class
== GFX6
) {
628 unsigned one_wave
= 64 / MAX2(tcs_num_input_vertices
, tcs_num_output_vertices
);
629 num_patches
= MIN2(num_patches
, one_wave
);
635 radv_lower_fs_io(nir_shader
*nir
);