src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "ac_binary.h"
  32 #include "amd_family.h"
  33 #include "radv_constants.h"
  34
  35 #include "nir/nir.h"
  36 #include "vulkan/vulkan.h"
  37 #include "vulkan/util/vk_object.h"
  38
  39 #define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
  40
  41 struct radv_device;
  42
  43 struct radv_shader_module {
  44         struct vk_object_base base;
  45         struct nir_shader *nir;
  46         unsigned char sha1[20];
  47         uint32_t size;
  48         char data[0];
  49 };
  50
  51 enum {
  52         RADV_ALPHA_ADJUST_NONE = 0,
  53         RADV_ALPHA_ADJUST_SNORM = 1,
  54         RADV_ALPHA_ADJUST_SINT = 2,
  55         RADV_ALPHA_ADJUST_SSCALED = 3,
  56 };
  57
  58 struct radv_vs_out_key {
  59         uint32_t as_es:1;
  60         uint32_t as_ls:1;
  61         uint32_t as_ngg:1;
  62         uint32_t as_ngg_passthrough:1;
  63         uint32_t export_prim_id:1;
  64         uint32_t export_layer_id:1;
  65         uint32_t export_clip_dists:1;
  66         uint32_t export_viewport_index:1;
  67 };
  68
  69 struct radv_vs_variant_key {
  70         struct radv_vs_out_key out;
  71
  72         uint32_t instance_rate_inputs;
  73         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  74         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  75         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  76         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  77         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  78
  79         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  80          * so we may need to fix it up. */
  81         uint64_t alpha_adjust;
  82
  83         /* For some formats the channels have to be shuffled. */
  84         uint32_t post_shuffle;
  85
  86         /* Output primitive type. */
  87         uint8_t outprim;
  88 };
  89
  90 struct radv_tes_variant_key {
  91         struct radv_vs_out_key out;
  92
  93         uint8_t num_patches;
  94         uint8_t tcs_num_outputs;
  95 };
  96
  97 struct radv_tcs_variant_key {
  98         struct radv_vs_variant_key vs_key;
  99         unsigned primitive_mode;
 100         unsigned input_vertices;
 101         unsigned num_inputs;
 102         uint32_t tes_reads_tess_factors:1;
 103 };
 104
 105 struct radv_fs_variant_key {
 106         uint32_t col_format;
 107         uint8_t log2_ps_iter_samples;
 108         uint8_t num_samples;
 109         uint32_t is_int8;
 110         uint32_t is_int10;
 111         bool is_dual_src;
 112 };
 113
 114 struct radv_cs_variant_key {
 115         uint8_t subgroup_size;
 116 };
 117
 118 struct radv_shader_variant_key {
 119         union {
 120                 struct radv_vs_variant_key vs;
 121                 struct radv_fs_variant_key fs;
 122                 struct radv_tes_variant_key tes;
 123                 struct radv_tcs_variant_key tcs;
 124                 struct radv_cs_variant_key cs;
 125
 126                 /* A common prefix of the vs and tes keys. */
 127                 struct radv_vs_out_key vs_common_out;
 128         };
 129         bool has_multiview_view_index;
 130 };
 131
 132 enum radv_compiler_debug_level {
 133         RADV_COMPILER_DEBUG_LEVEL_PERFWARN,
 134         RADV_COMPILER_DEBUG_LEVEL_ERROR,
 135 };
 136
 137 struct radv_nir_compiler_options {
 138         struct radv_pipeline_layout *layout;
 139         struct radv_shader_variant_key key;
 140         bool explicit_scratch_args;
 141         bool clamp_shadow_reference;
 142         bool robust_buffer_access;
 143         bool dump_shader;
 144         bool dump_preoptir;
 145         bool record_ir;
 146         bool record_stats;
 147         bool check_ir;
 148         bool has_ls_vgpr_init_bug;
 149         bool use_ngg_streamout;
 150         bool enable_mrt_output_nan_fixup;
 151         bool disable_optimizations; /* only used by ACO */
 152         enum radeon_family family;
 153         enum chip_class chip_class;
 154         uint32_t tess_offchip_block_dw_size;
 155         uint32_t address32_hi;
 156
 157         struct {
 158                 void (*func)(void *private_data,
 159                              enum radv_compiler_debug_level level,
 160                              const char *message);
 161                 void *private_data;
 162         } debug;
 163 };
 164
 165 enum radv_ud_index {
 166         AC_UD_SCRATCH_RING_OFFSETS = 0,
 167         AC_UD_PUSH_CONSTANTS = 1,
 168         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 169         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 170         AC_UD_VIEW_INDEX = 4,
 171         AC_UD_STREAMOUT_BUFFERS = 5,
 172         AC_UD_NGG_GS_STATE = 6,
 173         AC_UD_SHADER_START = 7,
 174         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 175         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 176         AC_UD_VS_MAX_UD,
 177         AC_UD_PS_MAX_UD,
 178         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 179         AC_UD_CS_MAX_UD,
 180         AC_UD_GS_MAX_UD,
 181         AC_UD_TCS_MAX_UD,
 182         AC_UD_TES_MAX_UD,
 183         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 184 };
 185
 186 struct radv_stream_output {
 187         uint8_t location;
 188         uint8_t buffer;
 189         uint16_t offset;
 190         uint8_t component_mask;
 191         uint8_t stream;
 192 };
 193
 194 struct radv_streamout_info {
 195         uint16_t num_outputs;
 196         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 197         uint16_t strides[MAX_SO_BUFFERS];
 198         uint32_t enabled_stream_buffers_mask;
 199 };
 200
 201 struct radv_userdata_info {
 202         int8_t sgpr_idx;
 203         uint8_t num_sgprs;
 204 };
 205
 206 struct radv_userdata_locations {
 207         struct radv_userdata_info descriptor_sets[MAX_SETS];
 208         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 209         uint32_t descriptor_sets_enabled;
 210 };
 211
 212 struct radv_vs_output_info {
 213         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 214         uint8_t clip_dist_mask;
 215         uint8_t cull_dist_mask;
 216         uint8_t param_exports;
 217         bool writes_pointsize;
 218         bool writes_layer;
 219         bool writes_viewport_index;
 220         bool export_prim_id;
 221         unsigned pos_exports;
 222 };
 223
 224 struct radv_es_output_info {
 225        uint32_t esgs_itemsize;
 226 };
 227
 228 struct gfx9_gs_info {
 229         uint32_t vgt_gs_onchip_cntl;
 230         uint32_t vgt_gs_max_prims_per_subgroup;
 231         uint32_t vgt_esgs_ring_itemsize;
 232         uint32_t lds_size;
 233 };
 234
 235 struct gfx10_ngg_info {
 236         uint16_t ngg_emit_size; /* in dwords */
 237         uint32_t hw_max_esverts;
 238         uint32_t max_gsprims;
 239         uint32_t max_out_verts;
 240         uint32_t prim_amp_factor;
 241         uint32_t vgt_esgs_ring_itemsize;
 242         uint32_t esgs_ring_size;
 243         bool max_vert_out_per_gs_instance;
 244 };
 245
 246 struct radv_shader_info {
 247         bool loads_push_constants;
 248         bool loads_dynamic_offsets;
 249         uint8_t min_push_constant_used;
 250         uint8_t max_push_constant_used;
 251         bool has_only_32bit_push_constants;
 252         bool has_indirect_push_constants;
 253         uint8_t num_inline_push_consts;
 254         uint8_t base_inline_push_consts;
 255         uint32_t desc_set_used_mask;
 256         bool needs_multiview_view_index;
 257         bool uses_invocation_id;
 258         bool uses_prim_id;
 259         uint8_t wave_size;
 260         uint8_t ballot_bit_size;
 261         struct radv_userdata_locations user_sgprs_locs;
 262         unsigned num_user_sgprs;
 263         unsigned num_input_sgprs;
 264         unsigned num_input_vgprs;
 265         unsigned private_mem_vgprs;
 266         bool need_indirect_descriptor_sets;
 267         bool is_ngg;
 268         bool is_ngg_passthrough;
 269         struct {
 270                 uint64_t ls_outputs_written;
 271                 uint8_t input_usage_mask[RADV_VERT_ATTRIB_MAX];
 272                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 273                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 274                 bool needs_draw_id;
 275                 bool needs_instance_id;
 276                 struct radv_vs_output_info outinfo;
 277                 struct radv_es_output_info es_info;
 278                 bool as_es;
 279                 bool as_ls;
 280                 bool export_prim_id;
 281                 uint8_t num_linked_outputs;
 282         } vs;
 283         struct {
 284                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 285                 uint8_t num_stream_output_components[4];
 286                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 287                 uint8_t max_stream;
 288                 bool writes_memory;
 289                 unsigned gsvs_vertex_size;
 290                 unsigned max_gsvs_emit_size;
 291                 unsigned vertices_in;
 292                 unsigned vertices_out;
 293                 unsigned output_prim;
 294                 unsigned invocations;
 295                 unsigned es_type; /* GFX9: VS or TES */
 296                 uint8_t num_linked_inputs;
 297         } gs;
 298         struct {
 299                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 300                 struct radv_vs_output_info outinfo;
 301                 struct radv_es_output_info es_info;
 302                 bool as_es;
 303                 unsigned primitive_mode;
 304                 enum gl_tess_spacing spacing;
 305                 bool ccw;
 306                 bool point_mode;
 307                 bool export_prim_id;
 308                 uint8_t num_linked_inputs;
 309                 uint8_t num_linked_patch_inputs;
 310                 uint8_t num_linked_outputs;
 311         } tes;
 312         struct {
 313                 bool force_persample;
 314                 bool needs_sample_positions;
 315                 bool writes_memory;
 316                 bool writes_z;
 317                 bool writes_stencil;
 318                 bool writes_sample_mask;
 319                 bool has_pcoord;
 320                 bool prim_id_input;
 321                 bool layer_input;
 322                 bool viewport_index_input;
 323                 uint8_t num_input_clips_culls;
 324                 uint32_t input_mask;
 325                 uint32_t flat_shaded_mask;
 326                 uint32_t explicit_shaded_mask;
 327                 uint32_t float16_shaded_mask;
 328                 uint32_t num_interp;
 329                 uint32_t cb_shader_mask;
 330                 bool can_discard;
 331                 bool early_fragment_test;
 332                 bool post_depth_coverage;
 333                 uint8_t depth_layout;
 334         } ps;
 335         struct {
 336                 bool uses_grid_size;
 337                 bool uses_block_id[3];
 338                 bool uses_thread_id[3];
 339                 bool uses_local_invocation_idx;
 340                 unsigned block_size[3];
 341         } cs;
 342         struct {
 343                 uint64_t outputs_written;
 344                 uint64_t patch_outputs_written;
 345                 uint64_t tes_inputs_read;
 346                 uint64_t tes_patch_inputs_read;
 347                 unsigned tcs_vertices_out;
 348                 uint32_t num_patches;
 349                 uint32_t num_lds_blocks;
 350                 uint8_t num_linked_inputs;
 351                 uint8_t num_linked_outputs;
 352                 uint8_t num_linked_patch_outputs;
 353         } tcs;
 354
 355         struct radv_streamout_info so;
 356
 357         struct gfx9_gs_info gs_ring_info;
 358         struct gfx10_ngg_info ngg_info;
 359
 360         unsigned float_controls_mode;
 361 };
 362
 363 enum radv_shader_binary_type {
 364         RADV_BINARY_TYPE_LEGACY,
 365         RADV_BINARY_TYPE_RTLD
 366 };
 367
 368 struct radv_shader_binary {
 369         enum radv_shader_binary_type type;
 370         gl_shader_stage stage;
 371         bool is_gs_copy_shader;
 372
 373         struct radv_shader_info info;
 374
 375         /* Self-referential size so we avoid consistency issues. */
 376         uint32_t total_size;
 377 };
 378
 379 struct radv_shader_binary_legacy {
 380         struct radv_shader_binary base;
 381         struct ac_shader_config config;
 382         unsigned code_size;
 383         unsigned exec_size;
 384         unsigned ir_size;
 385         unsigned disasm_size;
 386         unsigned stats_size;
 387
 388         /* data has size of stats_size + code_size + ir_size + disasm_size + 2,
 389          * where the +2 is for 0 of the ir strings. */
 390         uint8_t data[0];
 391 };
 392
 393 struct radv_shader_binary_rtld {
 394         struct radv_shader_binary base;
 395         unsigned elf_size;
 396         unsigned llvm_ir_size;
 397         uint8_t data[0];
 398 };
 399
 400 struct radv_compiler_statistic_info {
 401         char name[32];
 402         char desc[64];
 403 };
 404
 405 struct radv_compiler_statistics {
 406         unsigned count;
 407         struct radv_compiler_statistic_info *infos;
 408         uint32_t values[];
 409 };
 410
 411 struct radv_shader_variant {
 412         uint32_t ref_count;
 413
 414         struct radeon_winsys_bo *bo;
 415         uint64_t bo_offset;
 416         struct ac_shader_config config;
 417         uint32_t code_size;
 418         uint32_t exec_size;
 419         struct radv_shader_info info;
 420
 421         /* debug only */
 422         char *spirv;
 423         uint32_t spirv_size;
 424         char *nir_string;
 425         char *disasm_string;
 426         char *ir_string;
 427         struct radv_compiler_statistics *statistics;
 428
 429         struct list_head slab_list;
 430 };
 431
 432 struct radv_shader_slab {
 433         struct list_head slabs;
 434         struct list_head shaders;
 435         struct radeon_winsys_bo *bo;
 436         uint64_t size;
 437         char *ptr;
 438 };
 439
 440 void
 441 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 442                   bool allow_copies);
 443 bool
 444 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 445                              const struct radv_pipeline_layout *layout);
 446
 447 nir_shader *
 448 radv_shader_compile_to_nir(struct radv_device *device,
 449                            struct radv_shader_module *module,
 450                            const char *entrypoint_name,
 451                            gl_shader_stage stage,
 452                            const VkSpecializationInfo *spec_info,
 453                            const VkPipelineCreateFlags flags,
 454                            const struct radv_pipeline_layout *layout,
 455                            unsigned subgroup_size, unsigned ballot_bit_size);
 456
 457 void
 458 radv_destroy_shader_slabs(struct radv_device *device);
 459
 460 VkResult
 461 radv_create_shaders(struct radv_pipeline *pipeline,
 462                     struct radv_device *device,
 463                     struct radv_pipeline_cache *cache,
 464                     const struct radv_pipeline_key *key,
 465                     const VkPipelineShaderStageCreateInfo **pStages,
 466                     const VkPipelineCreateFlags flags,
 467                     VkPipelineCreationFeedbackEXT *pipeline_feedback,
 468                     VkPipelineCreationFeedbackEXT **stage_feedbacks);
 469
 470 struct radv_shader_variant *
 471 radv_shader_variant_create(struct radv_device *device,
 472                            const struct radv_shader_binary *binary,
 473                            bool keep_shader_info);
 474 struct radv_shader_variant *
 475 radv_shader_variant_compile(struct radv_device *device,
 476                             struct radv_shader_module *module,
 477                             struct nir_shader *const *shaders,
 478                             int shader_count,
 479                             struct radv_pipeline_layout *layout,
 480                             const struct radv_shader_variant_key *key,
 481                             struct radv_shader_info *info,
 482                             bool keep_shader_info, bool keep_statistic_info,
 483                             bool disable_optimizations,
 484                             struct radv_shader_binary **binary_out);
 485
 486 struct radv_shader_variant *
 487 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 488                            struct radv_shader_info *info,
 489                            struct radv_shader_binary **binary_out,
 490                            bool multiview,  bool keep_shader_info,
 491                            bool keep_statistic_info,
 492                            bool disable_optimizations);
 493
 494 struct radv_shader_variant *
 495 radv_create_trap_handler_shader(struct radv_device *device);
 496
 497 void
 498 radv_shader_variant_destroy(struct radv_device *device,
 499                             struct radv_shader_variant *variant);
 500
 501
 502 unsigned
 503 radv_get_max_waves(struct radv_device *device,
 504                    struct radv_shader_variant *variant,
 505                    gl_shader_stage stage);
 506
 507 unsigned
 508 radv_get_max_workgroup_size(enum chip_class chip_class,
 509                             gl_shader_stage stage,
 510                             const unsigned *sizes);
 511
 512 const char *
 513 radv_get_shader_name(struct radv_shader_info *info,
 514                      gl_shader_stage stage);
 515
 516 bool
 517 radv_can_dump_shader(struct radv_device *device,
 518                      struct radv_shader_module *module,
 519                      bool is_gs_copy_shader);
 520
 521 bool
 522 radv_can_dump_shader_stats(struct radv_device *device,
 523                            struct radv_shader_module *module);
 524
 525 VkResult
 526 radv_dump_shader_stats(struct radv_device *device,
 527                        struct radv_pipeline *pipeline,
 528                        gl_shader_stage stage, FILE *output);
 529
 530 static inline unsigned
 531 shader_io_get_unique_index(gl_varying_slot slot)
 532 {
 533         /* handle patch indices separate */
 534         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 535                 return 0;
 536         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 537                 return 1;
 538         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 539                 return 2 + (slot - VARYING_SLOT_PATCH0);
 540         if (slot == VARYING_SLOT_POS)
 541                 return 0;
 542         if (slot == VARYING_SLOT_PSIZ)
 543                 return 1;
 544         if (slot == VARYING_SLOT_CLIP_DIST0)
 545                 return 2;
 546         if (slot == VARYING_SLOT_CLIP_DIST1)
 547                 return 3;
 548         /* 3 is reserved for clip dist as well */
 549         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 550                 return 4 + (slot - VARYING_SLOT_VAR0);
 551         unreachable("illegal slot in get unique index\n");
 552 }
 553
 554 static inline unsigned
 555 calculate_tess_lds_size(enum chip_class chip_class,
 556                         unsigned tcs_num_input_vertices,
 557                         unsigned tcs_num_output_vertices,
 558                         unsigned tcs_num_inputs,
 559                         unsigned tcs_num_patches,
 560                         unsigned tcs_num_outputs,
 561                         unsigned tcs_num_patch_outputs)
 562 {
 563         unsigned input_vertex_size = tcs_num_inputs * 16;
 564         unsigned output_vertex_size = tcs_num_outputs * 16;
 565
 566         unsigned input_patch_size = tcs_num_input_vertices * input_vertex_size;
 567
 568         unsigned pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
 569         unsigned output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16;
 570
 571         unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
 572
 573         unsigned lds_size = output_patch0_offset + output_patch_size * tcs_num_patches;
 574
 575         if (chip_class >= GFX7) {
 576                 assert(lds_size <= 65536);
 577                 lds_size = align(lds_size, 512) / 512;
 578         } else {
 579                 assert(lds_size <= 32768);
 580                 lds_size = align(lds_size, 256) / 256;
 581         }
 582
 583         return lds_size;
 584 }
 585
 586 static inline unsigned
 587 get_tcs_num_patches(unsigned tcs_num_input_vertices,
 588                         unsigned tcs_num_output_vertices,
 589                         unsigned tcs_num_inputs,
 590                         unsigned tcs_num_outputs,
 591                         unsigned tcs_num_patch_outputs,
 592                         unsigned tess_offchip_block_dw_size,
 593                         enum chip_class chip_class,
 594                         enum radeon_family family)
 595 {
 596         uint32_t input_vertex_size = tcs_num_inputs * 16;
 597         uint32_t input_patch_size = tcs_num_input_vertices * input_vertex_size;
 598         uint32_t output_vertex_size = tcs_num_outputs * 16;
 599         uint32_t pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
 600         uint32_t output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16;
 601
 602         /* Ensure that we only need one wave per SIMD so we don't need to check
 603          * resource usage. Also ensures that the number of tcs in and out
 604          * vertices per threadgroup are at most 256.
 605          */
 606         unsigned num_patches = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices) * 4;
 607         /* Make sure that the data fits in LDS. This assumes the shaders only
 608          * use LDS for the inputs and outputs.
 609          */
 610         unsigned hardware_lds_size = 32768;
 611
 612         /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
 613          * threadgroup, even though there is more than 32 KiB LDS.
 614          *
 615          * Test: dEQP-VK.tessellation.shader_input_output.barrier
 616          */
 617         if (chip_class >= GFX7 && family != CHIP_STONEY)
 618                 hardware_lds_size = 65536;
 619
 620         num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
 621         /* Make sure the output data fits in the offchip buffer */
 622         num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size);
 623         /* Not necessary for correctness, but improves performance. The
 624          * specific value is taken from the proprietary driver.
 625          */
 626         num_patches = MIN2(num_patches, 40);
 627
 628         /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
 629         if (chip_class == GFX6) {
 630                 unsigned one_wave = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices);
 631                 num_patches = MIN2(num_patches, one_wave);
 632         }
 633         return num_patches;
 634 }
 635
 636 void
 637 radv_lower_fs_io(nir_shader *nir);
 638
 639 #endif