ac: move ac_shader_info to radv folder
[mesa.git] / src / amd / vulkan / radv_shader.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_SHADER_H
29 #define RADV_SHADER_H
30
31 #include "radv_debug.h"
32 #include "radv_private.h"
33
34 #include "nir/nir.h"
35
36 /* descriptor index into scratch ring offsets */
37 #define RING_SCRATCH 0
38 #define RING_ESGS_VS 1
39 #define RING_ESGS_GS 2
40 #define RING_GSVS_VS 3
41 #define RING_GSVS_GS 4
42 #define RING_HS_TESS_FACTOR 5
43 #define RING_HS_TESS_OFFCHIP 6
44 #define RING_PS_SAMPLE_POSITIONS 7
45
46 // Match MAX_SETS from radv_descriptor_set.h
47 #define RADV_UD_MAX_SETS MAX_SETS
48
49 struct radv_shader_module {
50 struct nir_shader *nir;
51 unsigned char sha1[20];
52 uint32_t size;
53 char data[0];
54 };
55
56 struct radv_shader_info {
57 bool loads_push_constants;
58 uint32_t desc_set_used_mask;
59 bool needs_multiview_view_index;
60 bool uses_invocation_id;
61 bool uses_prim_id;
62 struct {
63 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
64 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
65 bool has_vertex_buffers; /* needs vertex buffers and base/start */
66 bool needs_draw_id;
67 bool needs_instance_id;
68 } vs;
69 struct {
70 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
71 } tes;
72 struct {
73 bool force_persample;
74 bool needs_sample_positions;
75 bool uses_input_attachments;
76 bool writes_memory;
77 bool writes_z;
78 bool writes_stencil;
79 bool writes_sample_mask;
80 bool has_pcoord;
81 bool prim_id_input;
82 bool layer_input;
83 } ps;
84 struct {
85 bool uses_grid_size;
86 bool uses_block_id[3];
87 bool uses_thread_id[3];
88 bool uses_local_invocation_idx;
89 } cs;
90 };
91
92 struct radv_userdata_info {
93 int8_t sgpr_idx;
94 uint8_t num_sgprs;
95 bool indirect;
96 uint32_t indirect_offset;
97 };
98
99 struct radv_userdata_locations {
100 struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
101 struct radv_userdata_info shader_data[AC_UD_MAX_UD];
102 };
103
104 struct radv_vs_output_info {
105 uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
106 uint8_t clip_dist_mask;
107 uint8_t cull_dist_mask;
108 uint8_t param_exports;
109 bool writes_pointsize;
110 bool writes_layer;
111 bool writes_viewport_index;
112 bool export_prim_id;
113 unsigned pos_exports;
114 };
115
116 struct radv_es_output_info {
117 uint32_t esgs_itemsize;
118 };
119
120 struct radv_shader_variant_info {
121 struct radv_userdata_locations user_sgprs_locs;
122 struct radv_shader_info info;
123 unsigned num_user_sgprs;
124 unsigned num_input_sgprs;
125 unsigned num_input_vgprs;
126 unsigned private_mem_vgprs;
127 bool need_indirect_descriptor_sets;
128 struct {
129 struct {
130 struct radv_vs_output_info outinfo;
131 struct radv_es_output_info es_info;
132 unsigned vgpr_comp_cnt;
133 bool as_es;
134 bool as_ls;
135 uint64_t outputs_written;
136 } vs;
137 struct {
138 unsigned num_interp;
139 uint32_t input_mask;
140 uint32_t flat_shaded_mask;
141 bool can_discard;
142 bool early_fragment_test;
143 } fs;
144 struct {
145 unsigned block_size[3];
146 } cs;
147 struct {
148 unsigned vertices_in;
149 unsigned vertices_out;
150 unsigned output_prim;
151 unsigned invocations;
152 unsigned gsvs_vertex_size;
153 unsigned max_gsvs_emit_size;
154 unsigned es_type; /* GFX9: VS or TES */
155 } gs;
156 struct {
157 unsigned tcs_vertices_out;
158 /* Which outputs are actually written */
159 uint64_t outputs_written;
160 /* Which patch outputs are actually written */
161 uint32_t patch_outputs_written;
162
163 } tcs;
164 struct {
165 struct radv_vs_output_info outinfo;
166 struct radv_es_output_info es_info;
167 bool as_es;
168 unsigned primitive_mode;
169 enum gl_tess_spacing spacing;
170 bool ccw;
171 bool point_mode;
172 } tes;
173 };
174 };
175
176 struct radv_shader_variant {
177 uint32_t ref_count;
178
179 struct radeon_winsys_bo *bo;
180 uint64_t bo_offset;
181 struct ac_shader_config config;
182 uint32_t code_size;
183 struct radv_shader_variant_info info;
184 unsigned rsrc1;
185 unsigned rsrc2;
186
187 /* debug only */
188 uint32_t *spirv;
189 uint32_t spirv_size;
190 struct nir_shader *nir;
191 char *disasm_string;
192
193 struct list_head slab_list;
194 };
195
196 struct radv_shader_slab {
197 struct list_head slabs;
198 struct list_head shaders;
199 struct radeon_winsys_bo *bo;
200 uint64_t size;
201 char *ptr;
202 };
203
204 void
205 radv_optimize_nir(struct nir_shader *shader);
206
207 nir_shader *
208 radv_shader_compile_to_nir(struct radv_device *device,
209 struct radv_shader_module *module,
210 const char *entrypoint_name,
211 gl_shader_stage stage,
212 const VkSpecializationInfo *spec_info);
213
214 void *
215 radv_alloc_shader_memory(struct radv_device *device,
216 struct radv_shader_variant *shader);
217
218 void
219 radv_destroy_shader_slabs(struct radv_device *device);
220
221 struct radv_shader_variant *
222 radv_shader_variant_create(struct radv_device *device,
223 struct radv_shader_module *module,
224 struct nir_shader *const *shaders,
225 int shader_count,
226 struct radv_pipeline_layout *layout,
227 const struct ac_shader_variant_key *key,
228 void **code_out,
229 unsigned *code_size_out);
230
231 struct radv_shader_variant *
232 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
233 void **code_out, unsigned *code_size_out,
234 bool multiview);
235
236 void
237 radv_shader_variant_destroy(struct radv_device *device,
238 struct radv_shader_variant *variant);
239
240 const char *
241 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);
242
243 void
244 radv_shader_dump_stats(struct radv_device *device,
245 struct radv_shader_variant *variant,
246 gl_shader_stage stage,
247 FILE *file);
248
249 static inline bool
250 radv_can_dump_shader(struct radv_device *device,
251 struct radv_shader_module *module)
252 {
253 /* Only dump non-meta shaders, useful for debugging purposes. */
254 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS &&
255 module && !module->nir;
256 }
257
258 static inline bool
259 radv_can_dump_shader_stats(struct radv_device *device,
260 struct radv_shader_module *module)
261 {
262 /* Only dump non-meta shader stats. */
263 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
264 module && !module->nir;
265 }
266
267 #endif