src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "ac_binary.h"
  32 #include "amd_family.h"
  33 #include "radv_constants.h"
  34
  35 #include "nir/nir.h"
  36 #include "vulkan/vulkan.h"
  37 #include "vulkan/util/vk_object.h"
  38
  39 struct radv_device;
  40
  41 struct radv_shader_module {
  42         struct vk_object_base base;
  43         struct nir_shader *nir;
  44         unsigned char sha1[20];
  45         uint32_t size;
  46         char data[0];
  47 };
  48
  49 enum {
  50         RADV_ALPHA_ADJUST_NONE = 0,
  51         RADV_ALPHA_ADJUST_SNORM = 1,
  52         RADV_ALPHA_ADJUST_SINT = 2,
  53         RADV_ALPHA_ADJUST_SSCALED = 3,
  54 };
  55
  56 struct radv_vs_out_key {
  57         uint32_t as_es:1;
  58         uint32_t as_ls:1;
  59         uint32_t as_ngg:1;
  60         uint32_t as_ngg_passthrough:1;
  61         uint32_t export_prim_id:1;
  62         uint32_t export_layer_id:1;
  63         uint32_t export_clip_dists:1;
  64         uint32_t export_viewport_index:1;
  65 };
  66
  67 struct radv_vs_variant_key {
  68         struct radv_vs_out_key out;
  69
  70         uint32_t instance_rate_inputs;
  71         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  72         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  73         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  74         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  75         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  76
  77         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  78          * so we may need to fix it up. */
  79         uint64_t alpha_adjust;
  80
  81         /* For some formats the channels have to be shuffled. */
  82         uint32_t post_shuffle;
  83
  84         /* Output primitive type. */
  85         uint8_t outprim;
  86 };
  87
  88 struct radv_tes_variant_key {
  89         struct radv_vs_out_key out;
  90
  91         uint8_t num_patches;
  92         uint8_t tcs_num_outputs;
  93 };
  94
  95 struct radv_tcs_variant_key {
  96         struct radv_vs_variant_key vs_key;
  97         unsigned primitive_mode;
  98         unsigned input_vertices;
  99         unsigned num_inputs;
 100         uint32_t tes_reads_tess_factors:1;
 101 };
 102
 103 struct radv_fs_variant_key {
 104         uint32_t col_format;
 105         uint8_t log2_ps_iter_samples;
 106         uint8_t num_samples;
 107         uint32_t is_int8;
 108         uint32_t is_int10;
 109 };
 110
 111 struct radv_cs_variant_key {
 112         uint8_t subgroup_size;
 113 };
 114
 115 struct radv_shader_variant_key {
 116         union {
 117                 struct radv_vs_variant_key vs;
 118                 struct radv_fs_variant_key fs;
 119                 struct radv_tes_variant_key tes;
 120                 struct radv_tcs_variant_key tcs;
 121                 struct radv_cs_variant_key cs;
 122
 123                 /* A common prefix of the vs and tes keys. */
 124                 struct radv_vs_out_key vs_common_out;
 125         };
 126         bool has_multiview_view_index;
 127 };
 128
 129 struct radv_nir_compiler_options {
 130         struct radv_pipeline_layout *layout;
 131         struct radv_shader_variant_key key;
 132         bool explicit_scratch_args;
 133         bool clamp_shadow_reference;
 134         bool robust_buffer_access;
 135         bool dump_shader;
 136         bool dump_preoptir;
 137         bool record_ir;
 138         bool record_stats;
 139         bool check_ir;
 140         bool has_ls_vgpr_init_bug;
 141         bool use_ngg_streamout;
 142         enum radeon_family family;
 143         enum chip_class chip_class;
 144         uint32_t tess_offchip_block_dw_size;
 145         uint32_t address32_hi;
 146 };
 147
 148 enum radv_ud_index {
 149         AC_UD_SCRATCH_RING_OFFSETS = 0,
 150         AC_UD_PUSH_CONSTANTS = 1,
 151         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 152         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 153         AC_UD_VIEW_INDEX = 4,
 154         AC_UD_STREAMOUT_BUFFERS = 5,
 155         AC_UD_NGG_GS_STATE = 6,
 156         AC_UD_SHADER_START = 7,
 157         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 158         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 159         AC_UD_VS_MAX_UD,
 160         AC_UD_PS_MAX_UD,
 161         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 162         AC_UD_CS_MAX_UD,
 163         AC_UD_GS_MAX_UD,
 164         AC_UD_TCS_MAX_UD,
 165         AC_UD_TES_MAX_UD,
 166         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 167 };
 168
 169 struct radv_stream_output {
 170         uint8_t location;
 171         uint8_t buffer;
 172         uint16_t offset;
 173         uint8_t component_mask;
 174         uint8_t stream;
 175 };
 176
 177 struct radv_streamout_info {
 178         uint16_t num_outputs;
 179         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 180         uint16_t strides[MAX_SO_BUFFERS];
 181         uint32_t enabled_stream_buffers_mask;
 182 };
 183
 184 struct radv_userdata_info {
 185         int8_t sgpr_idx;
 186         uint8_t num_sgprs;
 187 };
 188
 189 struct radv_userdata_locations {
 190         struct radv_userdata_info descriptor_sets[MAX_SETS];
 191         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 192         uint32_t descriptor_sets_enabled;
 193 };
 194
 195 struct radv_vs_output_info {
 196         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 197         uint8_t clip_dist_mask;
 198         uint8_t cull_dist_mask;
 199         uint8_t param_exports;
 200         bool writes_pointsize;
 201         bool writes_layer;
 202         bool writes_viewport_index;
 203         bool export_prim_id;
 204         unsigned pos_exports;
 205 };
 206
 207 struct radv_es_output_info {
 208        uint32_t esgs_itemsize;
 209 };
 210
 211 struct gfx9_gs_info {
 212         uint32_t vgt_gs_onchip_cntl;
 213         uint32_t vgt_gs_max_prims_per_subgroup;
 214         uint32_t vgt_esgs_ring_itemsize;
 215         uint32_t lds_size;
 216 };
 217
 218 struct gfx10_ngg_info {
 219         uint16_t ngg_emit_size; /* in dwords */
 220         uint32_t hw_max_esverts;
 221         uint32_t max_gsprims;
 222         uint32_t max_out_verts;
 223         uint32_t prim_amp_factor;
 224         uint32_t vgt_esgs_ring_itemsize;
 225         uint32_t esgs_ring_size;
 226         bool max_vert_out_per_gs_instance;
 227 };
 228
 229 struct radv_shader_info {
 230         bool loads_push_constants;
 231         bool loads_dynamic_offsets;
 232         uint8_t min_push_constant_used;
 233         uint8_t max_push_constant_used;
 234         bool has_only_32bit_push_constants;
 235         bool has_indirect_push_constants;
 236         uint8_t num_inline_push_consts;
 237         uint8_t base_inline_push_consts;
 238         uint32_t desc_set_used_mask;
 239         bool needs_multiview_view_index;
 240         bool uses_invocation_id;
 241         bool uses_prim_id;
 242         uint8_t wave_size;
 243         uint8_t ballot_bit_size;
 244         struct radv_userdata_locations user_sgprs_locs;
 245         unsigned num_user_sgprs;
 246         unsigned num_input_sgprs;
 247         unsigned num_input_vgprs;
 248         unsigned private_mem_vgprs;
 249         bool need_indirect_descriptor_sets;
 250         bool is_ngg;
 251         bool is_ngg_passthrough;
 252         struct {
 253                 uint64_t ls_outputs_written;
 254                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 255                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 256                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 257                 bool needs_draw_id;
 258                 bool needs_instance_id;
 259                 struct radv_vs_output_info outinfo;
 260                 struct radv_es_output_info es_info;
 261                 bool as_es;
 262                 bool as_ls;
 263                 bool export_prim_id;
 264                 uint8_t num_linked_outputs;
 265         } vs;
 266         struct {
 267                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 268                 uint8_t num_stream_output_components[4];
 269                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 270                 uint8_t max_stream;
 271                 bool writes_memory;
 272                 unsigned gsvs_vertex_size;
 273                 unsigned max_gsvs_emit_size;
 274                 unsigned vertices_in;
 275                 unsigned vertices_out;
 276                 unsigned output_prim;
 277                 unsigned invocations;
 278                 unsigned es_type; /* GFX9: VS or TES */
 279                 uint8_t num_linked_inputs;
 280         } gs;
 281         struct {
 282                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 283                 struct radv_vs_output_info outinfo;
 284                 struct radv_es_output_info es_info;
 285                 bool as_es;
 286                 unsigned primitive_mode;
 287                 enum gl_tess_spacing spacing;
 288                 bool ccw;
 289                 bool point_mode;
 290                 bool export_prim_id;
 291                 uint8_t num_linked_inputs;
 292                 uint8_t num_linked_patch_inputs;
 293                 uint8_t num_linked_outputs;
 294         } tes;
 295         struct {
 296                 bool force_persample;
 297                 bool needs_sample_positions;
 298                 bool writes_memory;
 299                 bool writes_z;
 300                 bool writes_stencil;
 301                 bool writes_sample_mask;
 302                 bool has_pcoord;
 303                 bool prim_id_input;
 304                 bool layer_input;
 305                 bool viewport_index_input;
 306                 uint8_t num_input_clips_culls;
 307                 uint32_t input_mask;
 308                 uint32_t flat_shaded_mask;
 309                 uint32_t explicit_shaded_mask;
 310                 uint32_t float16_shaded_mask;
 311                 uint32_t num_interp;
 312                 bool can_discard;
 313                 bool early_fragment_test;
 314                 bool post_depth_coverage;
 315                 uint8_t depth_layout;
 316         } ps;
 317         struct {
 318                 bool uses_grid_size;
 319                 bool uses_block_id[3];
 320                 bool uses_thread_id[3];
 321                 bool uses_local_invocation_idx;
 322                 unsigned block_size[3];
 323         } cs;
 324         struct {
 325                 uint64_t outputs_written;
 326                 uint64_t patch_outputs_written;
 327                 uint64_t tes_inputs_read;
 328                 uint64_t tes_patch_inputs_read;
 329                 unsigned tcs_vertices_out;
 330                 uint32_t num_patches;
 331                 uint32_t lds_size;
 332                 uint8_t num_linked_inputs;
 333                 uint8_t num_linked_outputs;
 334                 uint8_t num_linked_patch_outputs;
 335         } tcs;
 336
 337         struct radv_streamout_info so;
 338
 339         struct gfx9_gs_info gs_ring_info;
 340         struct gfx10_ngg_info ngg_info;
 341
 342         unsigned float_controls_mode;
 343 };
 344
 345 enum radv_shader_binary_type {
 346         RADV_BINARY_TYPE_LEGACY,
 347         RADV_BINARY_TYPE_RTLD
 348 };
 349
 350 struct radv_shader_binary {
 351         enum radv_shader_binary_type type;
 352         gl_shader_stage stage;
 353         bool is_gs_copy_shader;
 354
 355         struct radv_shader_info info;
 356
 357         /* Self-referential size so we avoid consistency issues. */
 358         uint32_t total_size;
 359 };
 360
 361 struct radv_shader_binary_legacy {
 362         struct radv_shader_binary base;
 363         struct ac_shader_config config;
 364         unsigned code_size;
 365         unsigned exec_size;
 366         unsigned ir_size;
 367         unsigned disasm_size;
 368         unsigned stats_size;
 369
 370         /* data has size of stats_size + code_size + ir_size + disasm_size + 2,
 371          * where the +2 is for 0 of the ir strings. */
 372         uint8_t data[0];
 373 };
 374
 375 struct radv_shader_binary_rtld {
 376         struct radv_shader_binary base;
 377         unsigned elf_size;
 378         unsigned llvm_ir_size;
 379         uint8_t data[0];
 380 };
 381
 382 struct radv_compiler_statistic_info {
 383         char name[32];
 384         char desc[64];
 385 };
 386
 387 struct radv_compiler_statistics {
 388         unsigned count;
 389         struct radv_compiler_statistic_info *infos;
 390         uint32_t values[];
 391 };
 392
 393 struct radv_shader_variant {
 394         uint32_t ref_count;
 395
 396         struct radeon_winsys_bo *bo;
 397         uint64_t bo_offset;
 398         struct ac_shader_config config;
 399         uint32_t code_size;
 400         uint32_t exec_size;
 401         struct radv_shader_info info;
 402
 403         /* debug only */
 404         char *spirv;
 405         uint32_t spirv_size;
 406         char *nir_string;
 407         char *disasm_string;
 408         char *ir_string;
 409         struct radv_compiler_statistics *statistics;
 410
 411         struct list_head slab_list;
 412 };
 413
 414 struct radv_shader_slab {
 415         struct list_head slabs;
 416         struct list_head shaders;
 417         struct radeon_winsys_bo *bo;
 418         uint64_t size;
 419         char *ptr;
 420 };
 421
 422 void
 423 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 424                   bool allow_copies);
 425 bool
 426 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 427                              const struct radv_pipeline_layout *layout);
 428
 429 nir_shader *
 430 radv_shader_compile_to_nir(struct radv_device *device,
 431                            struct radv_shader_module *module,
 432                            const char *entrypoint_name,
 433                            gl_shader_stage stage,
 434                            const VkSpecializationInfo *spec_info,
 435                            const VkPipelineCreateFlags flags,
 436                            const struct radv_pipeline_layout *layout,
 437                            unsigned subgroup_size, unsigned ballot_bit_size);
 438
 439 void *
 440 radv_alloc_shader_memory(struct radv_device *device,
 441                           struct radv_shader_variant *shader);
 442
 443 void
 444 radv_destroy_shader_slabs(struct radv_device *device);
 445
 446 VkResult
 447 radv_create_shaders(struct radv_pipeline *pipeline,
 448                     struct radv_device *device,
 449                     struct radv_pipeline_cache *cache,
 450                     const struct radv_pipeline_key *key,
 451                     const VkPipelineShaderStageCreateInfo **pStages,
 452                     const VkPipelineCreateFlags flags,
 453                     VkPipelineCreationFeedbackEXT *pipeline_feedback,
 454                     VkPipelineCreationFeedbackEXT **stage_feedbacks);
 455
 456 struct radv_shader_variant *
 457 radv_shader_variant_create(struct radv_device *device,
 458                            const struct radv_shader_binary *binary,
 459                            bool keep_shader_info);
 460 struct radv_shader_variant *
 461 radv_shader_variant_compile(struct radv_device *device,
 462                             struct radv_shader_module *module,
 463                             struct nir_shader *const *shaders,
 464                             int shader_count,
 465                             struct radv_pipeline_layout *layout,
 466                             const struct radv_shader_variant_key *key,
 467                             struct radv_shader_info *info,
 468                             bool keep_shader_info, bool keep_statistic_info,
 469                             struct radv_shader_binary **binary_out);
 470
 471 struct radv_shader_variant *
 472 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 473                            struct radv_shader_info *info,
 474                            struct radv_shader_binary **binary_out,
 475                            bool multiview,  bool keep_shader_info,
 476                            bool keep_statistic_info);
 477
 478 void
 479 radv_shader_variant_destroy(struct radv_device *device,
 480                             struct radv_shader_variant *variant);
 481
 482
 483 unsigned
 484 radv_get_max_waves(struct radv_device *device,
 485                    struct radv_shader_variant *variant,
 486                    gl_shader_stage stage);
 487
 488 unsigned
 489 radv_get_max_workgroup_size(enum chip_class chip_class,
 490                             gl_shader_stage stage,
 491                             const unsigned *sizes);
 492
 493 const char *
 494 radv_get_shader_name(struct radv_shader_info *info,
 495                      gl_shader_stage stage);
 496
 497 void
 498 radv_shader_dump_stats(struct radv_device *device,
 499                        struct radv_shader_variant *variant,
 500                        gl_shader_stage stage,
 501                        FILE *file);
 502
 503 bool
 504 radv_can_dump_shader(struct radv_device *device,
 505                      struct radv_shader_module *module,
 506                      bool is_gs_copy_shader);
 507
 508 bool
 509 radv_can_dump_shader_stats(struct radv_device *device,
 510                            struct radv_shader_module *module);
 511
 512 static inline unsigned
 513 shader_io_get_unique_index(gl_varying_slot slot)
 514 {
 515         /* handle patch indices separate */
 516         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 517                 return 0;
 518         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 519                 return 1;
 520         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 521                 return 2 + (slot - VARYING_SLOT_PATCH0);
 522         if (slot == VARYING_SLOT_POS)
 523                 return 0;
 524         if (slot == VARYING_SLOT_PSIZ)
 525                 return 1;
 526         if (slot == VARYING_SLOT_CLIP_DIST0)
 527                 return 2;
 528         if (slot == VARYING_SLOT_CLIP_DIST1)
 529                 return 3;
 530         /* 3 is reserved for clip dist as well */
 531         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 532                 return 4 + (slot - VARYING_SLOT_VAR0);
 533         unreachable("illegal slot in get unique index\n");
 534 }
 535
 536 static inline unsigned
 537 calculate_tess_lds_size(unsigned tcs_num_input_vertices,
 538                         unsigned tcs_num_output_vertices,
 539                         unsigned tcs_num_inputs,
 540                         unsigned tcs_num_patches,
 541                         unsigned tcs_num_outputs,
 542                         unsigned tcs_num_patch_outputs)
 543 {
 544         unsigned input_vertex_size = tcs_num_inputs * 16;
 545         unsigned output_vertex_size = tcs_num_outputs * 16;
 546
 547         unsigned input_patch_size = tcs_num_input_vertices * input_vertex_size;
 548
 549         unsigned pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
 550         unsigned output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16;
 551
 552         unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
 553
 554         return output_patch0_offset + output_patch_size * tcs_num_patches;
 555 }
 556
 557 static inline unsigned
 558 get_tcs_num_patches(unsigned tcs_num_input_vertices,
 559                         unsigned tcs_num_output_vertices,
 560                         unsigned tcs_num_inputs,
 561                         unsigned tcs_num_outputs,
 562                         unsigned tcs_num_patch_outputs,
 563                         unsigned tess_offchip_block_dw_size,
 564                         enum chip_class chip_class,
 565                         enum radeon_family family)
 566 {
 567         uint32_t input_vertex_size = tcs_num_inputs * 16;
 568         uint32_t input_patch_size = tcs_num_input_vertices * input_vertex_size;
 569         uint32_t output_vertex_size = tcs_num_outputs * 16;
 570         uint32_t pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
 571         uint32_t output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16;
 572
 573         /* Ensure that we only need one wave per SIMD so we don't need to check
 574          * resource usage. Also ensures that the number of tcs in and out
 575          * vertices per threadgroup are at most 256.
 576          */
 577         unsigned num_patches = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices) * 4;
 578         /* Make sure that the data fits in LDS. This assumes the shaders only
 579          * use LDS for the inputs and outputs.
 580          */
 581         unsigned hardware_lds_size = 32768;
 582
 583         /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
 584          * threadgroup, even though there is more than 32 KiB LDS.
 585          *
 586          * Test: dEQP-VK.tessellation.shader_input_output.barrier
 587          */
 588         if (chip_class >= GFX7 && family != CHIP_STONEY)
 589                 hardware_lds_size = 65536;
 590
 591         num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
 592         /* Make sure the output data fits in the offchip buffer */
 593         num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size);
 594         /* Not necessary for correctness, but improves performance. The
 595          * specific value is taken from the proprietary driver.
 596          */
 597         num_patches = MIN2(num_patches, 40);
 598
 599         /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
 600         if (chip_class == GFX6) {
 601                 unsigned one_wave = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices);
 602                 num_patches = MIN2(num_patches, one_wave);
 603         }
 604         return num_patches;
 605 }
 606
 607 void
 608 radv_lower_fs_io(nir_shader *nir);
 609
 610 #endif