src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "ac_binary.h"
  32 #include "amd_family.h"
  33 #include "radv_constants.h"
  34
  35 #include "nir/nir.h"
  36 #include "vulkan/vulkan.h"
  37
  38 struct radv_device;
  39
  40 struct radv_shader_module {
  41         struct nir_shader *nir;
  42         unsigned char sha1[20];
  43         uint32_t size;
  44         char data[0];
  45 };
  46
  47 enum {
  48         RADV_ALPHA_ADJUST_NONE = 0,
  49         RADV_ALPHA_ADJUST_SNORM = 1,
  50         RADV_ALPHA_ADJUST_SINT = 2,
  51         RADV_ALPHA_ADJUST_SSCALED = 3,
  52 };
  53
  54 struct radv_vs_out_key {
  55         uint32_t as_es:1;
  56         uint32_t as_ls:1;
  57         uint32_t as_ngg:1;
  58         uint32_t export_prim_id:1;
  59         uint32_t export_layer_id:1;
  60         uint32_t export_clip_dists:1;
  61 };
  62
  63 struct radv_vs_variant_key {
  64         struct radv_vs_out_key out;
  65
  66         uint32_t instance_rate_inputs;
  67         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  68         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  69         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  70         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  71         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  72
  73         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  74          * so we may need to fix it up. */
  75         uint64_t alpha_adjust;
  76
  77         /* For some formats the channels have to be shuffled. */
  78         uint32_t post_shuffle;
  79 };
  80
  81 struct radv_tes_variant_key {
  82         struct radv_vs_out_key out;
  83
  84         uint8_t num_patches;
  85         uint8_t tcs_num_outputs;
  86 };
  87
  88 struct radv_tcs_variant_key {
  89         struct radv_vs_variant_key vs_key;
  90         unsigned primitive_mode;
  91         unsigned input_vertices;
  92         unsigned num_inputs;
  93         uint32_t tes_reads_tess_factors:1;
  94 };
  95
  96 struct radv_fs_variant_key {
  97         uint32_t col_format;
  98         uint8_t log2_ps_iter_samples;
  99         uint8_t num_samples;
 100         uint32_t is_int8;
 101         uint32_t is_int10;
 102 };
 103
 104 struct radv_shader_variant_key {
 105         union {
 106                 struct radv_vs_variant_key vs;
 107                 struct radv_fs_variant_key fs;
 108                 struct radv_tes_variant_key tes;
 109                 struct radv_tcs_variant_key tcs;
 110
 111                 /* A common prefix of the vs and tes keys. */
 112                 struct radv_vs_out_key vs_common_out;
 113         };
 114         bool has_multiview_view_index;
 115 };
 116
 117 struct radv_nir_compiler_options {
 118         struct radv_pipeline_layout *layout;
 119         struct radv_shader_variant_key key;
 120         bool unsafe_math;
 121         bool supports_spill;
 122         bool clamp_shadow_reference;
 123         bool robust_buffer_access;
 124         bool dump_shader;
 125         bool dump_preoptir;
 126         bool record_llvm_ir;
 127         bool check_ir;
 128         bool has_ls_vgpr_init_bug;
 129         enum radeon_family family;
 130         enum chip_class chip_class;
 131         uint32_t tess_offchip_block_dw_size;
 132         uint32_t address32_hi;
 133         uint8_t wave_size;
 134 };
 135
 136 enum radv_ud_index {
 137         AC_UD_SCRATCH_RING_OFFSETS = 0,
 138         AC_UD_PUSH_CONSTANTS = 1,
 139         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 140         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 141         AC_UD_VIEW_INDEX = 4,
 142         AC_UD_STREAMOUT_BUFFERS = 5,
 143         AC_UD_SHADER_START = 6,
 144         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 145         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 146         AC_UD_VS_MAX_UD,
 147         AC_UD_PS_MAX_UD,
 148         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 149         AC_UD_CS_MAX_UD,
 150         AC_UD_GS_MAX_UD,
 151         AC_UD_TCS_MAX_UD,
 152         AC_UD_TES_MAX_UD,
 153         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 154 };
 155
 156 struct radv_stream_output {
 157         uint8_t location;
 158         uint8_t buffer;
 159         uint16_t offset;
 160         uint8_t component_mask;
 161         uint8_t stream;
 162 };
 163
 164 struct radv_streamout_info {
 165         uint16_t num_outputs;
 166         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 167         uint16_t strides[MAX_SO_BUFFERS];
 168         uint32_t enabled_stream_buffers_mask;
 169 };
 170
 171 struct radv_shader_info {
 172         bool loads_push_constants;
 173         bool loads_dynamic_offsets;
 174         uint8_t min_push_constant_used;
 175         uint8_t max_push_constant_used;
 176         bool has_only_32bit_push_constants;
 177         bool has_indirect_push_constants;
 178         uint8_t num_inline_push_consts;
 179         uint8_t base_inline_push_consts;
 180         uint32_t desc_set_used_mask;
 181         bool needs_multiview_view_index;
 182         bool uses_invocation_id;
 183         bool uses_prim_id;
 184         uint8_t wave_size;
 185         struct {
 186                 uint64_t ls_outputs_written;
 187                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 188                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 189                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 190                 bool needs_draw_id;
 191                 bool needs_instance_id;
 192         } vs;
 193         struct {
 194                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 195                 uint8_t num_stream_output_components[4];
 196                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 197                 uint8_t max_stream;
 198         } gs;
 199         struct {
 200                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 201         } tes;
 202         struct {
 203                 bool force_persample;
 204                 bool needs_sample_positions;
 205                 bool writes_memory;
 206                 bool writes_z;
 207                 bool writes_stencil;
 208                 bool writes_sample_mask;
 209                 bool has_pcoord;
 210                 bool prim_id_input;
 211                 bool layer_input;
 212                 uint8_t num_input_clips_culls;
 213                 uint32_t input_mask;
 214                 uint32_t flat_shaded_mask;
 215                 uint32_t float16_shaded_mask;
 216                 uint32_t num_interp;
 217         } ps;
 218         struct {
 219                 bool uses_grid_size;
 220                 bool uses_block_id[3];
 221                 bool uses_thread_id[3];
 222                 bool uses_local_invocation_idx;
 223         } cs;
 224         struct {
 225                 uint64_t outputs_written;
 226                 uint64_t patch_outputs_written;
 227         } tcs;
 228
 229         struct radv_streamout_info so;
 230 };
 231
 232 struct radv_userdata_info {
 233         int8_t sgpr_idx;
 234         uint8_t num_sgprs;
 235 };
 236
 237 struct radv_userdata_locations {
 238         struct radv_userdata_info descriptor_sets[MAX_SETS];
 239         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 240         uint32_t descriptor_sets_enabled;
 241 };
 242
 243 struct radv_vs_output_info {
 244         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 245         uint8_t clip_dist_mask;
 246         uint8_t cull_dist_mask;
 247         uint8_t param_exports;
 248         bool writes_pointsize;
 249         bool writes_layer;
 250         bool writes_viewport_index;
 251         bool export_prim_id;
 252         unsigned pos_exports;
 253 };
 254
 255 struct radv_es_output_info {
 256         uint32_t esgs_itemsize;
 257 };
 258
 259 struct radv_shader_variant_info {
 260         struct radv_userdata_locations user_sgprs_locs;
 261         struct radv_shader_info info;
 262         unsigned num_user_sgprs;
 263         unsigned num_input_sgprs;
 264         unsigned num_input_vgprs;
 265         unsigned private_mem_vgprs;
 266         bool need_indirect_descriptor_sets;
 267         bool is_ngg;
 268         struct {
 269                 struct {
 270                         struct radv_vs_output_info outinfo;
 271                         struct radv_es_output_info es_info;
 272                         bool as_es;
 273                         bool as_ls;
 274                         bool export_prim_id;
 275                 } vs;
 276                 struct {
 277                         bool can_discard;
 278                         bool early_fragment_test;
 279                         bool post_depth_coverage;
 280                 } fs;
 281                 struct {
 282                         unsigned block_size[3];
 283                 } cs;
 284                 struct {
 285                         unsigned vertices_in;
 286                         unsigned vertices_out;
 287                         unsigned output_prim;
 288                         unsigned invocations;
 289                         unsigned gsvs_vertex_size;
 290                         unsigned max_gsvs_emit_size;
 291                         unsigned es_type; /* GFX9: VS or TES */
 292                 } gs;
 293                 struct {
 294                         unsigned tcs_vertices_out;
 295                         uint32_t num_patches;
 296                         uint32_t lds_size;
 297                 } tcs;
 298                 struct {
 299                         struct radv_vs_output_info outinfo;
 300                         struct radv_es_output_info es_info;
 301                         bool as_es;
 302                         unsigned primitive_mode;
 303                         enum gl_tess_spacing spacing;
 304                         bool ccw;
 305                         bool point_mode;
 306                         bool export_prim_id;
 307                 } tes;
 308         };
 309 };
 310
 311 enum radv_shader_binary_type {
 312         RADV_BINARY_TYPE_LEGACY,
 313         RADV_BINARY_TYPE_RTLD
 314 };
 315
 316 struct radv_shader_binary {
 317         enum radv_shader_binary_type type;
 318         gl_shader_stage stage;
 319         bool is_gs_copy_shader;
 320
 321         struct radv_shader_variant_info variant_info;
 322
 323         /* Self-referential size so we avoid consistency issues. */
 324         uint32_t total_size;
 325 };
 326
 327 struct radv_shader_binary_legacy {
 328         struct radv_shader_binary base;
 329         struct ac_shader_config config;
 330         unsigned code_size;
 331         unsigned llvm_ir_size;
 332         unsigned disasm_size;
 333
 334         /* data has size of code_size + llvm_ir_size + disasm_size + 2, where
 335          * the +2 is for 0 of the ir strings. */
 336         uint8_t data[0];
 337 };
 338
 339 struct radv_shader_binary_rtld {
 340         struct radv_shader_binary base;
 341         unsigned elf_size;
 342         unsigned llvm_ir_size;
 343         uint8_t data[0];
 344 };
 345
 346 struct radv_shader_variant {
 347         uint32_t ref_count;
 348
 349         struct radeon_winsys_bo *bo;
 350         uint64_t bo_offset;
 351         struct ac_shader_config config;
 352         uint32_t code_size;
 353         struct radv_shader_variant_info info;
 354
 355         /* debug only */
 356         uint32_t *spirv;
 357         uint32_t spirv_size;
 358         char *nir_string;
 359         char *disasm_string;
 360         char *llvm_ir_string;
 361
 362         struct list_head slab_list;
 363 };
 364
 365 struct radv_shader_slab {
 366         struct list_head slabs;
 367         struct list_head shaders;
 368         struct radeon_winsys_bo *bo;
 369         uint64_t size;
 370         char *ptr;
 371 };
 372
 373 void
 374 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 375                   bool allow_copies);
 376 bool
 377 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 378                              const struct radv_pipeline_layout *layout);
 379
 380 nir_shader *
 381 radv_shader_compile_to_nir(struct radv_device *device,
 382                            struct radv_shader_module *module,
 383                            const char *entrypoint_name,
 384                            gl_shader_stage stage,
 385                            const VkSpecializationInfo *spec_info,
 386                            const VkPipelineCreateFlags flags,
 387                            const struct radv_pipeline_layout *layout);
 388
 389 void *
 390 radv_alloc_shader_memory(struct radv_device *device,
 391                           struct radv_shader_variant *shader);
 392
 393 void
 394 radv_destroy_shader_slabs(struct radv_device *device);
 395
 396 struct radv_shader_variant *
 397 radv_shader_variant_create(struct radv_device *device,
 398                            const struct radv_shader_binary *binary,
 399                            bool keep_shader_info);
 400 struct radv_shader_variant *
 401 radv_shader_variant_compile(struct radv_device *device,
 402                             struct radv_shader_module *module,
 403                             struct nir_shader *const *shaders,
 404                             int shader_count,
 405                             struct radv_pipeline_layout *layout,
 406                             const struct radv_shader_variant_key *key,
 407                             bool keep_shader_info,
 408                             struct radv_shader_binary **binary_out);
 409
 410 struct radv_shader_variant *
 411 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 412                            struct radv_shader_binary **binary_out,
 413                            bool multiview,  bool keep_shader_info);
 414
 415 void
 416 radv_shader_variant_destroy(struct radv_device *device,
 417                             struct radv_shader_variant *variant);
 418
 419
 420 unsigned
 421 radv_get_max_waves(struct radv_device *device,
 422                    struct radv_shader_variant *variant,
 423                    gl_shader_stage stage);
 424
 425 unsigned
 426 radv_get_max_workgroup_size(enum chip_class chip_class,
 427                             gl_shader_stage stage,
 428                             const unsigned *sizes);
 429
 430 const char *
 431 radv_get_shader_name(struct radv_shader_variant_info *info,
 432                      gl_shader_stage stage);
 433
 434 void
 435 radv_shader_dump_stats(struct radv_device *device,
 436                        struct radv_shader_variant *variant,
 437                        gl_shader_stage stage,
 438                        FILE *file);
 439
 440 bool
 441 radv_can_dump_shader(struct radv_device *device,
 442                      struct radv_shader_module *module,
 443                      bool is_gs_copy_shader);
 444
 445 bool
 446 radv_can_dump_shader_stats(struct radv_device *device,
 447                            struct radv_shader_module *module);
 448
 449 unsigned
 450 shader_io_get_unique_index(gl_varying_slot slot);
 451
 452 #endif