2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "radv_debug.h"
32 #include "radv_private.h"
36 /* descriptor index into scratch ring offsets */
37 #define RING_SCRATCH 0
38 #define RING_ESGS_VS 1
39 #define RING_ESGS_GS 2
40 #define RING_GSVS_VS 3
41 #define RING_GSVS_GS 4
42 #define RING_HS_TESS_FACTOR 5
43 #define RING_HS_TESS_OFFCHIP 6
44 #define RING_PS_SAMPLE_POSITIONS 7
46 // Match MAX_SETS from radv_descriptor_set.h
47 #define RADV_UD_MAX_SETS MAX_SETS
49 #define RADV_NUM_PHYSICAL_VGPRS 256
51 struct radv_shader_module
{
52 struct nir_shader
*nir
;
53 unsigned char sha1
[20];
59 RADV_ALPHA_ADJUST_NONE
= 0,
60 RADV_ALPHA_ADJUST_SNORM
= 1,
61 RADV_ALPHA_ADJUST_SINT
= 2,
62 RADV_ALPHA_ADJUST_SSCALED
= 3,
65 struct radv_vs_variant_key
{
66 uint32_t instance_rate_inputs
;
67 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
69 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
70 * so we may need to fix it up. */
71 uint64_t alpha_adjust
;
75 uint32_t export_prim_id
:1;
76 uint32_t export_layer_id
:1;
79 struct radv_tes_variant_key
{
81 uint32_t export_prim_id
:1;
82 uint32_t export_layer_id
:1;
84 uint8_t tcs_num_outputs
;
87 struct radv_tcs_variant_key
{
88 struct radv_vs_variant_key vs_key
;
89 unsigned primitive_mode
;
90 unsigned input_vertices
;
92 uint32_t tes_reads_tess_factors
:1;
95 struct radv_fs_variant_key
{
97 uint8_t log2_ps_iter_samples
;
103 struct radv_shader_variant_key
{
105 struct radv_vs_variant_key vs
;
106 struct radv_fs_variant_key fs
;
107 struct radv_tes_variant_key tes
;
108 struct radv_tcs_variant_key tcs
;
110 bool has_multiview_view_index
;
113 struct radv_nir_compiler_options
{
114 struct radv_pipeline_layout
*layout
;
115 struct radv_shader_variant_key key
;
118 bool clamp_shadow_reference
;
123 enum radeon_family family
;
124 enum chip_class chip_class
;
125 uint32_t tess_offchip_block_dw_size
;
126 uint32_t address32_hi
;
130 AC_UD_SCRATCH_RING_OFFSETS
= 0,
131 AC_UD_PUSH_CONSTANTS
= 1,
132 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 2,
133 AC_UD_VIEW_INDEX
= 3,
134 AC_UD_STREAMOUT_BUFFERS
= 4,
135 AC_UD_SHADER_START
= 5,
136 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
137 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
140 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
145 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
148 struct radv_stream_output
{
152 uint8_t component_mask
;
156 struct radv_streamout_info
{
157 uint16_t num_outputs
;
158 struct radv_stream_output outputs
[MAX_SO_OUTPUTS
];
159 uint16_t strides
[MAX_SO_BUFFERS
];
160 uint32_t enabled_stream_buffers_mask
;
163 struct radv_shader_info
{
164 bool loads_push_constants
;
165 uint32_t desc_set_used_mask
;
166 bool needs_multiview_view_index
;
167 bool uses_invocation_id
;
170 uint64_t ls_outputs_written
;
171 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
172 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
173 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
175 bool needs_instance_id
;
178 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
179 uint8_t num_stream_output_components
[4];
180 uint8_t output_streams
[VARYING_SLOT_VAR31
+ 1];
184 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
187 bool force_persample
;
188 bool needs_sample_positions
;
189 bool uses_input_attachments
;
193 bool writes_sample_mask
;
197 uint8_t num_input_clips_culls
;
201 bool uses_block_id
[3];
202 bool uses_thread_id
[3];
203 bool uses_local_invocation_idx
;
206 uint64_t outputs_written
;
207 uint64_t patch_outputs_written
;
210 struct radv_streamout_info so
;
213 struct radv_userdata_info
{
219 struct radv_userdata_locations
{
220 struct radv_userdata_info descriptor_sets
[RADV_UD_MAX_SETS
];
221 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
222 uint32_t descriptor_sets_enabled
;
225 struct radv_vs_output_info
{
226 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
227 uint8_t clip_dist_mask
;
228 uint8_t cull_dist_mask
;
229 uint8_t param_exports
;
230 bool writes_pointsize
;
232 bool writes_viewport_index
;
234 unsigned pos_exports
;
237 struct radv_es_output_info
{
238 uint32_t esgs_itemsize
;
241 struct radv_shader_variant_info
{
242 struct radv_userdata_locations user_sgprs_locs
;
243 struct radv_shader_info info
;
244 unsigned num_user_sgprs
;
245 unsigned num_input_sgprs
;
246 unsigned num_input_vgprs
;
247 unsigned private_mem_vgprs
;
248 bool need_indirect_descriptor_sets
;
251 struct radv_vs_output_info outinfo
;
252 struct radv_es_output_info es_info
;
253 unsigned vgpr_comp_cnt
;
260 uint32_t flat_shaded_mask
;
262 bool early_fragment_test
;
265 unsigned block_size
[3];
268 unsigned vertices_in
;
269 unsigned vertices_out
;
270 unsigned output_prim
;
271 unsigned invocations
;
272 unsigned gsvs_vertex_size
;
273 unsigned max_gsvs_emit_size
;
274 unsigned es_type
; /* GFX9: VS or TES */
277 unsigned tcs_vertices_out
;
278 uint32_t num_patches
;
282 struct radv_vs_output_info outinfo
;
283 struct radv_es_output_info es_info
;
285 unsigned primitive_mode
;
286 enum gl_tess_spacing spacing
;
293 struct radv_shader_variant
{
296 struct radeon_winsys_bo
*bo
;
298 struct ac_shader_config config
;
300 struct radv_shader_variant_info info
;
307 struct nir_shader
*nir
;
309 char *llvm_ir_string
;
311 struct list_head slab_list
;
314 struct radv_shader_slab
{
315 struct list_head slabs
;
316 struct list_head shaders
;
317 struct radeon_winsys_bo
*bo
;
323 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
327 radv_shader_compile_to_nir(struct radv_device
*device
,
328 struct radv_shader_module
*module
,
329 const char *entrypoint_name
,
330 gl_shader_stage stage
,
331 const VkSpecializationInfo
*spec_info
,
332 const VkPipelineCreateFlags flags
);
335 radv_alloc_shader_memory(struct radv_device
*device
,
336 struct radv_shader_variant
*shader
);
339 radv_destroy_shader_slabs(struct radv_device
*device
);
341 struct radv_shader_variant
*
342 radv_shader_variant_create(struct radv_device
*device
,
343 struct radv_shader_module
*module
,
344 struct nir_shader
*const *shaders
,
346 struct radv_pipeline_layout
*layout
,
347 const struct radv_shader_variant_key
*key
,
349 unsigned *code_size_out
);
351 struct radv_shader_variant
*
352 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
353 void **code_out
, unsigned *code_size_out
,
357 radv_shader_variant_destroy(struct radv_device
*device
,
358 struct radv_shader_variant
*variant
);
361 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
);
364 radv_shader_dump_stats(struct radv_device
*device
,
365 struct radv_shader_variant
*variant
,
366 gl_shader_stage stage
,
370 radv_can_dump_shader(struct radv_device
*device
,
371 struct radv_shader_module
*module
,
372 bool is_gs_copy_shader
)
374 if (!(device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
))
377 /* Only dump non-meta shaders, useful for debugging purposes. */
378 return (module
&& !module
->nir
) || is_gs_copy_shader
;
382 radv_can_dump_shader_stats(struct radv_device
*device
,
383 struct radv_shader_module
*module
)
385 /* Only dump non-meta shader stats. */
386 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
&&
387 module
&& !module
->nir
;
390 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot
)
392 /* handle patch indices separate */
393 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
395 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
397 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
398 return 2 + (slot
- VARYING_SLOT_PATCH0
);
399 if (slot
== VARYING_SLOT_POS
)
401 if (slot
== VARYING_SLOT_PSIZ
)
403 if (slot
== VARYING_SLOT_CLIP_DIST0
)
405 /* 3 is reserved for clip dist as well */
406 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
407 return 4 + (slot
- VARYING_SLOT_VAR0
);
408 unreachable("illegal slot in get unique index\n");
411 static inline uint32_t
412 radv_get_num_physical_sgprs(struct radv_physical_device
*physical_device
)
414 return physical_device
->rad_info
.chip_class
>= VI
? 800 : 512;