src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "radv_debug.h"
  32 #include "radv_private.h"
  33
  34 #include "nir/nir.h"
  35
  36 /* descriptor index into scratch ring offsets */
  37 #define RING_SCRATCH 0
  38 #define RING_ESGS_VS 1
  39 #define RING_ESGS_GS 2
  40 #define RING_GSVS_VS 3
  41 #define RING_GSVS_GS 4
  42 #define RING_HS_TESS_FACTOR 5
  43 #define RING_HS_TESS_OFFCHIP 6
  44 #define RING_PS_SAMPLE_POSITIONS 7
  45
  46 // Match MAX_SETS from radv_descriptor_set.h
  47 #define RADV_UD_MAX_SETS MAX_SETS
  48
  49 #define RADV_NUM_PHYSICAL_VGPRS 256
  50
  51 struct radv_shader_module {
  52         struct nir_shader *nir;
  53         unsigned char sha1[20];
  54         uint32_t size;
  55         char data[0];
  56 };
  57
  58 enum {
  59         RADV_ALPHA_ADJUST_NONE = 0,
  60         RADV_ALPHA_ADJUST_SNORM = 1,
  61         RADV_ALPHA_ADJUST_SINT = 2,
  62         RADV_ALPHA_ADJUST_SSCALED = 3,
  63 };
  64
  65 struct radv_vs_variant_key {
  66         uint32_t instance_rate_inputs;
  67         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  68         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  69         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  70         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  71         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  72
  73         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  74          * so we may need to fix it up. */
  75         uint64_t alpha_adjust;
  76
  77         /* For some formats the channels have to be shuffled. */
  78         uint32_t post_shuffle;
  79
  80         uint32_t as_es:1;
  81         uint32_t as_ls:1;
  82         uint32_t export_prim_id:1;
  83         uint32_t export_layer_id:1;
  84         uint32_t export_clip_dists:1;
  85 };
  86
  87 struct radv_tes_variant_key {
  88         uint32_t as_es:1;
  89         uint32_t export_prim_id:1;
  90         uint32_t export_layer_id:1;
  91         uint32_t export_clip_dists:1;
  92         uint8_t num_patches;
  93         uint8_t tcs_num_outputs;
  94 };
  95
  96 struct radv_tcs_variant_key {
  97         struct radv_vs_variant_key vs_key;
  98         unsigned primitive_mode;
  99         unsigned input_vertices;
 100         unsigned num_inputs;
 101         uint32_t tes_reads_tess_factors:1;
 102 };
 103
 104 struct radv_fs_variant_key {
 105         uint32_t col_format;
 106         uint8_t log2_ps_iter_samples;
 107         uint8_t num_samples;
 108         uint32_t is_int8;
 109         uint32_t is_int10;
 110 };
 111
 112 struct radv_shader_variant_key {
 113         union {
 114                 struct radv_vs_variant_key vs;
 115                 struct radv_fs_variant_key fs;
 116                 struct radv_tes_variant_key tes;
 117                 struct radv_tcs_variant_key tcs;
 118         };
 119         bool has_multiview_view_index;
 120 };
 121
 122 struct radv_nir_compiler_options {
 123         struct radv_pipeline_layout *layout;
 124         struct radv_shader_variant_key key;
 125         bool unsafe_math;
 126         bool supports_spill;
 127         bool clamp_shadow_reference;
 128         bool dump_shader;
 129         bool dump_preoptir;
 130         bool record_llvm_ir;
 131         bool check_ir;
 132         enum radeon_family family;
 133         enum chip_class chip_class;
 134         uint32_t tess_offchip_block_dw_size;
 135         uint32_t address32_hi;
 136 };
 137
 138 enum radv_ud_index {
 139         AC_UD_SCRATCH_RING_OFFSETS = 0,
 140         AC_UD_PUSH_CONSTANTS = 1,
 141         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 142         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 143         AC_UD_VIEW_INDEX = 4,
 144         AC_UD_STREAMOUT_BUFFERS = 5,
 145         AC_UD_SHADER_START = 6,
 146         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 147         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 148         AC_UD_VS_MAX_UD,
 149         AC_UD_PS_MAX_UD,
 150         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 151         AC_UD_CS_MAX_UD,
 152         AC_UD_GS_MAX_UD,
 153         AC_UD_TCS_MAX_UD,
 154         AC_UD_TES_MAX_UD,
 155         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 156 };
 157
 158 struct radv_stream_output {
 159         uint8_t location;
 160         uint8_t buffer;
 161         uint16_t offset;
 162         uint8_t component_mask;
 163         uint8_t stream;
 164 };
 165
 166 struct radv_streamout_info {
 167         uint16_t num_outputs;
 168         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 169         uint16_t strides[MAX_SO_BUFFERS];
 170         uint32_t enabled_stream_buffers_mask;
 171 };
 172
 173 struct radv_shader_info {
 174         bool loads_push_constants;
 175         bool loads_dynamic_offsets;
 176         uint8_t min_push_constant_used;
 177         uint8_t max_push_constant_used;
 178         bool has_only_32bit_push_constants;
 179         bool has_indirect_push_constants;
 180         uint8_t num_inline_push_consts;
 181         uint8_t base_inline_push_consts;
 182         uint32_t desc_set_used_mask;
 183         bool needs_multiview_view_index;
 184         bool uses_invocation_id;
 185         bool uses_prim_id;
 186         struct {
 187                 uint64_t ls_outputs_written;
 188                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 189                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 190                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 191                 bool needs_draw_id;
 192                 bool needs_instance_id;
 193         } vs;
 194         struct {
 195                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 196                 uint8_t num_stream_output_components[4];
 197                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 198                 uint8_t max_stream;
 199         } gs;
 200         struct {
 201                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 202         } tes;
 203         struct {
 204                 bool force_persample;
 205                 bool needs_sample_positions;
 206                 bool uses_input_attachments;
 207                 bool writes_memory;
 208                 bool writes_z;
 209                 bool writes_stencil;
 210                 bool writes_sample_mask;
 211                 bool has_pcoord;
 212                 bool prim_id_input;
 213                 bool layer_input;
 214                 uint8_t num_input_clips_culls;
 215         } ps;
 216         struct {
 217                 bool uses_grid_size;
 218                 bool uses_block_id[3];
 219                 bool uses_thread_id[3];
 220                 bool uses_local_invocation_idx;
 221         } cs;
 222         struct {
 223                 uint64_t outputs_written;
 224                 uint64_t patch_outputs_written;
 225         } tcs;
 226
 227         struct radv_streamout_info so;
 228 };
 229
 230 struct radv_userdata_info {
 231         int8_t sgpr_idx;
 232         uint8_t num_sgprs;
 233 };
 234
 235 struct radv_userdata_locations {
 236         struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
 237         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 238         uint32_t descriptor_sets_enabled;
 239 };
 240
 241 struct radv_vs_output_info {
 242         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 243         uint8_t clip_dist_mask;
 244         uint8_t cull_dist_mask;
 245         uint8_t param_exports;
 246         bool writes_pointsize;
 247         bool writes_layer;
 248         bool writes_viewport_index;
 249         bool export_prim_id;
 250         unsigned pos_exports;
 251 };
 252
 253 struct radv_es_output_info {
 254         uint32_t esgs_itemsize;
 255 };
 256
 257 struct radv_shader_variant_info {
 258         struct radv_userdata_locations user_sgprs_locs;
 259         struct radv_shader_info info;
 260         unsigned num_user_sgprs;
 261         unsigned num_input_sgprs;
 262         unsigned num_input_vgprs;
 263         unsigned private_mem_vgprs;
 264         bool need_indirect_descriptor_sets;
 265         struct {
 266                 struct {
 267                         struct radv_vs_output_info outinfo;
 268                         struct radv_es_output_info es_info;
 269                         bool as_es;
 270                         bool as_ls;
 271                         bool export_prim_id;
 272                 } vs;
 273                 struct {
 274                         unsigned num_interp;
 275                         uint32_t input_mask;
 276                         uint32_t flat_shaded_mask;
 277                         uint32_t float16_shaded_mask;
 278                         bool can_discard;
 279                         bool early_fragment_test;
 280                 } fs;
 281                 struct {
 282                         unsigned block_size[3];
 283                 } cs;
 284                 struct {
 285                         unsigned vertices_in;
 286                         unsigned vertices_out;
 287                         unsigned output_prim;
 288                         unsigned invocations;
 289                         unsigned gsvs_vertex_size;
 290                         unsigned max_gsvs_emit_size;
 291                         unsigned es_type; /* GFX9: VS or TES */
 292                 } gs;
 293                 struct {
 294                         unsigned tcs_vertices_out;
 295                         uint32_t num_patches;
 296                         uint32_t lds_size;
 297                 } tcs;
 298                 struct {
 299                         struct radv_vs_output_info outinfo;
 300                         struct radv_es_output_info es_info;
 301                         bool as_es;
 302                         unsigned primitive_mode;
 303                         enum gl_tess_spacing spacing;
 304                         bool ccw;
 305                         bool point_mode;
 306                         bool export_prim_id;
 307                 } tes;
 308         };
 309 };
 310
 311 struct radv_shader_variant {
 312         uint32_t ref_count;
 313
 314         struct radeon_winsys_bo *bo;
 315         uint64_t bo_offset;
 316         struct ac_shader_config config;
 317         uint32_t code_size;
 318         struct radv_shader_variant_info info;
 319
 320         /* debug only */
 321         uint32_t *spirv;
 322         uint32_t spirv_size;
 323         struct nir_shader *nir;
 324         char *disasm_string;
 325         char *llvm_ir_string;
 326
 327         struct list_head slab_list;
 328 };
 329
 330 struct radv_shader_slab {
 331         struct list_head slabs;
 332         struct list_head shaders;
 333         struct radeon_winsys_bo *bo;
 334         uint64_t size;
 335         char *ptr;
 336 };
 337
 338 void
 339 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 340                   bool allow_copies);
 341 bool
 342 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 343                              const struct radv_pipeline_layout *layout);
 344
 345 nir_shader *
 346 radv_shader_compile_to_nir(struct radv_device *device,
 347                            struct radv_shader_module *module,
 348                            const char *entrypoint_name,
 349                            gl_shader_stage stage,
 350                            const VkSpecializationInfo *spec_info,
 351                            const VkPipelineCreateFlags flags,
 352                            const struct radv_pipeline_layout *layout);
 353
 354 void *
 355 radv_alloc_shader_memory(struct radv_device *device,
 356                           struct radv_shader_variant *shader);
 357
 358 void
 359 radv_destroy_shader_slabs(struct radv_device *device);
 360
 361 struct radv_shader_variant *
 362 radv_shader_variant_create(struct radv_device *device,
 363                            struct radv_shader_module *module,
 364                            struct nir_shader *const *shaders,
 365                            int shader_count,
 366                            struct radv_pipeline_layout *layout,
 367                            const struct radv_shader_variant_key *key,
 368                            void **code_out,
 369                            unsigned *code_size_out);
 370
 371 struct radv_shader_variant *
 372 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 373                            void **code_out, unsigned *code_size_out,
 374                            bool multiview);
 375
 376 void
 377 radv_shader_variant_destroy(struct radv_device *device,
 378                             struct radv_shader_variant *variant);
 379
 380 const char *
 381 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);
 382
 383 void
 384 radv_shader_dump_stats(struct radv_device *device,
 385                        struct radv_shader_variant *variant,
 386                        gl_shader_stage stage,
 387                        FILE *file);
 388
 389 static inline bool
 390 radv_can_dump_shader(struct radv_device *device,
 391                      struct radv_shader_module *module,
 392                      bool is_gs_copy_shader)
 393 {
 394         if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
 395                 return false;
 396
 397         /* Only dump non-meta shaders, useful for debugging purposes. */
 398         return (module && !module->nir) || is_gs_copy_shader;
 399 }
 400
 401 static inline bool
 402 radv_can_dump_shader_stats(struct radv_device *device,
 403                            struct radv_shader_module *module)
 404 {
 405         /* Only dump non-meta shader stats. */
 406         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
 407                module && !module->nir;
 408 }
 409
 410 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
 411 {
 412         /* handle patch indices separate */
 413         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 414                 return 0;
 415         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 416                 return 1;
 417         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 418                 return 2 + (slot - VARYING_SLOT_PATCH0);
 419         if (slot == VARYING_SLOT_POS)
 420                 return 0;
 421         if (slot == VARYING_SLOT_PSIZ)
 422                 return 1;
 423         if (slot == VARYING_SLOT_CLIP_DIST0)
 424                 return 2;
 425         if (slot == VARYING_SLOT_CLIP_DIST1)
 426                 return 3;
 427         /* 3 is reserved for clip dist as well */
 428         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 429                 return 4 + (slot - VARYING_SLOT_VAR0);
 430         unreachable("illegal slot in get unique index\n");
 431 }
 432
 433 #endif