src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "radv_debug.h"
  32 #include "radv_private.h"
  33
  34 #include "nir/nir.h"
  35
  36 /* descriptor index into scratch ring offsets */
  37 #define RING_SCRATCH 0
  38 #define RING_ESGS_VS 1
  39 #define RING_ESGS_GS 2
  40 #define RING_GSVS_VS 3
  41 #define RING_GSVS_GS 4
  42 #define RING_HS_TESS_FACTOR 5
  43 #define RING_HS_TESS_OFFCHIP 6
  44 #define RING_PS_SAMPLE_POSITIONS 7
  45
  46 // Match MAX_SETS from radv_descriptor_set.h
  47 #define RADV_UD_MAX_SETS MAX_SETS
  48
  49 #define RADV_NUM_PHYSICAL_VGPRS 256
  50
  51 struct radv_shader_module {
  52         struct nir_shader *nir;
  53         unsigned char sha1[20];
  54         uint32_t size;
  55         char data[0];
  56 };
  57
  58 enum {
  59         RADV_ALPHA_ADJUST_NONE = 0,
  60         RADV_ALPHA_ADJUST_SNORM = 1,
  61         RADV_ALPHA_ADJUST_SINT = 2,
  62         RADV_ALPHA_ADJUST_SSCALED = 3,
  63 };
  64
  65 struct radv_vs_out_key {
  66         uint32_t as_es:1;
  67         uint32_t as_ls:1;
  68         uint32_t as_ngg:1;
  69         uint32_t export_prim_id:1;
  70         uint32_t export_layer_id:1;
  71         uint32_t export_clip_dists:1;
  72 };
  73
  74 struct radv_vs_variant_key {
  75         struct radv_vs_out_key out;
  76
  77         uint32_t instance_rate_inputs;
  78         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  79         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  80         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  81         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  82         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  83
  84         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  85          * so we may need to fix it up. */
  86         uint64_t alpha_adjust;
  87
  88         /* For some formats the channels have to be shuffled. */
  89         uint32_t post_shuffle;
  90 };
  91
  92 struct radv_tes_variant_key {
  93         struct radv_vs_out_key out;
  94
  95         uint8_t num_patches;
  96         uint8_t tcs_num_outputs;
  97 };
  98
  99 struct radv_tcs_variant_key {
 100         struct radv_vs_variant_key vs_key;
 101         unsigned primitive_mode;
 102         unsigned input_vertices;
 103         unsigned num_inputs;
 104         uint32_t tes_reads_tess_factors:1;
 105 };
 106
 107 struct radv_fs_variant_key {
 108         uint32_t col_format;
 109         uint8_t log2_ps_iter_samples;
 110         uint8_t num_samples;
 111         uint32_t is_int8;
 112         uint32_t is_int10;
 113 };
 114
 115
 116 struct radv_gs_variant_key {
 117         uint32_t as_ngg:1;
 118 };
 119
 120 struct radv_shader_variant_key {
 121         union {
 122                 struct radv_vs_variant_key vs;
 123                 struct radv_fs_variant_key fs;
 124                 struct radv_tes_variant_key tes;
 125                 struct radv_tcs_variant_key tcs;
 126                 struct radv_gs_variant_key gs;
 127         };
 128         bool has_multiview_view_index;
 129 };
 130
 131 struct radv_nir_compiler_options {
 132         struct radv_pipeline_layout *layout;
 133         struct radv_shader_variant_key key;
 134         bool unsafe_math;
 135         bool supports_spill;
 136         bool clamp_shadow_reference;
 137         bool dump_shader;
 138         bool dump_preoptir;
 139         bool record_llvm_ir;
 140         bool check_ir;
 141         enum radeon_family family;
 142         enum chip_class chip_class;
 143         uint32_t tess_offchip_block_dw_size;
 144         uint32_t address32_hi;
 145 };
 146
 147 enum radv_ud_index {
 148         AC_UD_SCRATCH_RING_OFFSETS = 0,
 149         AC_UD_PUSH_CONSTANTS = 1,
 150         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 151         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 152         AC_UD_VIEW_INDEX = 4,
 153         AC_UD_STREAMOUT_BUFFERS = 5,
 154         AC_UD_SHADER_START = 6,
 155         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 156         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 157         AC_UD_VS_MAX_UD,
 158         AC_UD_PS_MAX_UD,
 159         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 160         AC_UD_CS_MAX_UD,
 161         AC_UD_GS_MAX_UD,
 162         AC_UD_TCS_MAX_UD,
 163         AC_UD_TES_MAX_UD,
 164         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 165 };
 166
 167 struct radv_stream_output {
 168         uint8_t location;
 169         uint8_t buffer;
 170         uint16_t offset;
 171         uint8_t component_mask;
 172         uint8_t stream;
 173 };
 174
 175 struct radv_streamout_info {
 176         uint16_t num_outputs;
 177         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 178         uint16_t strides[MAX_SO_BUFFERS];
 179         uint32_t enabled_stream_buffers_mask;
 180 };
 181
 182 struct radv_shader_info {
 183         bool loads_push_constants;
 184         bool loads_dynamic_offsets;
 185         uint8_t min_push_constant_used;
 186         uint8_t max_push_constant_used;
 187         bool has_only_32bit_push_constants;
 188         bool has_indirect_push_constants;
 189         uint8_t num_inline_push_consts;
 190         uint8_t base_inline_push_consts;
 191         uint32_t desc_set_used_mask;
 192         bool needs_multiview_view_index;
 193         bool uses_invocation_id;
 194         bool uses_prim_id;
 195         struct {
 196                 uint64_t ls_outputs_written;
 197                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 198                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 199                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 200                 bool needs_draw_id;
 201                 bool needs_instance_id;
 202         } vs;
 203         struct {
 204                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 205                 uint8_t num_stream_output_components[4];
 206                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 207                 uint8_t max_stream;
 208         } gs;
 209         struct {
 210                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 211         } tes;
 212         struct {
 213                 bool force_persample;
 214                 bool needs_sample_positions;
 215                 bool writes_memory;
 216                 bool writes_z;
 217                 bool writes_stencil;
 218                 bool writes_sample_mask;
 219                 bool has_pcoord;
 220                 bool prim_id_input;
 221                 bool layer_input;
 222                 uint8_t num_input_clips_culls;
 223         } ps;
 224         struct {
 225                 bool uses_grid_size;
 226                 bool uses_block_id[3];
 227                 bool uses_thread_id[3];
 228                 bool uses_local_invocation_idx;
 229         } cs;
 230         struct {
 231                 uint64_t outputs_written;
 232                 uint64_t patch_outputs_written;
 233         } tcs;
 234
 235         struct radv_streamout_info so;
 236 };
 237
 238 struct radv_userdata_info {
 239         int8_t sgpr_idx;
 240         uint8_t num_sgprs;
 241 };
 242
 243 struct radv_userdata_locations {
 244         struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
 245         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 246         uint32_t descriptor_sets_enabled;
 247 };
 248
 249 struct radv_vs_output_info {
 250         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 251         uint8_t clip_dist_mask;
 252         uint8_t cull_dist_mask;
 253         uint8_t param_exports;
 254         bool writes_pointsize;
 255         bool writes_layer;
 256         bool writes_viewport_index;
 257         bool export_prim_id;
 258         unsigned pos_exports;
 259 };
 260
 261 struct radv_es_output_info {
 262         uint32_t esgs_itemsize;
 263 };
 264
 265 struct radv_shader_variant_info {
 266         struct radv_userdata_locations user_sgprs_locs;
 267         struct radv_shader_info info;
 268         unsigned num_user_sgprs;
 269         unsigned num_input_sgprs;
 270         unsigned num_input_vgprs;
 271         unsigned private_mem_vgprs;
 272         bool need_indirect_descriptor_sets;
 273         bool is_ngg;
 274         struct {
 275                 struct {
 276                         struct radv_vs_output_info outinfo;
 277                         struct radv_es_output_info es_info;
 278                         bool as_es;
 279                         bool as_ls;
 280                         bool export_prim_id;
 281                 } vs;
 282                 struct {
 283                         unsigned num_interp;
 284                         uint32_t input_mask;
 285                         uint32_t flat_shaded_mask;
 286                         uint32_t float16_shaded_mask;
 287                         bool can_discard;
 288                         bool early_fragment_test;
 289                 } fs;
 290                 struct {
 291                         unsigned block_size[3];
 292                 } cs;
 293                 struct {
 294                         unsigned vertices_in;
 295                         unsigned vertices_out;
 296                         unsigned output_prim;
 297                         unsigned invocations;
 298                         unsigned gsvs_vertex_size;
 299                         unsigned max_gsvs_emit_size;
 300                         unsigned es_type; /* GFX9: VS or TES */
 301                 } gs;
 302                 struct {
 303                         unsigned tcs_vertices_out;
 304                         uint32_t num_patches;
 305                         uint32_t lds_size;
 306                 } tcs;
 307                 struct {
 308                         struct radv_vs_output_info outinfo;
 309                         struct radv_es_output_info es_info;
 310                         bool as_es;
 311                         unsigned primitive_mode;
 312                         enum gl_tess_spacing spacing;
 313                         bool ccw;
 314                         bool point_mode;
 315                         bool export_prim_id;
 316                 } tes;
 317         };
 318 };
 319
 320 enum radv_shader_binary_type {
 321         RADV_BINARY_TYPE_LEGACY,
 322         RADV_BINARY_TYPE_RTLD
 323 };
 324
 325 struct radv_shader_binary {
 326         enum radv_shader_binary_type type;
 327         gl_shader_stage stage;
 328         bool is_gs_copy_shader;
 329
 330         struct radv_shader_variant_info variant_info;
 331
 332         /* Self-referential size so we avoid consistency issues. */
 333         uint32_t total_size;
 334 };
 335
 336 struct radv_shader_binary_legacy {
 337         struct radv_shader_binary base;
 338         struct ac_shader_config config;
 339         unsigned code_size;
 340         unsigned llvm_ir_size;
 341         unsigned disasm_size;
 342
 343         /* data has size of code_size + llvm_ir_size + disasm_size + 2, where
 344          * the +2 is for 0 of the ir strings. */
 345         uint8_t data[0];
 346 };
 347
 348 struct radv_shader_binary_rtld {
 349         struct radv_shader_binary base;
 350         unsigned elf_size;
 351         unsigned llvm_ir_size;
 352         uint8_t data[0];
 353 };
 354
 355 struct radv_shader_variant {
 356         uint32_t ref_count;
 357
 358         struct radeon_winsys_bo *bo;
 359         uint64_t bo_offset;
 360         struct ac_shader_config config;
 361         uint32_t code_size;
 362         struct radv_shader_variant_info info;
 363
 364         /* debug only */
 365         uint32_t *spirv;
 366         uint32_t spirv_size;
 367         struct nir_shader *nir;
 368         char *disasm_string;
 369         char *llvm_ir_string;
 370
 371         struct list_head slab_list;
 372 };
 373
 374 struct radv_shader_slab {
 375         struct list_head slabs;
 376         struct list_head shaders;
 377         struct radeon_winsys_bo *bo;
 378         uint64_t size;
 379         char *ptr;
 380 };
 381
 382 void
 383 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 384                   bool allow_copies);
 385 bool
 386 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 387                              const struct radv_pipeline_layout *layout);
 388
 389 nir_shader *
 390 radv_shader_compile_to_nir(struct radv_device *device,
 391                            struct radv_shader_module *module,
 392                            const char *entrypoint_name,
 393                            gl_shader_stage stage,
 394                            const VkSpecializationInfo *spec_info,
 395                            const VkPipelineCreateFlags flags,
 396                            const struct radv_pipeline_layout *layout);
 397
 398 void *
 399 radv_alloc_shader_memory(struct radv_device *device,
 400                           struct radv_shader_variant *shader);
 401
 402 void
 403 radv_destroy_shader_slabs(struct radv_device *device);
 404
 405 struct radv_shader_variant *
 406 radv_shader_variant_create(struct radv_device *device,
 407                            const struct radv_shader_binary *binary);
 408 struct radv_shader_variant *
 409 radv_shader_variant_compile(struct radv_device *device,
 410                             struct radv_shader_module *module,
 411                             struct nir_shader *const *shaders,
 412                             int shader_count,
 413                             struct radv_pipeline_layout *layout,
 414                             const struct radv_shader_variant_key *key,
 415                             struct radv_shader_binary **binary_out);
 416
 417 struct radv_shader_variant *
 418 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 419                            struct radv_shader_binary **binary_out,
 420                            bool multiview);
 421
 422 void
 423 radv_shader_variant_destroy(struct radv_device *device,
 424                             struct radv_shader_variant *variant);
 425
 426 const char *
 427 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);
 428
 429 void
 430 radv_shader_dump_stats(struct radv_device *device,
 431                        struct radv_shader_variant *variant,
 432                        gl_shader_stage stage,
 433                        FILE *file);
 434
 435 static inline bool
 436 radv_can_dump_shader(struct radv_device *device,
 437                      struct radv_shader_module *module,
 438                      bool is_gs_copy_shader)
 439 {
 440         if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
 441                 return false;
 442
 443         /* Only dump non-meta shaders, useful for debugging purposes. */
 444         return (module && !module->nir) || is_gs_copy_shader;
 445 }
 446
 447 static inline bool
 448 radv_can_dump_shader_stats(struct radv_device *device,
 449                            struct radv_shader_module *module)
 450 {
 451         /* Only dump non-meta shader stats. */
 452         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
 453                module && !module->nir;
 454 }
 455
 456 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
 457 {
 458         /* handle patch indices separate */
 459         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 460                 return 0;
 461         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 462                 return 1;
 463         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 464                 return 2 + (slot - VARYING_SLOT_PATCH0);
 465         if (slot == VARYING_SLOT_POS)
 466                 return 0;
 467         if (slot == VARYING_SLOT_PSIZ)
 468                 return 1;
 469         if (slot == VARYING_SLOT_CLIP_DIST0)
 470                 return 2;
 471         if (slot == VARYING_SLOT_CLIP_DIST1)
 472                 return 3;
 473         /* 3 is reserved for clip dist as well */
 474         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 475                 return 4 + (slot - VARYING_SLOT_VAR0);
 476         unreachable("illegal slot in get unique index\n");
 477 }
 478
 479 #endif