2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_binary.h"
32 #include "amd_family.h"
33 #include "radv_constants.h"
36 #include "vulkan/vulkan.h"
40 struct radv_shader_module
{
41 struct nir_shader
*nir
;
42 unsigned char sha1
[20];
48 RADV_ALPHA_ADJUST_NONE
= 0,
49 RADV_ALPHA_ADJUST_SNORM
= 1,
50 RADV_ALPHA_ADJUST_SINT
= 2,
51 RADV_ALPHA_ADJUST_SSCALED
= 3,
54 struct radv_vs_out_key
{
58 uint32_t as_ngg_passthrough
:1;
59 uint32_t export_prim_id
:1;
60 uint32_t export_layer_id
:1;
61 uint32_t export_clip_dists
:1;
62 uint32_t export_viewport_index
:1;
65 struct radv_vs_variant_key
{
66 struct radv_vs_out_key out
;
68 uint32_t instance_rate_inputs
;
69 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
70 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
71 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
72 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
73 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
75 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
76 * so we may need to fix it up. */
77 uint64_t alpha_adjust
;
79 /* For some formats the channels have to be shuffled. */
80 uint32_t post_shuffle
;
82 /* Output primitive type. */
86 struct radv_tes_variant_key
{
87 struct radv_vs_out_key out
;
90 uint8_t tcs_num_outputs
;
93 struct radv_tcs_variant_key
{
94 struct radv_vs_variant_key vs_key
;
95 unsigned primitive_mode
;
96 unsigned input_vertices
;
98 uint32_t tes_reads_tess_factors
:1;
101 struct radv_fs_variant_key
{
103 uint8_t log2_ps_iter_samples
;
109 struct radv_cs_variant_key
{
110 uint8_t subgroup_size
;
113 struct radv_shader_variant_key
{
115 struct radv_vs_variant_key vs
;
116 struct radv_fs_variant_key fs
;
117 struct radv_tes_variant_key tes
;
118 struct radv_tcs_variant_key tcs
;
119 struct radv_cs_variant_key cs
;
121 /* A common prefix of the vs and tes keys. */
122 struct radv_vs_out_key vs_common_out
;
124 bool has_multiview_view_index
;
127 struct radv_nir_compiler_options
{
128 struct radv_pipeline_layout
*layout
;
129 struct radv_shader_variant_key key
;
130 bool explicit_scratch_args
;
131 bool clamp_shadow_reference
;
132 bool robust_buffer_access
;
138 bool has_ls_vgpr_init_bug
;
139 bool use_ngg_streamout
;
140 enum radeon_family family
;
141 enum chip_class chip_class
;
142 uint32_t tess_offchip_block_dw_size
;
143 uint32_t address32_hi
;
147 AC_UD_SCRATCH_RING_OFFSETS
= 0,
148 AC_UD_PUSH_CONSTANTS
= 1,
149 AC_UD_INLINE_PUSH_CONSTANTS
= 2,
150 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 3,
151 AC_UD_VIEW_INDEX
= 4,
152 AC_UD_STREAMOUT_BUFFERS
= 5,
153 AC_UD_NGG_GS_STATE
= 6,
154 AC_UD_SHADER_START
= 7,
155 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
156 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
159 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
164 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
167 struct radv_stream_output
{
171 uint8_t component_mask
;
175 struct radv_streamout_info
{
176 uint16_t num_outputs
;
177 struct radv_stream_output outputs
[MAX_SO_OUTPUTS
];
178 uint16_t strides
[MAX_SO_BUFFERS
];
179 uint32_t enabled_stream_buffers_mask
;
182 struct radv_userdata_info
{
187 struct radv_userdata_locations
{
188 struct radv_userdata_info descriptor_sets
[MAX_SETS
];
189 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
190 uint32_t descriptor_sets_enabled
;
193 struct radv_vs_output_info
{
194 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
195 uint8_t clip_dist_mask
;
196 uint8_t cull_dist_mask
;
197 uint8_t param_exports
;
198 bool writes_pointsize
;
200 bool writes_viewport_index
;
202 unsigned pos_exports
;
205 struct radv_es_output_info
{
206 uint32_t esgs_itemsize
;
209 struct gfx9_gs_info
{
210 uint32_t vgt_gs_onchip_cntl
;
211 uint32_t vgt_gs_max_prims_per_subgroup
;
212 uint32_t vgt_esgs_ring_itemsize
;
216 struct gfx10_ngg_info
{
217 uint16_t ngg_emit_size
; /* in dwords */
218 uint32_t hw_max_esverts
;
219 uint32_t max_gsprims
;
220 uint32_t max_out_verts
;
221 uint32_t prim_amp_factor
;
222 uint32_t vgt_esgs_ring_itemsize
;
223 uint32_t esgs_ring_size
;
224 bool max_vert_out_per_gs_instance
;
227 struct radv_shader_info
{
228 bool loads_push_constants
;
229 bool loads_dynamic_offsets
;
230 uint8_t min_push_constant_used
;
231 uint8_t max_push_constant_used
;
232 bool has_only_32bit_push_constants
;
233 bool has_indirect_push_constants
;
234 uint8_t num_inline_push_consts
;
235 uint8_t base_inline_push_consts
;
236 uint32_t desc_set_used_mask
;
237 bool needs_multiview_view_index
;
238 bool uses_invocation_id
;
241 uint8_t ballot_bit_size
;
242 struct radv_userdata_locations user_sgprs_locs
;
243 unsigned num_user_sgprs
;
244 unsigned num_input_sgprs
;
245 unsigned num_input_vgprs
;
246 unsigned private_mem_vgprs
;
247 bool need_indirect_descriptor_sets
;
249 bool is_ngg_passthrough
;
251 uint64_t ls_outputs_written
;
252 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
253 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
254 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
256 bool needs_instance_id
;
257 struct radv_vs_output_info outinfo
;
258 struct radv_es_output_info es_info
;
264 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
265 uint8_t num_stream_output_components
[4];
266 uint8_t output_streams
[VARYING_SLOT_VAR31
+ 1];
269 unsigned gsvs_vertex_size
;
270 unsigned max_gsvs_emit_size
;
271 unsigned vertices_in
;
272 unsigned vertices_out
;
273 unsigned output_prim
;
274 unsigned invocations
;
275 unsigned es_type
; /* GFX9: VS or TES */
278 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
279 struct radv_vs_output_info outinfo
;
280 struct radv_es_output_info es_info
;
282 unsigned primitive_mode
;
283 enum gl_tess_spacing spacing
;
289 bool force_persample
;
290 bool needs_sample_positions
;
294 bool writes_sample_mask
;
298 bool viewport_index_input
;
299 uint8_t num_input_clips_culls
;
301 uint32_t flat_shaded_mask
;
302 uint32_t explicit_shaded_mask
;
303 uint32_t float16_shaded_mask
;
306 bool early_fragment_test
;
307 bool post_depth_coverage
;
311 bool uses_block_id
[3];
312 bool uses_thread_id
[3];
313 bool uses_local_invocation_idx
;
314 unsigned block_size
[3];
317 uint64_t outputs_written
;
318 uint64_t patch_outputs_written
;
319 unsigned tcs_vertices_out
;
320 uint32_t num_patches
;
324 struct radv_streamout_info so
;
326 struct gfx9_gs_info gs_ring_info
;
327 struct gfx10_ngg_info ngg_info
;
329 unsigned float_controls_mode
;
332 enum radv_shader_binary_type
{
333 RADV_BINARY_TYPE_LEGACY
,
334 RADV_BINARY_TYPE_RTLD
337 struct radv_shader_binary
{
338 enum radv_shader_binary_type type
;
339 gl_shader_stage stage
;
340 bool is_gs_copy_shader
;
342 struct radv_shader_info info
;
344 /* Self-referential size so we avoid consistency issues. */
348 struct radv_shader_binary_legacy
{
349 struct radv_shader_binary base
;
350 struct ac_shader_config config
;
354 unsigned disasm_size
;
357 /* data has size of stats_size + code_size + ir_size + disasm_size + 2,
358 * where the +2 is for 0 of the ir strings. */
362 struct radv_shader_binary_rtld
{
363 struct radv_shader_binary base
;
365 unsigned llvm_ir_size
;
369 struct radv_compiler_statistic_info
{
374 struct radv_compiler_statistics
{
376 struct radv_compiler_statistic_info
*infos
;
380 struct radv_shader_variant
{
383 struct radeon_winsys_bo
*bo
;
385 struct ac_shader_config config
;
388 struct radv_shader_info info
;
396 struct radv_compiler_statistics
*statistics
;
398 struct list_head slab_list
;
401 struct radv_shader_slab
{
402 struct list_head slabs
;
403 struct list_head shaders
;
404 struct radeon_winsys_bo
*bo
;
410 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
413 radv_nir_lower_ycbcr_textures(nir_shader
*shader
,
414 const struct radv_pipeline_layout
*layout
);
417 radv_shader_compile_to_nir(struct radv_device
*device
,
418 struct radv_shader_module
*module
,
419 const char *entrypoint_name
,
420 gl_shader_stage stage
,
421 const VkSpecializationInfo
*spec_info
,
422 const VkPipelineCreateFlags flags
,
423 const struct radv_pipeline_layout
*layout
,
424 unsigned subgroup_size
, unsigned ballot_bit_size
);
427 radv_alloc_shader_memory(struct radv_device
*device
,
428 struct radv_shader_variant
*shader
);
431 radv_destroy_shader_slabs(struct radv_device
*device
);
434 radv_create_shaders(struct radv_pipeline
*pipeline
,
435 struct radv_device
*device
,
436 struct radv_pipeline_cache
*cache
,
437 const struct radv_pipeline_key
*key
,
438 const VkPipelineShaderStageCreateInfo
**pStages
,
439 const VkPipelineCreateFlags flags
,
440 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
441 VkPipelineCreationFeedbackEXT
**stage_feedbacks
);
443 struct radv_shader_variant
*
444 radv_shader_variant_create(struct radv_device
*device
,
445 const struct radv_shader_binary
*binary
,
446 bool keep_shader_info
);
447 struct radv_shader_variant
*
448 radv_shader_variant_compile(struct radv_device
*device
,
449 struct radv_shader_module
*module
,
450 struct nir_shader
*const *shaders
,
452 struct radv_pipeline_layout
*layout
,
453 const struct radv_shader_variant_key
*key
,
454 struct radv_shader_info
*info
,
455 bool keep_shader_info
, bool keep_statistic_info
,
456 struct radv_shader_binary
**binary_out
);
458 struct radv_shader_variant
*
459 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
460 struct radv_shader_info
*info
,
461 struct radv_shader_binary
**binary_out
,
462 bool multiview
, bool keep_shader_info
,
463 bool keep_statistic_info
);
466 radv_shader_variant_destroy(struct radv_device
*device
,
467 struct radv_shader_variant
*variant
);
471 radv_get_max_waves(struct radv_device
*device
,
472 struct radv_shader_variant
*variant
,
473 gl_shader_stage stage
);
476 radv_get_max_workgroup_size(enum chip_class chip_class
,
477 gl_shader_stage stage
,
478 const unsigned *sizes
);
481 radv_get_shader_name(struct radv_shader_info
*info
,
482 gl_shader_stage stage
);
485 radv_shader_dump_stats(struct radv_device
*device
,
486 struct radv_shader_variant
*variant
,
487 gl_shader_stage stage
,
491 radv_can_dump_shader(struct radv_device
*device
,
492 struct radv_shader_module
*module
,
493 bool is_gs_copy_shader
);
496 radv_can_dump_shader_stats(struct radv_device
*device
,
497 struct radv_shader_module
*module
);
499 static inline unsigned
500 shader_io_get_unique_index(gl_varying_slot slot
)
502 /* handle patch indices separate */
503 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
505 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
507 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
508 return 2 + (slot
- VARYING_SLOT_PATCH0
);
509 if (slot
== VARYING_SLOT_POS
)
511 if (slot
== VARYING_SLOT_PSIZ
)
513 if (slot
== VARYING_SLOT_CLIP_DIST0
)
515 if (slot
== VARYING_SLOT_CLIP_DIST1
)
517 /* 3 is reserved for clip dist as well */
518 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
519 return 4 + (slot
- VARYING_SLOT_VAR0
);
520 unreachable("illegal slot in get unique index\n");
523 static inline unsigned
524 calculate_tess_lds_size(unsigned tcs_num_input_vertices
,
525 unsigned tcs_num_output_vertices
,
526 unsigned tcs_num_inputs
,
527 unsigned tcs_num_patches
,
528 unsigned tcs_outputs_written
,
529 unsigned tcs_per_patch_outputs_written
)
531 unsigned num_tcs_outputs
= util_last_bit64(tcs_outputs_written
);
532 unsigned num_tcs_patch_outputs
= util_last_bit64(tcs_per_patch_outputs_written
);
534 unsigned input_vertex_size
= tcs_num_inputs
* 16;
535 unsigned output_vertex_size
= num_tcs_outputs
* 16;
537 unsigned input_patch_size
= tcs_num_input_vertices
* input_vertex_size
;
539 unsigned pervertex_output_patch_size
= tcs_num_output_vertices
* output_vertex_size
;
540 unsigned output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
542 unsigned output_patch0_offset
= input_patch_size
* tcs_num_patches
;
544 return output_patch0_offset
+ output_patch_size
* tcs_num_patches
;
547 static inline unsigned
548 get_tcs_num_patches(unsigned tcs_num_input_vertices
,
549 unsigned tcs_num_output_vertices
,
550 unsigned tcs_num_inputs
,
551 unsigned tcs_outputs_written
,
552 unsigned tcs_per_patch_outputs_written
,
553 unsigned tess_offchip_block_dw_size
,
554 enum chip_class chip_class
,
555 enum radeon_family family
)
557 uint32_t input_vertex_size
= tcs_num_inputs
* 16;
558 uint32_t input_patch_size
= tcs_num_input_vertices
* input_vertex_size
;
559 uint32_t num_tcs_outputs
= util_last_bit64(tcs_outputs_written
);
560 uint32_t num_tcs_patch_outputs
= util_last_bit64(tcs_per_patch_outputs_written
);
561 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
562 uint32_t pervertex_output_patch_size
= tcs_num_output_vertices
* output_vertex_size
;
563 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
565 /* Ensure that we only need one wave per SIMD so we don't need to check
566 * resource usage. Also ensures that the number of tcs in and out
567 * vertices per threadgroup are at most 256.
569 unsigned num_patches
= 64 / MAX2(tcs_num_input_vertices
, tcs_num_output_vertices
) * 4;
570 /* Make sure that the data fits in LDS. This assumes the shaders only
571 * use LDS for the inputs and outputs.
573 unsigned hardware_lds_size
= 32768;
575 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
576 * threadgroup, even though there is more than 32 KiB LDS.
578 * Test: dEQP-VK.tessellation.shader_input_output.barrier
580 if (chip_class
>= GFX7
&& family
!= CHIP_STONEY
)
581 hardware_lds_size
= 65536;
583 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
584 /* Make sure the output data fits in the offchip buffer */
585 num_patches
= MIN2(num_patches
, (tess_offchip_block_dw_size
* 4) / output_patch_size
);
586 /* Not necessary for correctness, but improves performance. The
587 * specific value is taken from the proprietary driver.
589 num_patches
= MIN2(num_patches
, 40);
591 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
592 if (chip_class
== GFX6
) {
593 unsigned one_wave
= 64 / MAX2(tcs_num_input_vertices
, tcs_num_output_vertices
);
594 num_patches
= MIN2(num_patches
, one_wave
);
600 radv_lower_fs_io(nir_shader
*nir
);