2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "radv_debug.h"
32 #include "radv_private.h"
36 /* descriptor index into scratch ring offsets */
37 #define RING_SCRATCH 0
38 #define RING_ESGS_VS 1
39 #define RING_ESGS_GS 2
40 #define RING_GSVS_VS 3
41 #define RING_GSVS_GS 4
42 #define RING_HS_TESS_FACTOR 5
43 #define RING_HS_TESS_OFFCHIP 6
44 #define RING_PS_SAMPLE_POSITIONS 7
46 // Match MAX_SETS from radv_descriptor_set.h
47 #define RADV_UD_MAX_SETS MAX_SETS
49 #define RADV_NUM_PHYSICAL_VGPRS 256
51 struct radv_shader_module
{
52 struct nir_shader
*nir
;
53 unsigned char sha1
[20];
59 RADV_ALPHA_ADJUST_NONE
= 0,
60 RADV_ALPHA_ADJUST_SNORM
= 1,
61 RADV_ALPHA_ADJUST_SINT
= 2,
62 RADV_ALPHA_ADJUST_SSCALED
= 3,
65 struct radv_vs_variant_key
{
66 uint32_t instance_rate_inputs
;
67 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
68 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
69 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
70 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
71 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
73 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
74 * so we may need to fix it up. */
75 uint64_t alpha_adjust
;
77 /* For some formats the channels have to be shuffled. */
78 uint32_t post_shuffle
;
82 uint32_t export_prim_id
:1;
83 uint32_t export_layer_id
:1;
84 uint32_t export_clip_dists
:1;
87 struct radv_tes_variant_key
{
89 uint32_t export_prim_id
:1;
90 uint32_t export_layer_id
:1;
91 uint32_t export_clip_dists
:1;
93 uint8_t tcs_num_outputs
;
96 struct radv_tcs_variant_key
{
97 struct radv_vs_variant_key vs_key
;
98 unsigned primitive_mode
;
99 unsigned input_vertices
;
101 uint32_t tes_reads_tess_factors
:1;
104 struct radv_fs_variant_key
{
106 uint8_t log2_ps_iter_samples
;
112 struct radv_shader_variant_key
{
114 struct radv_vs_variant_key vs
;
115 struct radv_fs_variant_key fs
;
116 struct radv_tes_variant_key tes
;
117 struct radv_tcs_variant_key tcs
;
119 bool has_multiview_view_index
;
122 struct radv_nir_compiler_options
{
123 struct radv_pipeline_layout
*layout
;
124 struct radv_shader_variant_key key
;
127 bool clamp_shadow_reference
;
132 enum radeon_family family
;
133 enum chip_class chip_class
;
134 uint32_t tess_offchip_block_dw_size
;
135 uint32_t address32_hi
;
139 AC_UD_SCRATCH_RING_OFFSETS
= 0,
140 AC_UD_PUSH_CONSTANTS
= 1,
141 AC_UD_INLINE_PUSH_CONSTANTS
= 2,
142 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 3,
143 AC_UD_VIEW_INDEX
= 4,
144 AC_UD_STREAMOUT_BUFFERS
= 5,
145 AC_UD_SHADER_START
= 6,
146 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
147 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
150 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
155 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
158 struct radv_stream_output
{
162 uint8_t component_mask
;
166 struct radv_streamout_info
{
167 uint16_t num_outputs
;
168 struct radv_stream_output outputs
[MAX_SO_OUTPUTS
];
169 uint16_t strides
[MAX_SO_BUFFERS
];
170 uint32_t enabled_stream_buffers_mask
;
173 struct radv_shader_info
{
174 bool loads_push_constants
;
175 bool loads_dynamic_offsets
;
176 uint8_t min_push_constant_used
;
177 uint8_t max_push_constant_used
;
178 bool has_only_32bit_push_constants
;
179 bool has_indirect_push_constants
;
180 uint8_t num_inline_push_consts
;
181 uint8_t base_inline_push_consts
;
182 uint32_t desc_set_used_mask
;
183 bool needs_multiview_view_index
;
184 bool uses_invocation_id
;
187 uint64_t ls_outputs_written
;
188 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
189 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
190 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
192 bool needs_instance_id
;
195 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
196 uint8_t num_stream_output_components
[4];
197 uint8_t output_streams
[VARYING_SLOT_VAR31
+ 1];
201 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
204 bool force_persample
;
205 bool needs_sample_positions
;
206 bool uses_input_attachments
;
210 bool writes_sample_mask
;
214 uint8_t num_input_clips_culls
;
218 bool uses_block_id
[3];
219 bool uses_thread_id
[3];
220 bool uses_local_invocation_idx
;
223 uint64_t outputs_written
;
224 uint64_t patch_outputs_written
;
227 struct radv_streamout_info so
;
230 struct radv_userdata_info
{
235 struct radv_userdata_locations
{
236 struct radv_userdata_info descriptor_sets
[RADV_UD_MAX_SETS
];
237 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
238 uint32_t descriptor_sets_enabled
;
241 struct radv_vs_output_info
{
242 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
243 uint8_t clip_dist_mask
;
244 uint8_t cull_dist_mask
;
245 uint8_t param_exports
;
246 bool writes_pointsize
;
248 bool writes_viewport_index
;
250 unsigned pos_exports
;
253 struct radv_es_output_info
{
254 uint32_t esgs_itemsize
;
257 struct radv_shader_variant_info
{
258 struct radv_userdata_locations user_sgprs_locs
;
259 struct radv_shader_info info
;
260 unsigned num_user_sgprs
;
261 unsigned num_input_sgprs
;
262 unsigned num_input_vgprs
;
263 unsigned private_mem_vgprs
;
264 bool need_indirect_descriptor_sets
;
267 struct radv_vs_output_info outinfo
;
268 struct radv_es_output_info es_info
;
276 uint32_t flat_shaded_mask
;
277 uint32_t float16_shaded_mask
;
279 bool early_fragment_test
;
282 unsigned block_size
[3];
285 unsigned vertices_in
;
286 unsigned vertices_out
;
287 unsigned output_prim
;
288 unsigned invocations
;
289 unsigned gsvs_vertex_size
;
290 unsigned max_gsvs_emit_size
;
291 unsigned es_type
; /* GFX9: VS or TES */
294 unsigned tcs_vertices_out
;
295 uint32_t num_patches
;
299 struct radv_vs_output_info outinfo
;
300 struct radv_es_output_info es_info
;
302 unsigned primitive_mode
;
303 enum gl_tess_spacing spacing
;
311 enum radv_shader_binary_type
{
312 RADV_BINARY_TYPE_LEGACY
,
313 RADV_BINARY_TYPE_RTLD
316 struct radv_shader_binary
{
317 enum radv_shader_binary_type type
;
318 gl_shader_stage stage
;
319 bool is_gs_copy_shader
;
321 struct radv_shader_variant_info variant_info
;
323 /* Self-referential size so we avoid consistency issues. */
327 struct radv_shader_binary_legacy
{
328 struct radv_shader_binary base
;
329 struct ac_shader_config config
;
331 unsigned llvm_ir_size
;
332 unsigned disasm_size
;
334 /* data has size of code_size + llvm_ir_size + disasm_size + 2, where
335 * the +2 is for 0 of the ir strings. */
339 struct radv_shader_binary_rtld
{
340 struct radv_shader_binary base
;
342 unsigned llvm_ir_size
;
346 struct radv_shader_variant
{
349 struct radeon_winsys_bo
*bo
;
351 struct ac_shader_config config
;
353 struct radv_shader_variant_info info
;
358 struct nir_shader
*nir
;
360 char *llvm_ir_string
;
362 struct list_head slab_list
;
365 struct radv_shader_slab
{
366 struct list_head slabs
;
367 struct list_head shaders
;
368 struct radeon_winsys_bo
*bo
;
374 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
377 radv_nir_lower_ycbcr_textures(nir_shader
*shader
,
378 const struct radv_pipeline_layout
*layout
);
381 radv_shader_compile_to_nir(struct radv_device
*device
,
382 struct radv_shader_module
*module
,
383 const char *entrypoint_name
,
384 gl_shader_stage stage
,
385 const VkSpecializationInfo
*spec_info
,
386 const VkPipelineCreateFlags flags
,
387 const struct radv_pipeline_layout
*layout
);
390 radv_alloc_shader_memory(struct radv_device
*device
,
391 struct radv_shader_variant
*shader
);
394 radv_destroy_shader_slabs(struct radv_device
*device
);
396 struct radv_shader_variant
*
397 radv_shader_variant_create(struct radv_device
*device
,
398 const struct radv_shader_binary
*binary
);
399 struct radv_shader_variant
*
400 radv_shader_variant_compile(struct radv_device
*device
,
401 struct radv_shader_module
*module
,
402 struct nir_shader
*const *shaders
,
404 struct radv_pipeline_layout
*layout
,
405 const struct radv_shader_variant_key
*key
,
406 struct radv_shader_binary
**binary_out
);
408 struct radv_shader_variant
*
409 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
410 struct radv_shader_binary
**binary_out
,
414 radv_shader_variant_destroy(struct radv_device
*device
,
415 struct radv_shader_variant
*variant
);
418 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
);
421 radv_shader_dump_stats(struct radv_device
*device
,
422 struct radv_shader_variant
*variant
,
423 gl_shader_stage stage
,
427 radv_can_dump_shader(struct radv_device
*device
,
428 struct radv_shader_module
*module
,
429 bool is_gs_copy_shader
)
431 if (!(device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
))
434 /* Only dump non-meta shaders, useful for debugging purposes. */
435 return (module
&& !module
->nir
) || is_gs_copy_shader
;
439 radv_can_dump_shader_stats(struct radv_device
*device
,
440 struct radv_shader_module
*module
)
442 /* Only dump non-meta shader stats. */
443 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
&&
444 module
&& !module
->nir
;
447 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot
)
449 /* handle patch indices separate */
450 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
452 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
454 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
455 return 2 + (slot
- VARYING_SLOT_PATCH0
);
456 if (slot
== VARYING_SLOT_POS
)
458 if (slot
== VARYING_SLOT_PSIZ
)
460 if (slot
== VARYING_SLOT_CLIP_DIST0
)
462 if (slot
== VARYING_SLOT_CLIP_DIST1
)
464 /* 3 is reserved for clip dist as well */
465 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
466 return 4 + (slot
- VARYING_SLOT_VAR0
);
467 unreachable("illegal slot in get unique index\n");