src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "ac_binary.h"
  32 #include "amd_family.h"
  33 #include "radv_constants.h"
  34
  35 #include "nir/nir.h"
  36 #include "vulkan/vulkan.h"
  37
  38 struct radv_device;
  39
  40 struct radv_shader_module {
  41         struct nir_shader *nir;
  42         unsigned char sha1[20];
  43         uint32_t size;
  44         char data[0];
  45 };
  46
  47 enum {
  48         RADV_ALPHA_ADJUST_NONE = 0,
  49         RADV_ALPHA_ADJUST_SNORM = 1,
  50         RADV_ALPHA_ADJUST_SINT = 2,
  51         RADV_ALPHA_ADJUST_SSCALED = 3,
  52 };
  53
  54 struct radv_vs_out_key {
  55         uint32_t as_es:1;
  56         uint32_t as_ls:1;
  57         uint32_t as_ngg:1;
  58         uint32_t export_prim_id:1;
  59         uint32_t export_layer_id:1;
  60         uint32_t export_clip_dists:1;
  61 };
  62
  63 struct radv_vs_variant_key {
  64         struct radv_vs_out_key out;
  65
  66         uint32_t instance_rate_inputs;
  67         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  68         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  69         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  70         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  71         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  72
  73         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  74          * so we may need to fix it up. */
  75         uint64_t alpha_adjust;
  76
  77         /* For some formats the channels have to be shuffled. */
  78         uint32_t post_shuffle;
  79 };
  80
  81 struct radv_tes_variant_key {
  82         struct radv_vs_out_key out;
  83
  84         uint8_t num_patches;
  85         uint8_t tcs_num_outputs;
  86 };
  87
  88 struct radv_tcs_variant_key {
  89         struct radv_vs_variant_key vs_key;
  90         unsigned primitive_mode;
  91         unsigned input_vertices;
  92         unsigned num_inputs;
  93         uint32_t tes_reads_tess_factors:1;
  94 };
  95
  96 struct radv_fs_variant_key {
  97         uint32_t col_format;
  98         uint8_t log2_ps_iter_samples;
  99         uint8_t num_samples;
 100         uint32_t is_int8;
 101         uint32_t is_int10;
 102 };
 103
 104 struct radv_shader_variant_key {
 105         union {
 106                 struct radv_vs_variant_key vs;
 107                 struct radv_fs_variant_key fs;
 108                 struct radv_tes_variant_key tes;
 109                 struct radv_tcs_variant_key tcs;
 110
 111                 /* A common prefix of the vs and tes keys. */
 112                 struct radv_vs_out_key vs_common_out;
 113         };
 114         bool has_multiview_view_index;
 115 };
 116
 117 struct radv_nir_compiler_options {
 118         struct radv_pipeline_layout *layout;
 119         struct radv_shader_variant_key key;
 120         bool unsafe_math;
 121         bool supports_spill;
 122         bool clamp_shadow_reference;
 123         bool robust_buffer_access;
 124         bool dump_shader;
 125         bool dump_preoptir;
 126         bool record_llvm_ir;
 127         bool check_ir;
 128         bool has_ls_vgpr_init_bug;
 129         enum radeon_family family;
 130         enum chip_class chip_class;
 131         uint32_t tess_offchip_block_dw_size;
 132         uint32_t address32_hi;
 133         uint8_t wave_size;
 134 };
 135
 136 enum radv_ud_index {
 137         AC_UD_SCRATCH_RING_OFFSETS = 0,
 138         AC_UD_PUSH_CONSTANTS = 1,
 139         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 140         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 141         AC_UD_VIEW_INDEX = 4,
 142         AC_UD_STREAMOUT_BUFFERS = 5,
 143         AC_UD_SHADER_START = 6,
 144         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 145         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 146         AC_UD_VS_MAX_UD,
 147         AC_UD_PS_MAX_UD,
 148         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 149         AC_UD_CS_MAX_UD,
 150         AC_UD_GS_MAX_UD,
 151         AC_UD_TCS_MAX_UD,
 152         AC_UD_TES_MAX_UD,
 153         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 154 };
 155
 156 struct radv_stream_output {
 157         uint8_t location;
 158         uint8_t buffer;
 159         uint16_t offset;
 160         uint8_t component_mask;
 161         uint8_t stream;
 162 };
 163
 164 struct radv_streamout_info {
 165         uint16_t num_outputs;
 166         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 167         uint16_t strides[MAX_SO_BUFFERS];
 168         uint32_t enabled_stream_buffers_mask;
 169 };
 170
 171 struct radv_userdata_info {
 172         int8_t sgpr_idx;
 173         uint8_t num_sgprs;
 174 };
 175
 176 struct radv_userdata_locations {
 177         struct radv_userdata_info descriptor_sets[MAX_SETS];
 178         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 179         uint32_t descriptor_sets_enabled;
 180 };
 181
 182 struct radv_vs_output_info {
 183         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 184         uint8_t clip_dist_mask;
 185         uint8_t cull_dist_mask;
 186         uint8_t param_exports;
 187         bool writes_pointsize;
 188         bool writes_layer;
 189         bool writes_viewport_index;
 190         bool export_prim_id;
 191         unsigned pos_exports;
 192 };
 193
 194 struct radv_es_output_info {
 195        uint32_t esgs_itemsize;
 196 };
 197
 198 struct radv_shader_info {
 199         bool loads_push_constants;
 200         bool loads_dynamic_offsets;
 201         uint8_t min_push_constant_used;
 202         uint8_t max_push_constant_used;
 203         bool has_only_32bit_push_constants;
 204         bool has_indirect_push_constants;
 205         uint8_t num_inline_push_consts;
 206         uint8_t base_inline_push_consts;
 207         uint32_t desc_set_used_mask;
 208         bool needs_multiview_view_index;
 209         bool uses_invocation_id;
 210         bool uses_prim_id;
 211         uint8_t wave_size;
 212         struct radv_userdata_locations user_sgprs_locs;
 213         unsigned num_user_sgprs;
 214         unsigned num_input_sgprs;
 215         unsigned num_input_vgprs;
 216         unsigned private_mem_vgprs;
 217         bool need_indirect_descriptor_sets;
 218         bool is_ngg;
 219         struct {
 220                 uint64_t ls_outputs_written;
 221                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 222                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 223                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 224                 bool needs_draw_id;
 225                 bool needs_instance_id;
 226                 struct radv_vs_output_info outinfo;
 227                 struct radv_es_output_info es_info;
 228                 bool as_es;
 229                 bool as_ls;
 230                 bool export_prim_id;
 231         } vs;
 232         struct {
 233                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 234                 uint8_t num_stream_output_components[4];
 235                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 236                 uint8_t max_stream;
 237                 unsigned gsvs_vertex_size;
 238                 unsigned max_gsvs_emit_size;
 239                 unsigned vertices_in;
 240                 unsigned vertices_out;
 241                 unsigned output_prim;
 242                 unsigned invocations;
 243                 unsigned es_type; /* GFX9: VS or TES */
 244         } gs;
 245         struct {
 246                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 247                 struct radv_vs_output_info outinfo;
 248                 struct radv_es_output_info es_info;
 249                 bool as_es;
 250                 unsigned primitive_mode;
 251                 enum gl_tess_spacing spacing;
 252                 bool ccw;
 253                 bool point_mode;
 254                 bool export_prim_id;
 255         } tes;
 256         struct {
 257                 bool force_persample;
 258                 bool needs_sample_positions;
 259                 bool writes_memory;
 260                 bool writes_z;
 261                 bool writes_stencil;
 262                 bool writes_sample_mask;
 263                 bool has_pcoord;
 264                 bool prim_id_input;
 265                 bool layer_input;
 266                 uint8_t num_input_clips_culls;
 267                 uint32_t input_mask;
 268                 uint32_t flat_shaded_mask;
 269                 uint32_t float16_shaded_mask;
 270                 uint32_t num_interp;
 271                 bool can_discard;
 272                 bool early_fragment_test;
 273                 bool post_depth_coverage;
 274         } ps;
 275         struct {
 276                 bool uses_grid_size;
 277                 bool uses_block_id[3];
 278                 bool uses_thread_id[3];
 279                 bool uses_local_invocation_idx;
 280                 unsigned block_size[3];
 281         } cs;
 282         struct {
 283                 uint64_t outputs_written;
 284                 uint64_t patch_outputs_written;
 285                 unsigned tcs_vertices_out;
 286                 uint32_t num_patches;
 287                 uint32_t lds_size;
 288         } tcs;
 289
 290         struct radv_streamout_info so;
 291 };
 292
 293 enum radv_shader_binary_type {
 294         RADV_BINARY_TYPE_LEGACY,
 295         RADV_BINARY_TYPE_RTLD
 296 };
 297
 298 struct radv_shader_binary {
 299         enum radv_shader_binary_type type;
 300         gl_shader_stage stage;
 301         bool is_gs_copy_shader;
 302
 303         struct radv_shader_info info;
 304
 305         /* Self-referential size so we avoid consistency issues. */
 306         uint32_t total_size;
 307 };
 308
 309 struct radv_shader_binary_legacy {
 310         struct radv_shader_binary base;
 311         struct ac_shader_config config;
 312         unsigned code_size;
 313         unsigned llvm_ir_size;
 314         unsigned disasm_size;
 315
 316         /* data has size of code_size + llvm_ir_size + disasm_size + 2, where
 317          * the +2 is for 0 of the ir strings. */
 318         uint8_t data[0];
 319 };
 320
 321 struct radv_shader_binary_rtld {
 322         struct radv_shader_binary base;
 323         unsigned elf_size;
 324         unsigned llvm_ir_size;
 325         uint8_t data[0];
 326 };
 327
 328 struct radv_shader_variant {
 329         uint32_t ref_count;
 330
 331         struct radeon_winsys_bo *bo;
 332         uint64_t bo_offset;
 333         struct ac_shader_config config;
 334         uint32_t code_size;
 335         uint32_t exec_size;
 336         struct radv_shader_info info;
 337
 338         /* debug only */
 339         uint32_t *spirv;
 340         uint32_t spirv_size;
 341         char *nir_string;
 342         char *disasm_string;
 343         char *llvm_ir_string;
 344
 345         struct list_head slab_list;
 346 };
 347
 348 struct radv_shader_slab {
 349         struct list_head slabs;
 350         struct list_head shaders;
 351         struct radeon_winsys_bo *bo;
 352         uint64_t size;
 353         char *ptr;
 354 };
 355
 356 void
 357 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 358                   bool allow_copies);
 359 bool
 360 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 361                              const struct radv_pipeline_layout *layout);
 362
 363 nir_shader *
 364 radv_shader_compile_to_nir(struct radv_device *device,
 365                            struct radv_shader_module *module,
 366                            const char *entrypoint_name,
 367                            gl_shader_stage stage,
 368                            const VkSpecializationInfo *spec_info,
 369                            const VkPipelineCreateFlags flags,
 370                            const struct radv_pipeline_layout *layout);
 371
 372 void *
 373 radv_alloc_shader_memory(struct radv_device *device,
 374                           struct radv_shader_variant *shader);
 375
 376 void
 377 radv_destroy_shader_slabs(struct radv_device *device);
 378
 379 struct radv_shader_variant *
 380 radv_shader_variant_create(struct radv_device *device,
 381                            const struct radv_shader_binary *binary,
 382                            bool keep_shader_info);
 383 struct radv_shader_variant *
 384 radv_shader_variant_compile(struct radv_device *device,
 385                             struct radv_shader_module *module,
 386                             struct nir_shader *const *shaders,
 387                             int shader_count,
 388                             struct radv_pipeline_layout *layout,
 389                             const struct radv_shader_variant_key *key,
 390                             struct radv_shader_info *info,
 391                             bool keep_shader_info,
 392                             struct radv_shader_binary **binary_out);
 393
 394 struct radv_shader_variant *
 395 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 396                            struct radv_shader_info *info,
 397                            struct radv_shader_binary **binary_out,
 398                            bool multiview,  bool keep_shader_info);
 399
 400 void
 401 radv_shader_variant_destroy(struct radv_device *device,
 402                             struct radv_shader_variant *variant);
 403
 404
 405 unsigned
 406 radv_get_max_waves(struct radv_device *device,
 407                    struct radv_shader_variant *variant,
 408                    gl_shader_stage stage);
 409
 410 unsigned
 411 radv_get_max_workgroup_size(enum chip_class chip_class,
 412                             gl_shader_stage stage,
 413                             const unsigned *sizes);
 414
 415 const char *
 416 radv_get_shader_name(struct radv_shader_info *info,
 417                      gl_shader_stage stage);
 418
 419 void
 420 radv_shader_dump_stats(struct radv_device *device,
 421                        struct radv_shader_variant *variant,
 422                        gl_shader_stage stage,
 423                        FILE *file);
 424
 425 bool
 426 radv_can_dump_shader(struct radv_device *device,
 427                      struct radv_shader_module *module,
 428                      bool is_gs_copy_shader);
 429
 430 bool
 431 radv_can_dump_shader_stats(struct radv_device *device,
 432                            struct radv_shader_module *module);
 433
 434 unsigned
 435 shader_io_get_unique_index(gl_varying_slot slot);
 436
 437 void
 438 radv_lower_fs_io(nir_shader *nir);
 439
 440 #endif