2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_binary.h"
32 #include "amd_family.h"
33 #include "radv_constants.h"
36 #include "vulkan/vulkan.h"
37 #include "vulkan/util/vk_object.h"
41 struct radv_shader_module
{
42 struct vk_object_base base
;
43 struct nir_shader
*nir
;
44 unsigned char sha1
[20];
50 RADV_ALPHA_ADJUST_NONE
= 0,
51 RADV_ALPHA_ADJUST_SNORM
= 1,
52 RADV_ALPHA_ADJUST_SINT
= 2,
53 RADV_ALPHA_ADJUST_SSCALED
= 3,
56 struct radv_vs_out_key
{
60 uint32_t as_ngg_passthrough
:1;
61 uint32_t export_prim_id
:1;
62 uint32_t export_layer_id
:1;
63 uint32_t export_clip_dists
:1;
64 uint32_t export_viewport_index
:1;
67 struct radv_vs_variant_key
{
68 struct radv_vs_out_key out
;
70 uint32_t instance_rate_inputs
;
71 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
72 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
73 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
74 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
75 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
77 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
78 * so we may need to fix it up. */
79 uint64_t alpha_adjust
;
81 /* For some formats the channels have to be shuffled. */
82 uint32_t post_shuffle
;
84 /* Output primitive type. */
88 struct radv_tes_variant_key
{
89 struct radv_vs_out_key out
;
92 uint8_t tcs_num_outputs
;
95 struct radv_tcs_variant_key
{
96 struct radv_vs_variant_key vs_key
;
97 unsigned primitive_mode
;
98 unsigned input_vertices
;
100 uint32_t tes_reads_tess_factors
:1;
103 struct radv_fs_variant_key
{
105 uint8_t log2_ps_iter_samples
;
111 struct radv_cs_variant_key
{
112 uint8_t subgroup_size
;
115 struct radv_shader_variant_key
{
117 struct radv_vs_variant_key vs
;
118 struct radv_fs_variant_key fs
;
119 struct radv_tes_variant_key tes
;
120 struct radv_tcs_variant_key tcs
;
121 struct radv_cs_variant_key cs
;
123 /* A common prefix of the vs and tes keys. */
124 struct radv_vs_out_key vs_common_out
;
126 bool has_multiview_view_index
;
129 struct radv_nir_compiler_options
{
130 struct radv_pipeline_layout
*layout
;
131 struct radv_shader_variant_key key
;
132 bool explicit_scratch_args
;
133 bool clamp_shadow_reference
;
134 bool robust_buffer_access
;
140 bool has_ls_vgpr_init_bug
;
141 bool use_ngg_streamout
;
142 bool enable_mrt_output_nan_fixup
;
143 enum radeon_family family
;
144 enum chip_class chip_class
;
145 uint32_t tess_offchip_block_dw_size
;
146 uint32_t address32_hi
;
150 AC_UD_SCRATCH_RING_OFFSETS
= 0,
151 AC_UD_PUSH_CONSTANTS
= 1,
152 AC_UD_INLINE_PUSH_CONSTANTS
= 2,
153 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 3,
154 AC_UD_VIEW_INDEX
= 4,
155 AC_UD_STREAMOUT_BUFFERS
= 5,
156 AC_UD_NGG_GS_STATE
= 6,
157 AC_UD_SHADER_START
= 7,
158 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
159 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
162 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
167 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
170 struct radv_stream_output
{
174 uint8_t component_mask
;
178 struct radv_streamout_info
{
179 uint16_t num_outputs
;
180 struct radv_stream_output outputs
[MAX_SO_OUTPUTS
];
181 uint16_t strides
[MAX_SO_BUFFERS
];
182 uint32_t enabled_stream_buffers_mask
;
185 struct radv_userdata_info
{
190 struct radv_userdata_locations
{
191 struct radv_userdata_info descriptor_sets
[MAX_SETS
];
192 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
193 uint32_t descriptor_sets_enabled
;
196 struct radv_vs_output_info
{
197 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
198 uint8_t clip_dist_mask
;
199 uint8_t cull_dist_mask
;
200 uint8_t param_exports
;
201 bool writes_pointsize
;
203 bool writes_viewport_index
;
205 unsigned pos_exports
;
208 struct radv_es_output_info
{
209 uint32_t esgs_itemsize
;
212 struct gfx9_gs_info
{
213 uint32_t vgt_gs_onchip_cntl
;
214 uint32_t vgt_gs_max_prims_per_subgroup
;
215 uint32_t vgt_esgs_ring_itemsize
;
219 struct gfx10_ngg_info
{
220 uint16_t ngg_emit_size
; /* in dwords */
221 uint32_t hw_max_esverts
;
222 uint32_t max_gsprims
;
223 uint32_t max_out_verts
;
224 uint32_t prim_amp_factor
;
225 uint32_t vgt_esgs_ring_itemsize
;
226 uint32_t esgs_ring_size
;
227 bool max_vert_out_per_gs_instance
;
230 struct radv_shader_info
{
231 bool loads_push_constants
;
232 bool loads_dynamic_offsets
;
233 uint8_t min_push_constant_used
;
234 uint8_t max_push_constant_used
;
235 bool has_only_32bit_push_constants
;
236 bool has_indirect_push_constants
;
237 uint8_t num_inline_push_consts
;
238 uint8_t base_inline_push_consts
;
239 uint32_t desc_set_used_mask
;
240 bool needs_multiview_view_index
;
241 bool uses_invocation_id
;
244 uint8_t ballot_bit_size
;
245 struct radv_userdata_locations user_sgprs_locs
;
246 unsigned num_user_sgprs
;
247 unsigned num_input_sgprs
;
248 unsigned num_input_vgprs
;
249 unsigned private_mem_vgprs
;
250 bool need_indirect_descriptor_sets
;
252 bool is_ngg_passthrough
;
254 uint64_t ls_outputs_written
;
255 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
256 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
257 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
259 bool needs_instance_id
;
260 struct radv_vs_output_info outinfo
;
261 struct radv_es_output_info es_info
;
265 uint8_t num_linked_outputs
;
268 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
269 uint8_t num_stream_output_components
[4];
270 uint8_t output_streams
[VARYING_SLOT_VAR31
+ 1];
273 unsigned gsvs_vertex_size
;
274 unsigned max_gsvs_emit_size
;
275 unsigned vertices_in
;
276 unsigned vertices_out
;
277 unsigned output_prim
;
278 unsigned invocations
;
279 unsigned es_type
; /* GFX9: VS or TES */
280 uint8_t num_linked_inputs
;
283 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
284 struct radv_vs_output_info outinfo
;
285 struct radv_es_output_info es_info
;
287 unsigned primitive_mode
;
288 enum gl_tess_spacing spacing
;
292 uint8_t num_linked_inputs
;
293 uint8_t num_linked_patch_inputs
;
294 uint8_t num_linked_outputs
;
297 bool force_persample
;
298 bool needs_sample_positions
;
302 bool writes_sample_mask
;
306 bool viewport_index_input
;
307 uint8_t num_input_clips_culls
;
309 uint32_t flat_shaded_mask
;
310 uint32_t explicit_shaded_mask
;
311 uint32_t float16_shaded_mask
;
313 uint32_t cb_shader_mask
;
315 bool early_fragment_test
;
316 bool post_depth_coverage
;
317 uint8_t depth_layout
;
321 bool uses_block_id
[3];
322 bool uses_thread_id
[3];
323 bool uses_local_invocation_idx
;
324 unsigned block_size
[3];
327 uint64_t outputs_written
;
328 uint64_t patch_outputs_written
;
329 uint64_t tes_inputs_read
;
330 uint64_t tes_patch_inputs_read
;
331 unsigned tcs_vertices_out
;
332 uint32_t num_patches
;
334 uint8_t num_linked_inputs
;
335 uint8_t num_linked_outputs
;
336 uint8_t num_linked_patch_outputs
;
339 struct radv_streamout_info so
;
341 struct gfx9_gs_info gs_ring_info
;
342 struct gfx10_ngg_info ngg_info
;
344 unsigned float_controls_mode
;
347 enum radv_shader_binary_type
{
348 RADV_BINARY_TYPE_LEGACY
,
349 RADV_BINARY_TYPE_RTLD
352 struct radv_shader_binary
{
353 enum radv_shader_binary_type type
;
354 gl_shader_stage stage
;
355 bool is_gs_copy_shader
;
357 struct radv_shader_info info
;
359 /* Self-referential size so we avoid consistency issues. */
363 struct radv_shader_binary_legacy
{
364 struct radv_shader_binary base
;
365 struct ac_shader_config config
;
369 unsigned disasm_size
;
372 /* data has size of stats_size + code_size + ir_size + disasm_size + 2,
373 * where the +2 is for 0 of the ir strings. */
377 struct radv_shader_binary_rtld
{
378 struct radv_shader_binary base
;
380 unsigned llvm_ir_size
;
384 struct radv_compiler_statistic_info
{
389 struct radv_compiler_statistics
{
391 struct radv_compiler_statistic_info
*infos
;
395 struct radv_shader_variant
{
398 struct radeon_winsys_bo
*bo
;
400 struct ac_shader_config config
;
403 struct radv_shader_info info
;
411 struct radv_compiler_statistics
*statistics
;
413 struct list_head slab_list
;
416 struct radv_shader_slab
{
417 struct list_head slabs
;
418 struct list_head shaders
;
419 struct radeon_winsys_bo
*bo
;
425 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
428 radv_nir_lower_ycbcr_textures(nir_shader
*shader
,
429 const struct radv_pipeline_layout
*layout
);
432 radv_shader_compile_to_nir(struct radv_device
*device
,
433 struct radv_shader_module
*module
,
434 const char *entrypoint_name
,
435 gl_shader_stage stage
,
436 const VkSpecializationInfo
*spec_info
,
437 const VkPipelineCreateFlags flags
,
438 const struct radv_pipeline_layout
*layout
,
439 unsigned subgroup_size
, unsigned ballot_bit_size
);
442 radv_destroy_shader_slabs(struct radv_device
*device
);
445 radv_create_shaders(struct radv_pipeline
*pipeline
,
446 struct radv_device
*device
,
447 struct radv_pipeline_cache
*cache
,
448 const struct radv_pipeline_key
*key
,
449 const VkPipelineShaderStageCreateInfo
**pStages
,
450 const VkPipelineCreateFlags flags
,
451 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
452 VkPipelineCreationFeedbackEXT
**stage_feedbacks
);
454 struct radv_shader_variant
*
455 radv_shader_variant_create(struct radv_device
*device
,
456 const struct radv_shader_binary
*binary
,
457 bool keep_shader_info
);
458 struct radv_shader_variant
*
459 radv_shader_variant_compile(struct radv_device
*device
,
460 struct radv_shader_module
*module
,
461 struct nir_shader
*const *shaders
,
463 struct radv_pipeline_layout
*layout
,
464 const struct radv_shader_variant_key
*key
,
465 struct radv_shader_info
*info
,
466 bool keep_shader_info
, bool keep_statistic_info
,
467 struct radv_shader_binary
**binary_out
);
469 struct radv_shader_variant
*
470 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
471 struct radv_shader_info
*info
,
472 struct radv_shader_binary
**binary_out
,
473 bool multiview
, bool keep_shader_info
,
474 bool keep_statistic_info
);
477 radv_shader_variant_destroy(struct radv_device
*device
,
478 struct radv_shader_variant
*variant
);
482 radv_get_max_waves(struct radv_device
*device
,
483 struct radv_shader_variant
*variant
,
484 gl_shader_stage stage
);
487 radv_get_max_workgroup_size(enum chip_class chip_class
,
488 gl_shader_stage stage
,
489 const unsigned *sizes
);
492 radv_get_shader_name(struct radv_shader_info
*info
,
493 gl_shader_stage stage
);
496 radv_shader_dump_stats(struct radv_device
*device
,
497 struct radv_shader_variant
*variant
,
498 gl_shader_stage stage
,
502 radv_can_dump_shader(struct radv_device
*device
,
503 struct radv_shader_module
*module
,
504 bool is_gs_copy_shader
);
507 radv_can_dump_shader_stats(struct radv_device
*device
,
508 struct radv_shader_module
*module
);
510 static inline unsigned
511 shader_io_get_unique_index(gl_varying_slot slot
)
513 /* handle patch indices separate */
514 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
516 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
518 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
519 return 2 + (slot
- VARYING_SLOT_PATCH0
);
520 if (slot
== VARYING_SLOT_POS
)
522 if (slot
== VARYING_SLOT_PSIZ
)
524 if (slot
== VARYING_SLOT_CLIP_DIST0
)
526 if (slot
== VARYING_SLOT_CLIP_DIST1
)
528 /* 3 is reserved for clip dist as well */
529 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
530 return 4 + (slot
- VARYING_SLOT_VAR0
);
531 unreachable("illegal slot in get unique index\n");
534 static inline unsigned
535 calculate_tess_lds_size(unsigned tcs_num_input_vertices
,
536 unsigned tcs_num_output_vertices
,
537 unsigned tcs_num_inputs
,
538 unsigned tcs_num_patches
,
539 unsigned tcs_num_outputs
,
540 unsigned tcs_num_patch_outputs
)
542 unsigned input_vertex_size
= tcs_num_inputs
* 16;
543 unsigned output_vertex_size
= tcs_num_outputs
* 16;
545 unsigned input_patch_size
= tcs_num_input_vertices
* input_vertex_size
;
547 unsigned pervertex_output_patch_size
= tcs_num_output_vertices
* output_vertex_size
;
548 unsigned output_patch_size
= pervertex_output_patch_size
+ tcs_num_patch_outputs
* 16;
550 unsigned output_patch0_offset
= input_patch_size
* tcs_num_patches
;
552 return output_patch0_offset
+ output_patch_size
* tcs_num_patches
;
555 static inline unsigned
556 get_tcs_num_patches(unsigned tcs_num_input_vertices
,
557 unsigned tcs_num_output_vertices
,
558 unsigned tcs_num_inputs
,
559 unsigned tcs_num_outputs
,
560 unsigned tcs_num_patch_outputs
,
561 unsigned tess_offchip_block_dw_size
,
562 enum chip_class chip_class
,
563 enum radeon_family family
)
565 uint32_t input_vertex_size
= tcs_num_inputs
* 16;
566 uint32_t input_patch_size
= tcs_num_input_vertices
* input_vertex_size
;
567 uint32_t output_vertex_size
= tcs_num_outputs
* 16;
568 uint32_t pervertex_output_patch_size
= tcs_num_output_vertices
* output_vertex_size
;
569 uint32_t output_patch_size
= pervertex_output_patch_size
+ tcs_num_patch_outputs
* 16;
571 /* Ensure that we only need one wave per SIMD so we don't need to check
572 * resource usage. Also ensures that the number of tcs in and out
573 * vertices per threadgroup are at most 256.
575 unsigned num_patches
= 64 / MAX2(tcs_num_input_vertices
, tcs_num_output_vertices
) * 4;
576 /* Make sure that the data fits in LDS. This assumes the shaders only
577 * use LDS for the inputs and outputs.
579 unsigned hardware_lds_size
= 32768;
581 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
582 * threadgroup, even though there is more than 32 KiB LDS.
584 * Test: dEQP-VK.tessellation.shader_input_output.barrier
586 if (chip_class
>= GFX7
&& family
!= CHIP_STONEY
)
587 hardware_lds_size
= 65536;
589 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
590 /* Make sure the output data fits in the offchip buffer */
591 num_patches
= MIN2(num_patches
, (tess_offchip_block_dw_size
* 4) / output_patch_size
);
592 /* Not necessary for correctness, but improves performance. The
593 * specific value is taken from the proprietary driver.
595 num_patches
= MIN2(num_patches
, 40);
597 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
598 if (chip_class
== GFX6
) {
599 unsigned one_wave
= 64 / MAX2(tcs_num_input_vertices
, tcs_num_output_vertices
);
600 num_patches
= MIN2(num_patches
, one_wave
);
606 radv_lower_fs_io(nir_shader
*nir
);