src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "ac_binary.h"
  32 #include "amd_family.h"
  33 #include "radv_constants.h"
  34
  35 #include "nir/nir.h"
  36 #include "vulkan/vulkan.h"
  37
  38 struct radv_device;
  39
  40 struct radv_shader_module {
  41         struct nir_shader *nir;
  42         unsigned char sha1[20];
  43         uint32_t size;
  44         char data[0];
  45 };
  46
  47 enum {
  48         RADV_ALPHA_ADJUST_NONE = 0,
  49         RADV_ALPHA_ADJUST_SNORM = 1,
  50         RADV_ALPHA_ADJUST_SINT = 2,
  51         RADV_ALPHA_ADJUST_SSCALED = 3,
  52 };
  53
  54 struct radv_vs_out_key {
  55         uint32_t as_es:1;
  56         uint32_t as_ls:1;
  57         uint32_t as_ngg:1;
  58         uint32_t as_ngg_passthrough:1;
  59         uint32_t export_prim_id:1;
  60         uint32_t export_layer_id:1;
  61         uint32_t export_clip_dists:1;
  62 };
  63
  64 struct radv_vs_variant_key {
  65         struct radv_vs_out_key out;
  66
  67         uint32_t instance_rate_inputs;
  68         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  69         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  70         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  71         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  72         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  73
  74         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  75          * so we may need to fix it up. */
  76         uint64_t alpha_adjust;
  77
  78         /* For some formats the channels have to be shuffled. */
  79         uint32_t post_shuffle;
  80
  81         /* Output primitive type. */
  82         uint8_t outprim;
  83 };
  84
  85 struct radv_tes_variant_key {
  86         struct radv_vs_out_key out;
  87
  88         uint8_t num_patches;
  89         uint8_t tcs_num_outputs;
  90 };
  91
  92 struct radv_tcs_variant_key {
  93         struct radv_vs_variant_key vs_key;
  94         unsigned primitive_mode;
  95         unsigned input_vertices;
  96         unsigned num_inputs;
  97         uint32_t tes_reads_tess_factors:1;
  98 };
  99
 100 struct radv_fs_variant_key {
 101         uint32_t col_format;
 102         uint8_t log2_ps_iter_samples;
 103         uint8_t num_samples;
 104         uint32_t is_int8;
 105         uint32_t is_int10;
 106 };
 107
 108 struct radv_cs_variant_key {
 109         uint8_t subgroup_size;
 110 };
 111
 112 struct radv_shader_variant_key {
 113         union {
 114                 struct radv_vs_variant_key vs;
 115                 struct radv_fs_variant_key fs;
 116                 struct radv_tes_variant_key tes;
 117                 struct radv_tcs_variant_key tcs;
 118                 struct radv_cs_variant_key cs;
 119
 120                 /* A common prefix of the vs and tes keys. */
 121                 struct radv_vs_out_key vs_common_out;
 122         };
 123         bool has_multiview_view_index;
 124 };
 125
 126 struct radv_nir_compiler_options {
 127         struct radv_pipeline_layout *layout;
 128         struct radv_shader_variant_key key;
 129         bool explicit_scratch_args;
 130         bool clamp_shadow_reference;
 131         bool robust_buffer_access;
 132         bool dump_shader;
 133         bool dump_preoptir;
 134         bool record_ir;
 135         bool check_ir;
 136         bool has_ls_vgpr_init_bug;
 137         bool use_ngg_streamout;
 138         enum radeon_family family;
 139         enum chip_class chip_class;
 140         uint32_t tess_offchip_block_dw_size;
 141         uint32_t address32_hi;
 142 };
 143
 144 enum radv_ud_index {
 145         AC_UD_SCRATCH_RING_OFFSETS = 0,
 146         AC_UD_PUSH_CONSTANTS = 1,
 147         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 148         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 149         AC_UD_VIEW_INDEX = 4,
 150         AC_UD_STREAMOUT_BUFFERS = 5,
 151         AC_UD_NGG_GS_STATE = 6,
 152         AC_UD_SHADER_START = 7,
 153         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 154         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 155         AC_UD_VS_MAX_UD,
 156         AC_UD_PS_MAX_UD,
 157         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 158         AC_UD_CS_MAX_UD,
 159         AC_UD_GS_MAX_UD,
 160         AC_UD_TCS_MAX_UD,
 161         AC_UD_TES_MAX_UD,
 162         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 163 };
 164
 165 struct radv_stream_output {
 166         uint8_t location;
 167         uint8_t buffer;
 168         uint16_t offset;
 169         uint8_t component_mask;
 170         uint8_t stream;
 171 };
 172
 173 struct radv_streamout_info {
 174         uint16_t num_outputs;
 175         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 176         uint16_t strides[MAX_SO_BUFFERS];
 177         uint32_t enabled_stream_buffers_mask;
 178 };
 179
 180 struct radv_userdata_info {
 181         int8_t sgpr_idx;
 182         uint8_t num_sgprs;
 183 };
 184
 185 struct radv_userdata_locations {
 186         struct radv_userdata_info descriptor_sets[MAX_SETS];
 187         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 188         uint32_t descriptor_sets_enabled;
 189 };
 190
 191 struct radv_vs_output_info {
 192         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 193         uint8_t clip_dist_mask;
 194         uint8_t cull_dist_mask;
 195         uint8_t param_exports;
 196         bool writes_pointsize;
 197         bool writes_layer;
 198         bool writes_viewport_index;
 199         bool export_prim_id;
 200         unsigned pos_exports;
 201 };
 202
 203 struct radv_es_output_info {
 204        uint32_t esgs_itemsize;
 205 };
 206
 207 struct gfx9_gs_info {
 208         uint32_t vgt_gs_onchip_cntl;
 209         uint32_t vgt_gs_max_prims_per_subgroup;
 210         uint32_t vgt_esgs_ring_itemsize;
 211         uint32_t lds_size;
 212 };
 213
 214 struct gfx10_ngg_info {
 215         uint16_t ngg_emit_size; /* in dwords */
 216         uint32_t hw_max_esverts;
 217         uint32_t max_gsprims;
 218         uint32_t max_out_verts;
 219         uint32_t prim_amp_factor;
 220         uint32_t vgt_esgs_ring_itemsize;
 221         uint32_t esgs_ring_size;
 222         bool max_vert_out_per_gs_instance;
 223 };
 224
 225 struct radv_shader_info {
 226         bool loads_push_constants;
 227         bool loads_dynamic_offsets;
 228         uint8_t min_push_constant_used;
 229         uint8_t max_push_constant_used;
 230         bool has_only_32bit_push_constants;
 231         bool has_indirect_push_constants;
 232         uint8_t num_inline_push_consts;
 233         uint8_t base_inline_push_consts;
 234         uint32_t desc_set_used_mask;
 235         bool needs_multiview_view_index;
 236         bool uses_invocation_id;
 237         bool uses_prim_id;
 238         uint8_t wave_size;
 239         uint8_t ballot_bit_size;
 240         struct radv_userdata_locations user_sgprs_locs;
 241         unsigned num_user_sgprs;
 242         unsigned num_input_sgprs;
 243         unsigned num_input_vgprs;
 244         unsigned private_mem_vgprs;
 245         bool need_indirect_descriptor_sets;
 246         bool is_ngg;
 247         bool is_ngg_passthrough;
 248         struct {
 249                 uint64_t ls_outputs_written;
 250                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 251                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 252                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 253                 bool needs_draw_id;
 254                 bool needs_instance_id;
 255                 struct radv_vs_output_info outinfo;
 256                 struct radv_es_output_info es_info;
 257                 bool as_es;
 258                 bool as_ls;
 259                 bool export_prim_id;
 260         } vs;
 261         struct {
 262                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 263                 uint8_t num_stream_output_components[4];
 264                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 265                 uint8_t max_stream;
 266                 bool writes_memory;
 267                 unsigned gsvs_vertex_size;
 268                 unsigned max_gsvs_emit_size;
 269                 unsigned vertices_in;
 270                 unsigned vertices_out;
 271                 unsigned output_prim;
 272                 unsigned invocations;
 273                 unsigned es_type; /* GFX9: VS or TES */
 274         } gs;
 275         struct {
 276                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 277                 struct radv_vs_output_info outinfo;
 278                 struct radv_es_output_info es_info;
 279                 bool as_es;
 280                 unsigned primitive_mode;
 281                 enum gl_tess_spacing spacing;
 282                 bool ccw;
 283                 bool point_mode;
 284                 bool export_prim_id;
 285         } tes;
 286         struct {
 287                 bool force_persample;
 288                 bool needs_sample_positions;
 289                 bool writes_memory;
 290                 bool writes_z;
 291                 bool writes_stencil;
 292                 bool writes_sample_mask;
 293                 bool has_pcoord;
 294                 bool prim_id_input;
 295                 bool layer_input;
 296                 uint8_t num_input_clips_culls;
 297                 uint32_t input_mask;
 298                 uint32_t flat_shaded_mask;
 299                 uint32_t explicit_shaded_mask;
 300                 uint32_t float16_shaded_mask;
 301                 uint32_t num_interp;
 302                 bool can_discard;
 303                 bool early_fragment_test;
 304                 bool post_depth_coverage;
 305         } ps;
 306         struct {
 307                 bool uses_grid_size;
 308                 bool uses_block_id[3];
 309                 bool uses_thread_id[3];
 310                 bool uses_local_invocation_idx;
 311                 unsigned block_size[3];
 312         } cs;
 313         struct {
 314                 uint64_t outputs_written;
 315                 uint64_t patch_outputs_written;
 316                 unsigned tcs_vertices_out;
 317                 uint32_t num_patches;
 318                 uint32_t lds_size;
 319         } tcs;
 320
 321         struct radv_streamout_info so;
 322
 323         struct gfx9_gs_info gs_ring_info;
 324         struct gfx10_ngg_info ngg_info;
 325
 326         unsigned float_controls_mode;
 327 };
 328
 329 enum radv_shader_binary_type {
 330         RADV_BINARY_TYPE_LEGACY,
 331         RADV_BINARY_TYPE_RTLD
 332 };
 333
 334 struct radv_shader_binary {
 335         enum radv_shader_binary_type type;
 336         gl_shader_stage stage;
 337         bool is_gs_copy_shader;
 338
 339         struct radv_shader_info info;
 340
 341         /* Self-referential size so we avoid consistency issues. */
 342         uint32_t total_size;
 343 };
 344
 345 struct radv_shader_binary_legacy {
 346         struct radv_shader_binary base;
 347         struct ac_shader_config config;
 348         unsigned code_size;
 349         unsigned exec_size;
 350         unsigned ir_size;
 351         unsigned disasm_size;
 352
 353         /* data has size of code_size + ir_size + disasm_size + 2, where
 354          * the +2 is for 0 of the ir strings. */
 355         uint8_t data[0];
 356 };
 357
 358 struct radv_shader_binary_rtld {
 359         struct radv_shader_binary base;
 360         unsigned elf_size;
 361         unsigned llvm_ir_size;
 362         uint8_t data[0];
 363 };
 364
 365 struct radv_shader_variant {
 366         uint32_t ref_count;
 367
 368         struct radeon_winsys_bo *bo;
 369         uint64_t bo_offset;
 370         struct ac_shader_config config;
 371         uint32_t code_size;
 372         uint32_t exec_size;
 373         struct radv_shader_info info;
 374
 375         /* debug only */
 376         char *spirv;
 377         uint32_t spirv_size;
 378         char *nir_string;
 379         char *disasm_string;
 380         char *ir_string;
 381
 382         struct list_head slab_list;
 383 };
 384
 385 struct radv_shader_slab {
 386         struct list_head slabs;
 387         struct list_head shaders;
 388         struct radeon_winsys_bo *bo;
 389         uint64_t size;
 390         char *ptr;
 391 };
 392
 393 void
 394 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 395                   bool allow_copies);
 396 bool
 397 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 398                              const struct radv_pipeline_layout *layout);
 399
 400 nir_shader *
 401 radv_shader_compile_to_nir(struct radv_device *device,
 402                            struct radv_shader_module *module,
 403                            const char *entrypoint_name,
 404                            gl_shader_stage stage,
 405                            const VkSpecializationInfo *spec_info,
 406                            const VkPipelineCreateFlags flags,
 407                            const struct radv_pipeline_layout *layout,
 408                            unsigned subgroup_size, unsigned ballot_bit_size);
 409
 410 void *
 411 radv_alloc_shader_memory(struct radv_device *device,
 412                           struct radv_shader_variant *shader);
 413
 414 void
 415 radv_destroy_shader_slabs(struct radv_device *device);
 416
 417 void
 418 radv_create_shaders(struct radv_pipeline *pipeline,
 419                     struct radv_device *device,
 420                     struct radv_pipeline_cache *cache,
 421                     const struct radv_pipeline_key *key,
 422                     const VkPipelineShaderStageCreateInfo **pStages,
 423                     const VkPipelineCreateFlags flags,
 424                     VkPipelineCreationFeedbackEXT *pipeline_feedback,
 425                     VkPipelineCreationFeedbackEXT **stage_feedbacks);
 426
 427 struct radv_shader_variant *
 428 radv_shader_variant_create(struct radv_device *device,
 429                            const struct radv_shader_binary *binary,
 430                            bool keep_shader_info);
 431 struct radv_shader_variant *
 432 radv_shader_variant_compile(struct radv_device *device,
 433                             struct radv_shader_module *module,
 434                             struct nir_shader *const *shaders,
 435                             int shader_count,
 436                             struct radv_pipeline_layout *layout,
 437                             const struct radv_shader_variant_key *key,
 438                             struct radv_shader_info *info,
 439                             bool keep_shader_info,
 440                             struct radv_shader_binary **binary_out);
 441
 442 struct radv_shader_variant *
 443 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 444                            struct radv_shader_info *info,
 445                            struct radv_shader_binary **binary_out,
 446                            bool multiview,  bool keep_shader_info);
 447
 448 void
 449 radv_shader_variant_destroy(struct radv_device *device,
 450                             struct radv_shader_variant *variant);
 451
 452
 453 unsigned
 454 radv_get_max_waves(struct radv_device *device,
 455                    struct radv_shader_variant *variant,
 456                    gl_shader_stage stage);
 457
 458 unsigned
 459 radv_get_max_workgroup_size(enum chip_class chip_class,
 460                             gl_shader_stage stage,
 461                             const unsigned *sizes);
 462
 463 const char *
 464 radv_get_shader_name(struct radv_shader_info *info,
 465                      gl_shader_stage stage);
 466
 467 void
 468 radv_shader_dump_stats(struct radv_device *device,
 469                        struct radv_shader_variant *variant,
 470                        gl_shader_stage stage,
 471                        FILE *file);
 472
 473 bool
 474 radv_can_dump_shader(struct radv_device *device,
 475                      struct radv_shader_module *module,
 476                      bool is_gs_copy_shader);
 477
 478 bool
 479 radv_can_dump_shader_stats(struct radv_device *device,
 480                            struct radv_shader_module *module);
 481
 482 static inline unsigned
 483 shader_io_get_unique_index(gl_varying_slot slot)
 484 {
 485         /* handle patch indices separate */
 486         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 487                 return 0;
 488         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 489                 return 1;
 490         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 491                 return 2 + (slot - VARYING_SLOT_PATCH0);
 492         if (slot == VARYING_SLOT_POS)
 493                 return 0;
 494         if (slot == VARYING_SLOT_PSIZ)
 495                 return 1;
 496         if (slot == VARYING_SLOT_CLIP_DIST0)
 497                 return 2;
 498         if (slot == VARYING_SLOT_CLIP_DIST1)
 499                 return 3;
 500         /* 3 is reserved for clip dist as well */
 501         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 502                 return 4 + (slot - VARYING_SLOT_VAR0);
 503         unreachable("illegal slot in get unique index\n");
 504 }
 505
 506 static inline unsigned
 507 calculate_tess_lds_size(unsigned tcs_num_input_vertices,
 508                         unsigned tcs_num_output_vertices,
 509                         unsigned tcs_num_inputs,
 510                         unsigned tcs_num_patches,
 511                         unsigned tcs_outputs_written,
 512                         unsigned tcs_per_patch_outputs_written)
 513 {
 514         unsigned num_tcs_outputs = util_last_bit64(tcs_outputs_written);
 515         unsigned num_tcs_patch_outputs = util_last_bit64(tcs_per_patch_outputs_written);
 516
 517         unsigned input_vertex_size = tcs_num_inputs * 16;
 518         unsigned output_vertex_size = num_tcs_outputs * 16;
 519
 520         unsigned input_patch_size = tcs_num_input_vertices * input_vertex_size;
 521
 522         unsigned pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
 523         unsigned output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
 524
 525         unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
 526
 527         return output_patch0_offset + output_patch_size * tcs_num_patches;
 528 }
 529
 530 static inline unsigned
 531 get_tcs_num_patches(unsigned tcs_num_input_vertices,
 532                         unsigned tcs_num_output_vertices,
 533                         unsigned tcs_num_inputs,
 534                         unsigned tcs_outputs_written,
 535                         unsigned tcs_per_patch_outputs_written,
 536                         unsigned tess_offchip_block_dw_size,
 537                         enum chip_class chip_class,
 538                         enum radeon_family family)
 539 {
 540         uint32_t input_vertex_size = tcs_num_inputs * 16;
 541         uint32_t input_patch_size = tcs_num_input_vertices * input_vertex_size;
 542         uint32_t num_tcs_outputs = util_last_bit64(tcs_outputs_written);
 543         uint32_t num_tcs_patch_outputs = util_last_bit64(tcs_per_patch_outputs_written);
 544         uint32_t output_vertex_size = num_tcs_outputs * 16;
 545         uint32_t pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
 546         uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
 547
 548         /* Ensure that we only need one wave per SIMD so we don't need to check
 549          * resource usage. Also ensures that the number of tcs in and out
 550          * vertices per threadgroup are at most 256.
 551          */
 552         unsigned num_patches = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices) * 4;
 553         /* Make sure that the data fits in LDS. This assumes the shaders only
 554          * use LDS for the inputs and outputs.
 555          */
 556         unsigned hardware_lds_size = 32768;
 557
 558         /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
 559          * threadgroup, even though there is more than 32 KiB LDS.
 560          *
 561          * Test: dEQP-VK.tessellation.shader_input_output.barrier
 562          */
 563         if (chip_class >= GFX7 && family != CHIP_STONEY)
 564                 hardware_lds_size = 65536;
 565
 566         num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
 567         /* Make sure the output data fits in the offchip buffer */
 568         num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size);
 569         /* Not necessary for correctness, but improves performance. The
 570          * specific value is taken from the proprietary driver.
 571          */
 572         num_patches = MIN2(num_patches, 40);
 573
 574         /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
 575         if (chip_class == GFX6) {
 576                 unsigned one_wave = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices);
 577                 num_patches = MIN2(num_patches, one_wave);
 578         }
 579         return num_patches;
 580 }
 581
 582 void
 583 radv_lower_fs_io(nir_shader *nir);
 584
 585 #endif