2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_binary.h"
32 #include "amd_family.h"
33 #include "radv_constants.h"
36 #include "vulkan/vulkan.h"
40 struct radv_shader_module
{
41 struct nir_shader
*nir
;
42 unsigned char sha1
[20];
48 RADV_ALPHA_ADJUST_NONE
= 0,
49 RADV_ALPHA_ADJUST_SNORM
= 1,
50 RADV_ALPHA_ADJUST_SINT
= 2,
51 RADV_ALPHA_ADJUST_SSCALED
= 3,
54 struct radv_vs_out_key
{
58 uint32_t export_prim_id
:1;
59 uint32_t export_layer_id
:1;
60 uint32_t export_clip_dists
:1;
63 struct radv_vs_variant_key
{
64 struct radv_vs_out_key out
;
66 uint32_t instance_rate_inputs
;
67 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
68 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
69 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
70 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
71 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
73 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
74 * so we may need to fix it up. */
75 uint64_t alpha_adjust
;
77 /* For some formats the channels have to be shuffled. */
78 uint32_t post_shuffle
;
80 /* Output primitive type. */
84 struct radv_tes_variant_key
{
85 struct radv_vs_out_key out
;
88 uint8_t tcs_num_outputs
;
91 struct radv_tcs_variant_key
{
92 struct radv_vs_variant_key vs_key
;
93 unsigned primitive_mode
;
94 unsigned input_vertices
;
96 uint32_t tes_reads_tess_factors
:1;
99 struct radv_fs_variant_key
{
101 uint8_t log2_ps_iter_samples
;
107 struct radv_shader_variant_key
{
109 struct radv_vs_variant_key vs
;
110 struct radv_fs_variant_key fs
;
111 struct radv_tes_variant_key tes
;
112 struct radv_tcs_variant_key tcs
;
114 /* A common prefix of the vs and tes keys. */
115 struct radv_vs_out_key vs_common_out
;
117 bool has_multiview_view_index
;
120 struct radv_nir_compiler_options
{
121 struct radv_pipeline_layout
*layout
;
122 struct radv_shader_variant_key key
;
125 bool clamp_shadow_reference
;
126 bool robust_buffer_access
;
131 bool has_ls_vgpr_init_bug
;
132 bool use_ngg_streamout
;
133 enum radeon_family family
;
134 enum chip_class chip_class
;
135 uint32_t tess_offchip_block_dw_size
;
136 uint32_t address32_hi
;
140 AC_UD_SCRATCH_RING_OFFSETS
= 0,
141 AC_UD_PUSH_CONSTANTS
= 1,
142 AC_UD_INLINE_PUSH_CONSTANTS
= 2,
143 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 3,
144 AC_UD_VIEW_INDEX
= 4,
145 AC_UD_STREAMOUT_BUFFERS
= 5,
146 AC_UD_SHADER_START
= 6,
147 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
148 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
151 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
156 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
159 struct radv_stream_output
{
163 uint8_t component_mask
;
167 struct radv_streamout_info
{
168 uint16_t num_outputs
;
169 struct radv_stream_output outputs
[MAX_SO_OUTPUTS
];
170 uint16_t strides
[MAX_SO_BUFFERS
];
171 uint32_t enabled_stream_buffers_mask
;
174 struct radv_userdata_info
{
179 struct radv_userdata_locations
{
180 struct radv_userdata_info descriptor_sets
[MAX_SETS
];
181 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
182 uint32_t descriptor_sets_enabled
;
185 struct radv_vs_output_info
{
186 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
187 uint8_t clip_dist_mask
;
188 uint8_t cull_dist_mask
;
189 uint8_t param_exports
;
190 bool writes_pointsize
;
192 bool writes_viewport_index
;
194 unsigned pos_exports
;
197 struct radv_es_output_info
{
198 uint32_t esgs_itemsize
;
201 struct gfx9_gs_info
{
202 uint32_t vgt_gs_onchip_cntl
;
203 uint32_t vgt_gs_max_prims_per_subgroup
;
204 uint32_t vgt_esgs_ring_itemsize
;
208 struct gfx10_ngg_info
{
209 uint16_t ngg_emit_size
; /* in dwords */
210 uint32_t hw_max_esverts
;
211 uint32_t max_gsprims
;
212 uint32_t max_out_verts
;
213 uint32_t prim_amp_factor
;
214 uint32_t vgt_esgs_ring_itemsize
;
215 uint32_t esgs_ring_size
;
216 bool max_vert_out_per_gs_instance
;
219 struct radv_shader_info
{
220 bool loads_push_constants
;
221 bool loads_dynamic_offsets
;
222 uint8_t min_push_constant_used
;
223 uint8_t max_push_constant_used
;
224 bool has_only_32bit_push_constants
;
225 bool has_indirect_push_constants
;
226 uint8_t num_inline_push_consts
;
227 uint8_t base_inline_push_consts
;
228 uint32_t desc_set_used_mask
;
229 bool needs_multiview_view_index
;
230 bool uses_invocation_id
;
233 struct radv_userdata_locations user_sgprs_locs
;
234 unsigned num_user_sgprs
;
235 unsigned num_input_sgprs
;
236 unsigned num_input_vgprs
;
237 unsigned private_mem_vgprs
;
238 bool need_indirect_descriptor_sets
;
241 uint64_t ls_outputs_written
;
242 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
243 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
244 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
246 bool needs_instance_id
;
247 struct radv_vs_output_info outinfo
;
248 struct radv_es_output_info es_info
;
254 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
255 uint8_t num_stream_output_components
[4];
256 uint8_t output_streams
[VARYING_SLOT_VAR31
+ 1];
259 unsigned gsvs_vertex_size
;
260 unsigned max_gsvs_emit_size
;
261 unsigned vertices_in
;
262 unsigned vertices_out
;
263 unsigned output_prim
;
264 unsigned invocations
;
265 unsigned es_type
; /* GFX9: VS or TES */
268 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
269 struct radv_vs_output_info outinfo
;
270 struct radv_es_output_info es_info
;
272 unsigned primitive_mode
;
273 enum gl_tess_spacing spacing
;
279 bool force_persample
;
280 bool needs_sample_positions
;
284 bool writes_sample_mask
;
288 uint8_t num_input_clips_culls
;
290 uint32_t flat_shaded_mask
;
291 uint32_t float16_shaded_mask
;
294 bool early_fragment_test
;
295 bool post_depth_coverage
;
299 bool uses_block_id
[3];
300 bool uses_thread_id
[3];
301 bool uses_local_invocation_idx
;
302 unsigned block_size
[3];
305 uint64_t outputs_written
;
306 uint64_t patch_outputs_written
;
307 unsigned tcs_vertices_out
;
308 uint32_t num_patches
;
312 struct radv_streamout_info so
;
314 struct gfx9_gs_info gs_ring_info
;
315 struct gfx10_ngg_info ngg_info
;
317 unsigned float_controls_mode
;
320 enum radv_shader_binary_type
{
321 RADV_BINARY_TYPE_LEGACY
,
322 RADV_BINARY_TYPE_RTLD
325 struct radv_shader_binary
{
326 enum radv_shader_binary_type type
;
327 gl_shader_stage stage
;
328 bool is_gs_copy_shader
;
330 struct radv_shader_info info
;
332 /* Self-referential size so we avoid consistency issues. */
336 struct radv_shader_binary_legacy
{
337 struct radv_shader_binary base
;
338 struct ac_shader_config config
;
342 unsigned disasm_size
;
344 /* data has size of code_size + ir_size + disasm_size + 2, where
345 * the +2 is for 0 of the ir strings. */
349 struct radv_shader_binary_rtld
{
350 struct radv_shader_binary base
;
352 unsigned llvm_ir_size
;
356 struct radv_shader_variant
{
359 struct radeon_winsys_bo
*bo
;
361 struct ac_shader_config config
;
364 struct radv_shader_info info
;
374 struct list_head slab_list
;
377 struct radv_shader_slab
{
378 struct list_head slabs
;
379 struct list_head shaders
;
380 struct radeon_winsys_bo
*bo
;
386 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
389 radv_nir_lower_ycbcr_textures(nir_shader
*shader
,
390 const struct radv_pipeline_layout
*layout
);
393 radv_shader_compile_to_nir(struct radv_device
*device
,
394 struct radv_shader_module
*module
,
395 const char *entrypoint_name
,
396 gl_shader_stage stage
,
397 const VkSpecializationInfo
*spec_info
,
398 const VkPipelineCreateFlags flags
,
399 const struct radv_pipeline_layout
*layout
,
403 radv_alloc_shader_memory(struct radv_device
*device
,
404 struct radv_shader_variant
*shader
);
407 radv_destroy_shader_slabs(struct radv_device
*device
);
410 radv_create_shaders(struct radv_pipeline
*pipeline
,
411 struct radv_device
*device
,
412 struct radv_pipeline_cache
*cache
,
413 const struct radv_pipeline_key
*key
,
414 const VkPipelineShaderStageCreateInfo
**pStages
,
415 const VkPipelineCreateFlags flags
,
416 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
417 VkPipelineCreationFeedbackEXT
**stage_feedbacks
);
419 struct radv_shader_variant
*
420 radv_shader_variant_create(struct radv_device
*device
,
421 const struct radv_shader_binary
*binary
,
422 bool keep_shader_info
);
423 struct radv_shader_variant
*
424 radv_shader_variant_compile(struct radv_device
*device
,
425 struct radv_shader_module
*module
,
426 struct nir_shader
*const *shaders
,
428 struct radv_pipeline_layout
*layout
,
429 const struct radv_shader_variant_key
*key
,
430 struct radv_shader_info
*info
,
431 bool keep_shader_info
,
433 struct radv_shader_binary
**binary_out
);
435 struct radv_shader_variant
*
436 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
437 struct radv_shader_info
*info
,
438 struct radv_shader_binary
**binary_out
,
439 bool multiview
, bool keep_shader_info
);
442 radv_shader_variant_destroy(struct radv_device
*device
,
443 struct radv_shader_variant
*variant
);
447 radv_get_max_waves(struct radv_device
*device
,
448 struct radv_shader_variant
*variant
,
449 gl_shader_stage stage
);
452 radv_get_max_workgroup_size(enum chip_class chip_class
,
453 gl_shader_stage stage
,
454 const unsigned *sizes
);
457 radv_get_shader_name(struct radv_shader_info
*info
,
458 gl_shader_stage stage
);
461 radv_shader_dump_stats(struct radv_device
*device
,
462 struct radv_shader_variant
*variant
,
463 gl_shader_stage stage
,
467 radv_can_dump_shader(struct radv_device
*device
,
468 struct radv_shader_module
*module
,
469 bool is_gs_copy_shader
);
472 radv_can_dump_shader_stats(struct radv_device
*device
,
473 struct radv_shader_module
*module
);
476 shader_io_get_unique_index(gl_varying_slot slot
);
479 radv_lower_fs_io(nir_shader
*nir
);