2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_binary.h"
32 #include "amd_family.h"
33 #include "radv_constants.h"
36 #include "vulkan/vulkan.h"
40 struct radv_shader_module
{
41 struct nir_shader
*nir
;
42 unsigned char sha1
[20];
48 RADV_ALPHA_ADJUST_NONE
= 0,
49 RADV_ALPHA_ADJUST_SNORM
= 1,
50 RADV_ALPHA_ADJUST_SINT
= 2,
51 RADV_ALPHA_ADJUST_SSCALED
= 3,
54 struct radv_vs_out_key
{
58 uint32_t export_prim_id
:1;
59 uint32_t export_layer_id
:1;
60 uint32_t export_clip_dists
:1;
63 struct radv_vs_variant_key
{
64 struct radv_vs_out_key out
;
66 uint32_t instance_rate_inputs
;
67 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
68 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
69 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
70 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
71 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
73 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
74 * so we may need to fix it up. */
75 uint64_t alpha_adjust
;
77 /* For some formats the channels have to be shuffled. */
78 uint32_t post_shuffle
;
80 /* Output primitive type. */
84 struct radv_tes_variant_key
{
85 struct radv_vs_out_key out
;
88 uint8_t tcs_num_outputs
;
91 struct radv_tcs_variant_key
{
92 struct radv_vs_variant_key vs_key
;
93 unsigned primitive_mode
;
94 unsigned input_vertices
;
96 uint32_t tes_reads_tess_factors
:1;
99 struct radv_fs_variant_key
{
101 uint8_t log2_ps_iter_samples
;
107 struct radv_cs_variant_key
{
108 uint8_t subgroup_size
;
111 struct radv_shader_variant_key
{
113 struct radv_vs_variant_key vs
;
114 struct radv_fs_variant_key fs
;
115 struct radv_tes_variant_key tes
;
116 struct radv_tcs_variant_key tcs
;
117 struct radv_cs_variant_key cs
;
119 /* A common prefix of the vs and tes keys. */
120 struct radv_vs_out_key vs_common_out
;
122 bool has_multiview_view_index
;
125 struct radv_nir_compiler_options
{
126 struct radv_pipeline_layout
*layout
;
127 struct radv_shader_variant_key key
;
128 bool explicit_scratch_args
;
129 bool clamp_shadow_reference
;
130 bool robust_buffer_access
;
135 bool has_ls_vgpr_init_bug
;
136 bool use_ngg_streamout
;
137 enum radeon_family family
;
138 enum chip_class chip_class
;
139 uint32_t tess_offchip_block_dw_size
;
140 uint32_t address32_hi
;
144 AC_UD_SCRATCH_RING_OFFSETS
= 0,
145 AC_UD_PUSH_CONSTANTS
= 1,
146 AC_UD_INLINE_PUSH_CONSTANTS
= 2,
147 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 3,
148 AC_UD_VIEW_INDEX
= 4,
149 AC_UD_STREAMOUT_BUFFERS
= 5,
150 AC_UD_SHADER_START
= 6,
151 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
152 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
155 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
160 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
163 struct radv_stream_output
{
167 uint8_t component_mask
;
171 struct radv_streamout_info
{
172 uint16_t num_outputs
;
173 struct radv_stream_output outputs
[MAX_SO_OUTPUTS
];
174 uint16_t strides
[MAX_SO_BUFFERS
];
175 uint32_t enabled_stream_buffers_mask
;
178 struct radv_userdata_info
{
183 struct radv_userdata_locations
{
184 struct radv_userdata_info descriptor_sets
[MAX_SETS
];
185 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
186 uint32_t descriptor_sets_enabled
;
189 struct radv_vs_output_info
{
190 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
191 uint8_t clip_dist_mask
;
192 uint8_t cull_dist_mask
;
193 uint8_t param_exports
;
194 bool writes_pointsize
;
196 bool writes_viewport_index
;
198 unsigned pos_exports
;
201 struct radv_es_output_info
{
202 uint32_t esgs_itemsize
;
205 struct gfx9_gs_info
{
206 uint32_t vgt_gs_onchip_cntl
;
207 uint32_t vgt_gs_max_prims_per_subgroup
;
208 uint32_t vgt_esgs_ring_itemsize
;
212 struct gfx10_ngg_info
{
213 uint16_t ngg_emit_size
; /* in dwords */
214 uint32_t hw_max_esverts
;
215 uint32_t max_gsprims
;
216 uint32_t max_out_verts
;
217 uint32_t prim_amp_factor
;
218 uint32_t vgt_esgs_ring_itemsize
;
219 uint32_t esgs_ring_size
;
220 bool max_vert_out_per_gs_instance
;
223 struct radv_shader_info
{
224 bool loads_push_constants
;
225 bool loads_dynamic_offsets
;
226 uint8_t min_push_constant_used
;
227 uint8_t max_push_constant_used
;
228 bool has_only_32bit_push_constants
;
229 bool has_indirect_push_constants
;
230 uint8_t num_inline_push_consts
;
231 uint8_t base_inline_push_consts
;
232 uint32_t desc_set_used_mask
;
233 bool needs_multiview_view_index
;
234 bool uses_invocation_id
;
237 struct radv_userdata_locations user_sgprs_locs
;
238 unsigned num_user_sgprs
;
239 unsigned num_input_sgprs
;
240 unsigned num_input_vgprs
;
241 unsigned private_mem_vgprs
;
242 bool need_indirect_descriptor_sets
;
245 uint64_t ls_outputs_written
;
246 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
247 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
248 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
250 bool needs_instance_id
;
251 struct radv_vs_output_info outinfo
;
252 struct radv_es_output_info es_info
;
258 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
259 uint8_t num_stream_output_components
[4];
260 uint8_t output_streams
[VARYING_SLOT_VAR31
+ 1];
263 unsigned gsvs_vertex_size
;
264 unsigned max_gsvs_emit_size
;
265 unsigned vertices_in
;
266 unsigned vertices_out
;
267 unsigned output_prim
;
268 unsigned invocations
;
269 unsigned es_type
; /* GFX9: VS or TES */
272 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
273 struct radv_vs_output_info outinfo
;
274 struct radv_es_output_info es_info
;
276 unsigned primitive_mode
;
277 enum gl_tess_spacing spacing
;
283 bool force_persample
;
284 bool needs_sample_positions
;
288 bool writes_sample_mask
;
292 uint8_t num_input_clips_culls
;
294 uint32_t flat_shaded_mask
;
295 uint32_t float16_shaded_mask
;
298 bool early_fragment_test
;
299 bool post_depth_coverage
;
303 bool uses_block_id
[3];
304 bool uses_thread_id
[3];
305 bool uses_local_invocation_idx
;
306 unsigned block_size
[3];
309 uint64_t outputs_written
;
310 uint64_t patch_outputs_written
;
311 unsigned tcs_vertices_out
;
312 uint32_t num_patches
;
316 struct radv_streamout_info so
;
318 struct gfx9_gs_info gs_ring_info
;
319 struct gfx10_ngg_info ngg_info
;
321 unsigned float_controls_mode
;
324 enum radv_shader_binary_type
{
325 RADV_BINARY_TYPE_LEGACY
,
326 RADV_BINARY_TYPE_RTLD
329 struct radv_shader_binary
{
330 enum radv_shader_binary_type type
;
331 gl_shader_stage stage
;
332 bool is_gs_copy_shader
;
334 struct radv_shader_info info
;
336 /* Self-referential size so we avoid consistency issues. */
340 struct radv_shader_binary_legacy
{
341 struct radv_shader_binary base
;
342 struct ac_shader_config config
;
346 unsigned disasm_size
;
348 /* data has size of code_size + ir_size + disasm_size + 2, where
349 * the +2 is for 0 of the ir strings. */
353 struct radv_shader_binary_rtld
{
354 struct radv_shader_binary base
;
356 unsigned llvm_ir_size
;
360 struct radv_shader_variant
{
363 struct radeon_winsys_bo
*bo
;
365 struct ac_shader_config config
;
368 struct radv_shader_info info
;
378 struct list_head slab_list
;
381 struct radv_shader_slab
{
382 struct list_head slabs
;
383 struct list_head shaders
;
384 struct radeon_winsys_bo
*bo
;
390 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
393 radv_nir_lower_ycbcr_textures(nir_shader
*shader
,
394 const struct radv_pipeline_layout
*layout
);
397 radv_shader_compile_to_nir(struct radv_device
*device
,
398 struct radv_shader_module
*module
,
399 const char *entrypoint_name
,
400 gl_shader_stage stage
,
401 const VkSpecializationInfo
*spec_info
,
402 const VkPipelineCreateFlags flags
,
403 const struct radv_pipeline_layout
*layout
,
407 radv_alloc_shader_memory(struct radv_device
*device
,
408 struct radv_shader_variant
*shader
);
411 radv_destroy_shader_slabs(struct radv_device
*device
);
414 radv_create_shaders(struct radv_pipeline
*pipeline
,
415 struct radv_device
*device
,
416 struct radv_pipeline_cache
*cache
,
417 const struct radv_pipeline_key
*key
,
418 const VkPipelineShaderStageCreateInfo
**pStages
,
419 const VkPipelineCreateFlags flags
,
420 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
421 VkPipelineCreationFeedbackEXT
**stage_feedbacks
);
423 struct radv_shader_variant
*
424 radv_shader_variant_create(struct radv_device
*device
,
425 const struct radv_shader_binary
*binary
,
426 bool keep_shader_info
);
427 struct radv_shader_variant
*
428 radv_shader_variant_compile(struct radv_device
*device
,
429 struct radv_shader_module
*module
,
430 struct nir_shader
*const *shaders
,
432 struct radv_pipeline_layout
*layout
,
433 const struct radv_shader_variant_key
*key
,
434 struct radv_shader_info
*info
,
435 bool keep_shader_info
,
437 struct radv_shader_binary
**binary_out
);
439 struct radv_shader_variant
*
440 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
441 struct radv_shader_info
*info
,
442 struct radv_shader_binary
**binary_out
,
443 bool multiview
, bool keep_shader_info
);
446 radv_shader_variant_destroy(struct radv_device
*device
,
447 struct radv_shader_variant
*variant
);
451 radv_get_max_waves(struct radv_device
*device
,
452 struct radv_shader_variant
*variant
,
453 gl_shader_stage stage
);
456 radv_get_max_workgroup_size(enum chip_class chip_class
,
457 gl_shader_stage stage
,
458 const unsigned *sizes
);
461 radv_get_shader_name(struct radv_shader_info
*info
,
462 gl_shader_stage stage
);
465 radv_shader_dump_stats(struct radv_device
*device
,
466 struct radv_shader_variant
*variant
,
467 gl_shader_stage stage
,
471 radv_can_dump_shader(struct radv_device
*device
,
472 struct radv_shader_module
*module
,
473 bool is_gs_copy_shader
);
476 radv_can_dump_shader_stats(struct radv_device
*device
,
477 struct radv_shader_module
*module
);
480 shader_io_get_unique_index(gl_varying_slot slot
);
483 radv_lower_fs_io(nir_shader
*nir
);