2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_binary.h"
32 #include "amd_family.h"
33 #include "radv_constants.h"
36 #include "vulkan/vulkan.h"
40 struct radv_shader_module
{
41 struct nir_shader
*nir
;
42 unsigned char sha1
[20];
48 RADV_ALPHA_ADJUST_NONE
= 0,
49 RADV_ALPHA_ADJUST_SNORM
= 1,
50 RADV_ALPHA_ADJUST_SINT
= 2,
51 RADV_ALPHA_ADJUST_SSCALED
= 3,
54 struct radv_vs_out_key
{
58 uint32_t export_prim_id
:1;
59 uint32_t export_layer_id
:1;
60 uint32_t export_clip_dists
:1;
63 struct radv_vs_variant_key
{
64 struct radv_vs_out_key out
;
66 uint32_t instance_rate_inputs
;
67 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
68 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
69 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
70 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
71 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
73 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
74 * so we may need to fix it up. */
75 uint64_t alpha_adjust
;
77 /* For some formats the channels have to be shuffled. */
78 uint32_t post_shuffle
;
81 struct radv_tes_variant_key
{
82 struct radv_vs_out_key out
;
85 uint8_t tcs_num_outputs
;
88 struct radv_tcs_variant_key
{
89 struct radv_vs_variant_key vs_key
;
90 unsigned primitive_mode
;
91 unsigned input_vertices
;
93 uint32_t tes_reads_tess_factors
:1;
96 struct radv_fs_variant_key
{
98 uint8_t log2_ps_iter_samples
;
104 struct radv_shader_variant_key
{
106 struct radv_vs_variant_key vs
;
107 struct radv_fs_variant_key fs
;
108 struct radv_tes_variant_key tes
;
109 struct radv_tcs_variant_key tcs
;
111 /* A common prefix of the vs and tes keys. */
112 struct radv_vs_out_key vs_common_out
;
114 bool has_multiview_view_index
;
117 struct radv_nir_compiler_options
{
118 struct radv_pipeline_layout
*layout
;
119 struct radv_shader_variant_key key
;
122 bool clamp_shadow_reference
;
127 enum radeon_family family
;
128 enum chip_class chip_class
;
129 uint32_t tess_offchip_block_dw_size
;
130 uint32_t address32_hi
;
131 uint8_t cs_wave_size
;
135 AC_UD_SCRATCH_RING_OFFSETS
= 0,
136 AC_UD_PUSH_CONSTANTS
= 1,
137 AC_UD_INLINE_PUSH_CONSTANTS
= 2,
138 AC_UD_INDIRECT_DESCRIPTOR_SETS
= 3,
139 AC_UD_VIEW_INDEX
= 4,
140 AC_UD_STREAMOUT_BUFFERS
= 5,
141 AC_UD_SHADER_START
= 6,
142 AC_UD_VS_VERTEX_BUFFERS
= AC_UD_SHADER_START
,
143 AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
146 AC_UD_CS_GRID_SIZE
= AC_UD_SHADER_START
,
151 AC_UD_MAX_UD
= AC_UD_TCS_MAX_UD
,
154 struct radv_stream_output
{
158 uint8_t component_mask
;
162 struct radv_streamout_info
{
163 uint16_t num_outputs
;
164 struct radv_stream_output outputs
[MAX_SO_OUTPUTS
];
165 uint16_t strides
[MAX_SO_BUFFERS
];
166 uint32_t enabled_stream_buffers_mask
;
169 struct radv_shader_info
{
170 bool loads_push_constants
;
171 bool loads_dynamic_offsets
;
172 uint8_t min_push_constant_used
;
173 uint8_t max_push_constant_used
;
174 bool has_only_32bit_push_constants
;
175 bool has_indirect_push_constants
;
176 uint8_t num_inline_push_consts
;
177 uint8_t base_inline_push_consts
;
178 uint32_t desc_set_used_mask
;
179 bool needs_multiview_view_index
;
180 bool uses_invocation_id
;
183 uint64_t ls_outputs_written
;
184 uint8_t input_usage_mask
[VERT_ATTRIB_MAX
];
185 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
186 bool has_vertex_buffers
; /* needs vertex buffers and base/start */
188 bool needs_instance_id
;
191 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
192 uint8_t num_stream_output_components
[4];
193 uint8_t output_streams
[VARYING_SLOT_VAR31
+ 1];
197 uint8_t output_usage_mask
[VARYING_SLOT_VAR31
+ 1];
200 bool force_persample
;
201 bool needs_sample_positions
;
205 bool writes_sample_mask
;
209 uint8_t num_input_clips_culls
;
213 bool uses_block_id
[3];
214 bool uses_thread_id
[3];
215 bool uses_local_invocation_idx
;
218 uint64_t outputs_written
;
219 uint64_t patch_outputs_written
;
222 struct radv_streamout_info so
;
225 struct radv_userdata_info
{
230 struct radv_userdata_locations
{
231 struct radv_userdata_info descriptor_sets
[MAX_SETS
];
232 struct radv_userdata_info shader_data
[AC_UD_MAX_UD
];
233 uint32_t descriptor_sets_enabled
;
236 struct radv_vs_output_info
{
237 uint8_t vs_output_param_offset
[VARYING_SLOT_MAX
];
238 uint8_t clip_dist_mask
;
239 uint8_t cull_dist_mask
;
240 uint8_t param_exports
;
241 bool writes_pointsize
;
243 bool writes_viewport_index
;
245 unsigned pos_exports
;
248 struct radv_es_output_info
{
249 uint32_t esgs_itemsize
;
252 struct radv_shader_variant_info
{
253 struct radv_userdata_locations user_sgprs_locs
;
254 struct radv_shader_info info
;
255 unsigned num_user_sgprs
;
256 unsigned num_input_sgprs
;
257 unsigned num_input_vgprs
;
258 unsigned private_mem_vgprs
;
259 bool need_indirect_descriptor_sets
;
263 struct radv_vs_output_info outinfo
;
264 struct radv_es_output_info es_info
;
272 uint32_t flat_shaded_mask
;
273 uint32_t float16_shaded_mask
;
275 bool early_fragment_test
;
276 bool post_depth_coverage
;
279 unsigned block_size
[3];
282 unsigned vertices_in
;
283 unsigned vertices_out
;
284 unsigned output_prim
;
285 unsigned invocations
;
286 unsigned gsvs_vertex_size
;
287 unsigned max_gsvs_emit_size
;
288 unsigned es_type
; /* GFX9: VS or TES */
291 unsigned tcs_vertices_out
;
292 uint32_t num_patches
;
296 struct radv_vs_output_info outinfo
;
297 struct radv_es_output_info es_info
;
299 unsigned primitive_mode
;
300 enum gl_tess_spacing spacing
;
308 enum radv_shader_binary_type
{
309 RADV_BINARY_TYPE_LEGACY
,
310 RADV_BINARY_TYPE_RTLD
313 struct radv_shader_binary
{
314 enum radv_shader_binary_type type
;
315 gl_shader_stage stage
;
316 bool is_gs_copy_shader
;
318 struct radv_shader_variant_info variant_info
;
320 /* Self-referential size so we avoid consistency issues. */
324 struct radv_shader_binary_legacy
{
325 struct radv_shader_binary base
;
326 struct ac_shader_config config
;
328 unsigned llvm_ir_size
;
329 unsigned disasm_size
;
331 /* data has size of code_size + llvm_ir_size + disasm_size + 2, where
332 * the +2 is for 0 of the ir strings. */
336 struct radv_shader_binary_rtld
{
337 struct radv_shader_binary base
;
339 unsigned llvm_ir_size
;
343 struct radv_shader_variant
{
346 struct radeon_winsys_bo
*bo
;
348 struct ac_shader_config config
;
350 struct radv_shader_variant_info info
;
355 struct nir_shader
*nir
;
357 char *llvm_ir_string
;
359 struct list_head slab_list
;
362 struct radv_shader_slab
{
363 struct list_head slabs
;
364 struct list_head shaders
;
365 struct radeon_winsys_bo
*bo
;
371 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
374 radv_nir_lower_ycbcr_textures(nir_shader
*shader
,
375 const struct radv_pipeline_layout
*layout
);
378 radv_shader_compile_to_nir(struct radv_device
*device
,
379 struct radv_shader_module
*module
,
380 const char *entrypoint_name
,
381 gl_shader_stage stage
,
382 const VkSpecializationInfo
*spec_info
,
383 const VkPipelineCreateFlags flags
,
384 const struct radv_pipeline_layout
*layout
);
387 radv_alloc_shader_memory(struct radv_device
*device
,
388 struct radv_shader_variant
*shader
);
391 radv_destroy_shader_slabs(struct radv_device
*device
);
393 struct radv_shader_variant
*
394 radv_shader_variant_create(struct radv_device
*device
,
395 const struct radv_shader_binary
*binary
);
396 struct radv_shader_variant
*
397 radv_shader_variant_compile(struct radv_device
*device
,
398 struct radv_shader_module
*module
,
399 struct nir_shader
*const *shaders
,
401 struct radv_pipeline_layout
*layout
,
402 const struct radv_shader_variant_key
*key
,
403 struct radv_shader_binary
**binary_out
);
405 struct radv_shader_variant
*
406 radv_create_gs_copy_shader(struct radv_device
*device
, struct nir_shader
*nir
,
407 struct radv_shader_binary
**binary_out
,
411 radv_shader_variant_destroy(struct radv_device
*device
,
412 struct radv_shader_variant
*variant
);
415 radv_get_shader_name(struct radv_shader_variant_info
*info
,
416 gl_shader_stage stage
);
419 radv_shader_dump_stats(struct radv_device
*device
,
420 struct radv_shader_variant
*variant
,
421 gl_shader_stage stage
,
425 radv_can_dump_shader(struct radv_device
*device
,
426 struct radv_shader_module
*module
,
427 bool is_gs_copy_shader
);
430 radv_can_dump_shader_stats(struct radv_device
*device
,
431 struct radv_shader_module
*module
);
434 shader_io_get_unique_index(gl_varying_slot slot
);