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1286a7609e746debcc9190529638aa5ac6a87516
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35
36 static void
37 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
38 struct radeon_cmdbuf *cs,
39 unsigned raster_config,
40 unsigned raster_config_1)
41 {
42 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
43 unsigned raster_config_se[4];
44 unsigned se;
45
46 ac_get_harvested_configs(&physical_device->rad_info,
47 raster_config,
48 &raster_config_1,
49 raster_config_se);
50
51 for (se = 0; se < num_se; se++) {
52 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
53 if (physical_device->rad_info.chip_class < GFX7)
54 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
55 S_00802C_SE_INDEX(se) |
56 S_00802C_SH_BROADCAST_WRITES(1) |
57 S_00802C_INSTANCE_BROADCAST_WRITES(1));
58 else
59 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
60 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
61 S_030800_INSTANCE_BROADCAST_WRITES(1));
62 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
63 }
64
65 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
66 if (physical_device->rad_info.chip_class < GFX7)
67 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
68 S_00802C_SE_BROADCAST_WRITES(1) |
69 S_00802C_SH_BROADCAST_WRITES(1) |
70 S_00802C_INSTANCE_BROADCAST_WRITES(1));
71 else
72 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
73 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
74 S_030800_INSTANCE_BROADCAST_WRITES(1));
75
76 if (physical_device->rad_info.chip_class >= GFX7)
77 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
78 }
79
80 void
81 si_emit_compute(struct radv_physical_device *physical_device,
82 struct radeon_cmdbuf *cs)
83 {
84 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
85 radeon_emit(cs, 0);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88
89 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
90 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
91 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 if (physical_device->rad_info.chip_class >= GFX9) {
106 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
107 physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0);
108 }
109
110 if (physical_device->rad_info.chip_class >= GFX10) {
111 radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0);
112 radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0);
113 radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0);
114 radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0);
115 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
116 radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0);
117 }
118
119 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
120 * and is now per pipe, so it should be handled in the
121 * kernel if we want to use something other than the default value,
122 * which is now 0x22f.
123 */
124 if (physical_device->rad_info.chip_class <= GFX6) {
125 /* XXX: This should be:
126 * (number of compute units) * 4 * (waves per simd) - 1 */
127
128 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
129 0x190 /* Default value */);
130 }
131 }
132
133 /* 12.4 fixed-point */
134 static unsigned radv_pack_float_12p4(float x)
135 {
136 return x <= 0 ? 0 :
137 x >= 4096 ? 0xffff : x * 16;
138 }
139
140 static void
141 si_set_raster_config(struct radv_physical_device *physical_device,
142 struct radeon_cmdbuf *cs)
143 {
144 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
145 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
146 unsigned raster_config, raster_config_1;
147
148 ac_get_raster_config(&physical_device->rad_info,
149 &raster_config,
150 &raster_config_1, NULL);
151
152 /* Always use the default config when all backends are enabled
153 * (or when we failed to determine the enabled backends).
154 */
155 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
156 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
157 raster_config);
158 if (physical_device->rad_info.chip_class >= GFX7)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
160 raster_config_1);
161 } else {
162 si_write_harvested_raster_configs(physical_device, cs,
163 raster_config,
164 raster_config_1);
165 }
166 }
167
168 void
169 si_emit_graphics(struct radv_device *device,
170 struct radeon_cmdbuf *cs)
171 {
172 struct radv_physical_device *physical_device = device->physical_device;
173
174 bool has_clear_state = physical_device->rad_info.has_clear_state;
175 int i;
176
177 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
178 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
179 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
180
181 if (has_clear_state) {
182 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
183 radeon_emit(cs, 0);
184 }
185
186 if (physical_device->rad_info.chip_class <= GFX8)
187 si_set_raster_config(physical_device, cs);
188
189 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
190 if (!has_clear_state)
191 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
192
193 /* FIXME calculate these values somehow ??? */
194 if (physical_device->rad_info.chip_class <= GFX8) {
195 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
196 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
197 }
198
199 if (!has_clear_state) {
200 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
201 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
202 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
203 }
204
205 if (physical_device->rad_info.chip_class <= GFX9)
206 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
207 if (!has_clear_state)
208 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
209 if (physical_device->rad_info.chip_class < GFX7)
210 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
211 S_008A14_CLIP_VTX_REORDER_ENA(1));
212
213 if (!has_clear_state)
214 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
215
216 /* CLEAR_STATE doesn't clear these correctly on certain generations.
217 * I don't know why. Deduced by trial and error.
218 */
219 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) {
220 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
221 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
222 S_028204_WINDOW_OFFSET_DISABLE(1));
223 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
224 S_028240_WINDOW_OFFSET_DISABLE(1));
225 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
226 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
227 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
228 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
229 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
230 }
231
232 if (!has_clear_state) {
233 for (i = 0; i < 16; i++) {
234 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
235 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
236 }
237 }
238
239 if (!has_clear_state) {
240 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
241 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
242 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
243 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
244 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
245 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
246 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
247 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
248 }
249
250 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
251 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
252 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
253
254 if (physical_device->rad_info.chip_class >= GFX10) {
255 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
256 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
257 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
258 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
259 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
260 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
261 } else if (physical_device->rad_info.chip_class == GFX9) {
262 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
263 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
264 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
265 } else {
266 /* These registers, when written, also overwrite the
267 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
268 * them. It would be an issue if there was another UMD
269 * changing them.
270 */
271 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
272 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
273 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
274 }
275
276 if (physical_device->rad_info.chip_class >= GFX7) {
277 if (physical_device->rad_info.chip_class >= GFX10) {
278 /* Logical CUs 16 - 31 */
279 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
280 3, S_00B404_CU_EN(0xffff));
281 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
282 3, S_00B104_CU_EN(0xffff));
283 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
284 3, S_00B004_CU_EN(0xffff));
285 }
286
287 if (physical_device->rad_info.chip_class >= GFX9) {
288 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
289 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
290 } else {
291 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
292 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
293 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
294 S_00B41C_WAVE_LIMIT(0x3F));
295 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
296 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
297 /* If this is 0, Bonaire can hang even if GS isn't being used.
298 * Other chips are unaffected. These are suboptimal values,
299 * but we don't use on-chip GS.
300 */
301 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
302 S_028A44_ES_VERTS_PER_SUBGRP(64) |
303 S_028A44_GS_PRIMS_PER_SUBGRP(4));
304 }
305
306 /* Compute LATE_ALLOC_VS.LIMIT. */
307 unsigned num_cu_per_sh = physical_device->rad_info.min_good_cu_per_sa;
308 unsigned late_alloc_wave64 = 0; /* The limit is per SA. */
309 unsigned late_alloc_wave64_gs = 0;
310 unsigned cu_mask_vs = 0xffff;
311 unsigned cu_mask_gs = 0xffff;
312
313 if (physical_device->rad_info.chip_class >= GFX10) {
314 /* For Wave32, the hw will launch twice the number of late
315 * alloc waves, so 1 == 2x wave32.
316 */
317 if (!physical_device->rad_info.use_late_alloc) {
318 late_alloc_wave64 = 0;
319 } else if (num_cu_per_sh <= 6) {
320 late_alloc_wave64 = num_cu_per_sh - 2;
321 } else {
322 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
323
324 /* CU2 & CU3 disabled because of the dual CU design */
325 cu_mask_vs = 0xfff3;
326 cu_mask_gs = 0xfff3; /* NGG only */
327 }
328
329 late_alloc_wave64_gs = late_alloc_wave64;
330
331 /* Don't use late alloc for NGG on Navi14 due to a hw
332 * bug. If NGG is never used, enable all CUs.
333 */
334 if (!physical_device->use_ngg ||
335 physical_device->rad_info.family == CHIP_NAVI14) {
336 late_alloc_wave64_gs = 0;
337 cu_mask_gs = 0xffff;
338 }
339 } else {
340 if (!physical_device->rad_info.use_late_alloc) {
341 late_alloc_wave64 = 0;
342 } else if (num_cu_per_sh <= 4) {
343 /* Too few available compute units per SA.
344 * Disallowing VS to run on one CU could hurt
345 * us more than late VS allocation would help.
346 *
347 * 2 is the highest safe number that allows us
348 * to keep all CUs enabled.
349 */
350 late_alloc_wave64 = 2;
351 } else {
352 /* This is a good initial value, allowing 1
353 * late_alloc wave per SIMD on num_cu - 2.
354 */
355 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
356 }
357
358 if (late_alloc_wave64 > 2)
359 cu_mask_vs = 0xfffe; /* 1 CU disabled */
360 }
361
362 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
363 3, S_00B118_CU_EN(cu_mask_vs) |
364 S_00B118_WAVE_LIMIT(0x3F));
365 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
366 S_00B11C_LIMIT(late_alloc_wave64));
367
368 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
369 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
370
371 if (physical_device->rad_info.chip_class >= GFX10) {
372 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
373 3, S_00B204_CU_EN(0xffff) |
374 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64_gs));
375 }
376
377 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
378 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
379 }
380
381 if (physical_device->rad_info.chip_class >= GFX10) {
382 /* Break up a pixel wave if it contains deallocs for more than
383 * half the parameter cache.
384 *
385 * To avoid a deadlock where pixel waves aren't launched
386 * because they're waiting for more pixels while the frontend
387 * is stuck waiting for PC space, the maximum allowed value is
388 * the size of the PC minus the largest possible allocation for
389 * a single primitive shader subgroup.
390 */
391 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
392 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
393 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
394
395 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
396 unsigned meta_write_policy, meta_read_policy;
397
398 /* TODO: investigate whether LRU improves performance on other chips too */
399 if (physical_device->rad_info.num_render_backends <= 4) {
400 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
401 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
402 } else {
403 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
404 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
405 }
406
407 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
408 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
409 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
410 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
411 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
412 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
413 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
414 S_02807C_HTILE_RD_POLICY(meta_read_policy));
415
416 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
417 S_028410_CMASK_WR_POLICY(meta_write_policy) |
418 S_028410_FMASK_WR_POLICY(meta_write_policy) |
419 S_028410_DCC_WR_POLICY(meta_write_policy) |
420 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
421 S_028410_CMASK_RD_POLICY(meta_read_policy) |
422 S_028410_FMASK_RD_POLICY(meta_read_policy) |
423 S_028410_DCC_RD_POLICY(meta_read_policy) |
424 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
425 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
426
427 radeon_set_sh_reg(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 0);
428 radeon_set_sh_reg(cs, R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1, 0);
429 radeon_set_sh_reg(cs, R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2, 0);
430 radeon_set_sh_reg(cs, R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3, 0);
431 radeon_set_sh_reg(cs, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 0);
432 radeon_set_sh_reg(cs, R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1, 0);
433 radeon_set_sh_reg(cs, R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2, 0);
434 radeon_set_sh_reg(cs, R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3, 0);
435 radeon_set_sh_reg(cs, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 0);
436 radeon_set_sh_reg(cs, R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1, 0);
437 radeon_set_sh_reg(cs, R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2, 0);
438 radeon_set_sh_reg(cs, R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3, 0);
439 radeon_set_sh_reg(cs, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 0);
440 radeon_set_sh_reg(cs, R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1, 0);
441 radeon_set_sh_reg(cs, R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2, 0);
442 radeon_set_sh_reg(cs, R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3, 0);
443
444 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
445 S_00B0C0_SOFT_GROUPING_EN(1) |
446 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
447 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
448
449 if (physical_device->rad_info.chip_class >= GFX10_3) {
450 radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103, 0xff);
451 radeon_set_context_reg(cs, 0x28848, 1 << 9); /* This fixes sample shading. */
452 }
453
454 if (physical_device->rad_info.chip_class == GFX10) {
455 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
456 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
457 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
458 }
459
460 /* TODO: For culling, replace 128 with 256. */
461 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
462 S_030980_OVERSUB_EN(physical_device->rad_info.use_late_alloc) |
463 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
464 }
465
466 if (physical_device->rad_info.chip_class >= GFX9) {
467 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
468 S_028B50_ACCUM_ISOLINE(40) |
469 S_028B50_ACCUM_TRI(30) |
470 S_028B50_ACCUM_QUAD(24) |
471 S_028B50_DONUT_SPLIT(24) |
472 S_028B50_TRAP_SPLIT(6));
473 } else if (physical_device->rad_info.chip_class >= GFX8) {
474 uint32_t vgt_tess_distribution;
475
476 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
477 S_028B50_ACCUM_TRI(11) |
478 S_028B50_ACCUM_QUAD(11) |
479 S_028B50_DONUT_SPLIT(16);
480
481 if (physical_device->rad_info.family == CHIP_FIJI ||
482 physical_device->rad_info.family >= CHIP_POLARIS10)
483 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
484
485 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
486 vgt_tess_distribution);
487 } else if (!has_clear_state) {
488 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
489 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
490 }
491
492 if (device->border_color_data.bo) {
493 uint64_t border_color_va = radv_buffer_get_va(device->border_color_data.bo);
494
495 radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
496 if (physical_device->rad_info.chip_class >= GFX7) {
497 radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI,
498 S_028084_ADDRESS(border_color_va >> 40));
499 }
500 }
501
502 if (physical_device->rad_info.chip_class >= GFX9) {
503 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
504 S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
505 S_028C48_MAX_PRIM_PER_BATCH(1023));
506 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
507 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
508 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
509 }
510
511 unsigned tmp = (unsigned)(1.0 * 8.0);
512 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
513 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
514 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
515 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
516 S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875/2)));
517
518 if (!has_clear_state) {
519 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
520 S_028004_ZPASS_INCREMENT_DISABLE(1));
521 }
522
523 /* Enable the Polaris small primitive filter control.
524 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
525 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
526 * and AMDVLK doesn't have a workaround as well.
527 */
528 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
529 unsigned small_prim_filter_cntl =
530 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
531 /* Workaround for a hw line bug. */
532 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
533
534 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
535 small_prim_filter_cntl);
536 }
537
538 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
539 S_0286D4_FLAT_SHADE_ENA(1) |
540 S_0286D4_PNT_SPRITE_ENA(1) |
541 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
542 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
543 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
544 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
545 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
546
547 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
548 S_028BE4_PIX_CENTER(1) |
549 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
550 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
551
552 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
553 S_028818_VTX_W0_FMT(1) |
554 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
555 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
556 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
557
558 si_emit_compute(physical_device, cs);
559 }
560
561 void
562 cik_create_gfx_config(struct radv_device *device)
563 {
564 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
565 if (!cs)
566 return;
567
568 si_emit_graphics(device, cs);
569
570 while (cs->cdw & 7) {
571 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
572 radeon_emit(cs, PKT2_NOP_PAD);
573 else
574 radeon_emit(cs, PKT3_NOP_PAD);
575 }
576
577 device->gfx_init = device->ws->buffer_create(device->ws,
578 cs->cdw * 4, 4096,
579 RADEON_DOMAIN_GTT,
580 RADEON_FLAG_CPU_ACCESS|
581 RADEON_FLAG_NO_INTERPROCESS_SHARING |
582 RADEON_FLAG_READ_ONLY |
583 RADEON_FLAG_GTT_WC,
584 RADV_BO_PRIORITY_CS);
585 if (!device->gfx_init)
586 goto fail;
587
588 void *map = device->ws->buffer_map(device->gfx_init);
589 if (!map) {
590 device->ws->buffer_destroy(device->gfx_init);
591 device->gfx_init = NULL;
592 goto fail;
593 }
594 memcpy(map, cs->buf, cs->cdw * 4);
595
596 device->ws->buffer_unmap(device->gfx_init);
597 device->gfx_init_size_dw = cs->cdw;
598 fail:
599 device->ws->cs_destroy(cs);
600 }
601
602 static void
603 get_viewport_xform(const VkViewport *viewport,
604 float scale[3], float translate[3])
605 {
606 float x = viewport->x;
607 float y = viewport->y;
608 float half_width = 0.5f * viewport->width;
609 float half_height = 0.5f * viewport->height;
610 double n = viewport->minDepth;
611 double f = viewport->maxDepth;
612
613 scale[0] = half_width;
614 translate[0] = half_width + x;
615 scale[1] = half_height;
616 translate[1] = half_height + y;
617
618 scale[2] = (f - n);
619 translate[2] = n;
620 }
621
622 void
623 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
624 int count, const VkViewport *viewports)
625 {
626 int i;
627
628 assert(count);
629 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
630 first_vp * 4 * 6, count * 6);
631
632 for (i = 0; i < count; i++) {
633 float scale[3], translate[3];
634
635
636 get_viewport_xform(&viewports[i], scale, translate);
637 radeon_emit(cs, fui(scale[0]));
638 radeon_emit(cs, fui(translate[0]));
639 radeon_emit(cs, fui(scale[1]));
640 radeon_emit(cs, fui(translate[1]));
641 radeon_emit(cs, fui(scale[2]));
642 radeon_emit(cs, fui(translate[2]));
643 }
644
645 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
646 first_vp * 4 * 2, count * 2);
647 for (i = 0; i < count; i++) {
648 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
649 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
650 radeon_emit(cs, fui(zmin));
651 radeon_emit(cs, fui(zmax));
652 }
653 }
654
655 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
656 {
657 float scale[3], translate[3];
658 VkRect2D rect;
659
660 get_viewport_xform(viewport, scale, translate);
661
662 rect.offset.x = translate[0] - fabsf(scale[0]);
663 rect.offset.y = translate[1] - fabsf(scale[1]);
664 rect.extent.width = ceilf(translate[0] + fabsf(scale[0])) - rect.offset.x;
665 rect.extent.height = ceilf(translate[1] + fabsf(scale[1])) - rect.offset.y;
666
667 return rect;
668 }
669
670 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
671 VkRect2D ret;
672 ret.offset.x = MAX2(a->offset.x, b->offset.x);
673 ret.offset.y = MAX2(a->offset.y, b->offset.y);
674 ret.extent.width = MIN2(a->offset.x + a->extent.width,
675 b->offset.x + b->extent.width) - ret.offset.x;
676 ret.extent.height = MIN2(a->offset.y + a->extent.height,
677 b->offset.y + b->extent.height) - ret.offset.y;
678 return ret;
679 }
680
681 void
682 si_write_scissors(struct radeon_cmdbuf *cs, int first,
683 int count, const VkRect2D *scissors,
684 const VkViewport *viewports, bool can_use_guardband)
685 {
686 int i;
687 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
688 const float max_range = 32767.0f;
689 if (!count)
690 return;
691
692 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
693 for (i = 0; i < count; i++) {
694 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
695 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
696
697 get_viewport_xform(viewports + i, scale, translate);
698 scale[0] = fabsf(scale[0]);
699 scale[1] = fabsf(scale[1]);
700
701 if (scale[0] < 0.5)
702 scale[0] = 0.5;
703 if (scale[1] < 0.5)
704 scale[1] = 0.5;
705
706 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
707 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
708
709 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
710 S_028250_TL_Y(scissor.offset.y) |
711 S_028250_WINDOW_OFFSET_DISABLE(1));
712 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
713 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
714 }
715 if (!can_use_guardband) {
716 guardband_x = 1.0;
717 guardband_y = 1.0;
718 }
719
720 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
721 radeon_emit(cs, fui(guardband_y));
722 radeon_emit(cs, fui(1.0));
723 radeon_emit(cs, fui(guardband_x));
724 radeon_emit(cs, fui(1.0));
725 }
726
727 static inline unsigned
728 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
729 {
730 if (num == 0)
731 return 0;
732
733 if (info->incr == 0)
734 return 0;
735
736 if (num < info->min)
737 return 0;
738
739 return 1 + ((num - info->min) / info->incr);
740 }
741
742 static const struct radv_prim_vertex_count prim_size_table[] = {
743 [V_008958_DI_PT_NONE] = {0, 0},
744 [V_008958_DI_PT_POINTLIST] = {1, 1},
745 [V_008958_DI_PT_LINELIST] = {2, 2},
746 [V_008958_DI_PT_LINESTRIP] = {2, 1},
747 [V_008958_DI_PT_TRILIST] = {3, 3},
748 [V_008958_DI_PT_TRIFAN] = {3, 1},
749 [V_008958_DI_PT_TRISTRIP] = {3, 1},
750 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
751 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
752 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
753 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
754 [V_008958_DI_PT_RECTLIST] = {3, 3},
755 [V_008958_DI_PT_LINELOOP] = {2, 1},
756 [V_008958_DI_PT_POLYGON] = {3, 1},
757 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
758 };
759
760 uint32_t
761 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
762 bool instanced_draw, bool indirect_draw,
763 bool count_from_stream_output,
764 uint32_t draw_vertex_count,
765 unsigned topology)
766 {
767 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
768 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
769 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
770 const unsigned max_primgroup_in_wave = 2;
771 /* SWITCH_ON_EOP(0) is always preferable. */
772 bool wd_switch_on_eop = false;
773 bool ia_switch_on_eop = false;
774 bool ia_switch_on_eoi = false;
775 bool partial_vs_wave = false;
776 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
777 bool multi_instances_smaller_than_primgroup;
778 struct radv_prim_vertex_count prim_vertex_count = prim_size_table[topology];
779
780 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline)) {
781 if (topology == V_008958_DI_PT_PATCH) {
782 prim_vertex_count.min = cmd_buffer->state.pipeline->graphics.tess_patch_control_points;
783 prim_vertex_count.incr = 1;
784 }
785 }
786
787 multi_instances_smaller_than_primgroup = indirect_draw;
788 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
789 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
790 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
791 multi_instances_smaller_than_primgroup = true;
792 }
793
794 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
795 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
796
797 if (chip_class >= GFX7) {
798 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
799 * 4 shader engines. Set 1 to pass the assertion below.
800 * The other cases are hardware requirements. */
801 if (cmd_buffer->device->physical_device->rad_info.max_se < 4 ||
802 topology == V_008958_DI_PT_POLYGON ||
803 topology == V_008958_DI_PT_LINELOOP ||
804 topology == V_008958_DI_PT_TRIFAN ||
805 topology == V_008958_DI_PT_TRISTRIP_ADJ ||
806 (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
807 (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
808 (topology != V_008958_DI_PT_POINTLIST &&
809 topology != V_008958_DI_PT_LINESTRIP))))
810 wd_switch_on_eop = true;
811
812 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
813 * We don't know that for indirect drawing, so treat it as
814 * always problematic. */
815 if (family == CHIP_HAWAII &&
816 (instanced_draw || indirect_draw))
817 wd_switch_on_eop = true;
818
819 /* Performance recommendation for 4 SE Gfx7-8 parts if
820 * instances are smaller than a primgroup.
821 * Assume indirect draws always use small instances.
822 * This is needed for good VS wave utilization.
823 */
824 if (chip_class <= GFX8 &&
825 info->max_se == 4 &&
826 multi_instances_smaller_than_primgroup)
827 wd_switch_on_eop = true;
828
829 /* Required on GFX7 and later. */
830 if (info->max_se > 2 && !wd_switch_on_eop)
831 ia_switch_on_eoi = true;
832
833 /* Required by Hawaii and, for some special cases, by GFX8. */
834 if (ia_switch_on_eoi &&
835 (family == CHIP_HAWAII ||
836 (chip_class == GFX8 &&
837 /* max primgroup in wave is always 2 - leave this for documentation */
838 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
839 partial_vs_wave = true;
840
841 /* Instancing bug on Bonaire. */
842 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
843 (instanced_draw || indirect_draw))
844 partial_vs_wave = true;
845
846 /* Hardware requirement when drawing primitives from a stream
847 * output buffer.
848 */
849 if (count_from_stream_output)
850 wd_switch_on_eop = true;
851
852 /* If the WD switch is false, the IA switch must be false too. */
853 assert(wd_switch_on_eop || !ia_switch_on_eop);
854 }
855 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
856 if (chip_class <= GFX8 && ia_switch_on_eoi)
857 partial_es_wave = true;
858
859 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
860 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
861 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
862 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
863 */
864 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
865 bool set_vgt_flush = indirect_draw;
866 if (!set_vgt_flush && instanced_draw) {
867 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
868 if (num_prims <= 1)
869 set_vgt_flush = true;
870 }
871 if (set_vgt_flush)
872 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
873 }
874 }
875
876 /* Workaround for a VGT hang when strip primitive types are used with
877 * primitive restart.
878 */
879 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
880 (topology == V_008958_DI_PT_LINESTRIP ||
881 topology == V_008958_DI_PT_TRISTRIP ||
882 topology == V_008958_DI_PT_LINESTRIP_ADJ ||
883 topology == V_008958_DI_PT_TRISTRIP_ADJ)) {
884 partial_vs_wave = true;
885 }
886
887 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
888 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
889 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
890 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
891 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
892 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
893
894 }
895
896 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
897 enum chip_class chip_class,
898 bool is_mec,
899 unsigned event, unsigned event_flags,
900 unsigned dst_sel, unsigned data_sel,
901 uint64_t va,
902 uint32_t new_fence,
903 uint64_t gfx9_eop_bug_va)
904 {
905 unsigned op = EVENT_TYPE(event) |
906 EVENT_INDEX(event == V_028A90_CS_DONE ||
907 event == V_028A90_PS_DONE ? 6 : 5) |
908 event_flags;
909 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
910 unsigned sel = EOP_DST_SEL(dst_sel) |
911 EOP_DATA_SEL(data_sel);
912
913 /* Wait for write confirmation before writing data, but don't send
914 * an interrupt. */
915 if (data_sel != EOP_DATA_SEL_DISCARD)
916 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
917
918 if (chip_class >= GFX9 || is_gfx8_mec) {
919 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
920 * counters) must immediately precede every timestamp event to
921 * prevent a GPU hang on GFX9.
922 */
923 if (chip_class == GFX9 && !is_mec) {
924 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
925 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
926 radeon_emit(cs, gfx9_eop_bug_va);
927 radeon_emit(cs, gfx9_eop_bug_va >> 32);
928 }
929
930 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
931 radeon_emit(cs, op);
932 radeon_emit(cs, sel);
933 radeon_emit(cs, va); /* address lo */
934 radeon_emit(cs, va >> 32); /* address hi */
935 radeon_emit(cs, new_fence); /* immediate data lo */
936 radeon_emit(cs, 0); /* immediate data hi */
937 if (!is_gfx8_mec)
938 radeon_emit(cs, 0); /* unused */
939 } else {
940 if (chip_class == GFX7 ||
941 chip_class == GFX8) {
942 /* Two EOP events are required to make all engines go idle
943 * (and optional cache flushes executed) before the timestamp
944 * is written.
945 */
946 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
947 radeon_emit(cs, op);
948 radeon_emit(cs, va);
949 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
950 radeon_emit(cs, 0); /* immediate data */
951 radeon_emit(cs, 0); /* unused */
952 }
953
954 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
955 radeon_emit(cs, op);
956 radeon_emit(cs, va);
957 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
958 radeon_emit(cs, new_fence); /* immediate data */
959 radeon_emit(cs, 0); /* unused */
960 }
961 }
962
963 void
964 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
965 uint32_t ref, uint32_t mask)
966 {
967 assert(op == WAIT_REG_MEM_EQUAL ||
968 op == WAIT_REG_MEM_NOT_EQUAL ||
969 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
970
971 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
972 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
973 radeon_emit(cs, va);
974 radeon_emit(cs, va >> 32);
975 radeon_emit(cs, ref); /* reference value */
976 radeon_emit(cs, mask); /* mask */
977 radeon_emit(cs, 4); /* poll interval */
978 }
979
980 static void
981 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
982 bool is_mec,
983 bool is_gfx9,
984 unsigned cp_coher_cntl)
985 {
986 if (is_mec || is_gfx9) {
987 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
988 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
989 PKT3_SHADER_TYPE_S(is_mec));
990 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
991 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
992 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
993 radeon_emit(cs, 0); /* CP_COHER_BASE */
994 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
995 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
996 } else {
997 /* ACQUIRE_MEM is only required on a compute ring. */
998 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
999 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1000 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1001 radeon_emit(cs, 0); /* CP_COHER_BASE */
1002 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1003 }
1004 }
1005
1006 static void
1007 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1008 enum chip_class chip_class,
1009 uint32_t *flush_cnt,
1010 uint64_t flush_va,
1011 bool is_mec,
1012 enum radv_cmd_flush_bits flush_bits,
1013 uint64_t gfx9_eop_bug_va)
1014 {
1015 uint32_t gcr_cntl = 0;
1016 unsigned cb_db_event = 0;
1017
1018 /* We don't need these. */
1019 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
1020
1021 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1022 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1023 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
1024 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1025 * to FORWARD when both L1 and L2 are written out (WB or INV).
1026 */
1027 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1028 }
1029 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
1030 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1031 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1032 /* Writeback and invalidate everything in L2. */
1033 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
1034 S_586_GLM_INV(1) | S_586_GLM_WB(1);
1035 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
1036 /* Writeback but do not invalidate.
1037 * GLM doesn't support WB alone. If WB is set, INV must be set too.
1038 */
1039 gcr_cntl |= S_586_GL2_WB(1) |
1040 S_586_GLM_WB(1) | S_586_GLM_INV(1);
1041 }
1042
1043 /* TODO: Implement this new flag for GFX9+.
1044 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
1045 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
1046 */
1047
1048 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1049 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
1050 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1051 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1052 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1053 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1054 EVENT_INDEX(0));
1055 }
1056
1057 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
1058 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1059 /* Flush HTILE. Will wait for idle later. */
1060 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1061 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1062 EVENT_INDEX(0));
1063 }
1064
1065 /* First flush CB/DB, then L1/L2. */
1066 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1067
1068 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
1069 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1070 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1071 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1072 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1073 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1074 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1075 } else {
1076 assert(0);
1077 }
1078 } else {
1079 /* Wait for graphics shaders to go idle if requested. */
1080 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1081 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1082 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1083 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1084 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1085 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1086 }
1087 }
1088
1089 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1090 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1091 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1092 }
1093
1094 if (cb_db_event) {
1095 /* CB/DB flush and invalidate (or possibly just a wait for a
1096 * meta flush) via RELEASE_MEM.
1097 *
1098 * Combine this with other cache flushes when possible; this
1099 * requires affected shaders to be idle, so do it after the
1100 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1101 * implied).
1102 */
1103 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1104 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1105 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1106 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1107 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1108 assert(G_586_GL2_US(gcr_cntl) == 0);
1109 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1110 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1111 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1112 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1113 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1114
1115 gcr_cntl &= C_586_GLM_WB &
1116 C_586_GLM_INV &
1117 C_586_GLV_INV &
1118 C_586_GL1_INV &
1119 C_586_GL2_INV &
1120 C_586_GL2_WB; /* keep SEQ */
1121
1122 assert(flush_cnt);
1123 (*flush_cnt)++;
1124
1125 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
1126 S_490_GLM_WB(glm_wb) |
1127 S_490_GLM_INV(glm_inv) |
1128 S_490_GLV_INV(glv_inv) |
1129 S_490_GL1_INV(gl1_inv) |
1130 S_490_GL2_INV(gl2_inv) |
1131 S_490_GL2_WB(gl2_wb) |
1132 S_490_SEQ(gcr_seq),
1133 EOP_DST_SEL_MEM,
1134 EOP_DATA_SEL_VALUE_32BIT,
1135 flush_va, *flush_cnt,
1136 gfx9_eop_bug_va);
1137
1138 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1139 *flush_cnt, 0xffffffff);
1140 }
1141
1142 /* VGT state sync */
1143 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1144 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1145 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1146 }
1147
1148 /* Ignore fields that only modify the behavior of other fields. */
1149 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1150 /* Flush caches and wait for the caches to assert idle.
1151 * The cache flush is executed in the ME, but the PFP waits
1152 * for completion.
1153 */
1154 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1155 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1156 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1157 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1158 radeon_emit(cs, 0); /* CP_COHER_BASE */
1159 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1160 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1161 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1162 } else if ((cb_db_event ||
1163 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1164 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1165 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1166 && !is_mec) {
1167 /* We need to ensure that PFP waits as well. */
1168 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1169 radeon_emit(cs, 0);
1170 }
1171
1172 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1173 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1174 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1175 EVENT_INDEX(0));
1176 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1177 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1178 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1179 EVENT_INDEX(0));
1180 }
1181 }
1182
1183 void
1184 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1185 enum chip_class chip_class,
1186 uint32_t *flush_cnt,
1187 uint64_t flush_va,
1188 bool is_mec,
1189 enum radv_cmd_flush_bits flush_bits,
1190 uint64_t gfx9_eop_bug_va)
1191 {
1192 unsigned cp_coher_cntl = 0;
1193 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1194 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1195
1196 if (chip_class >= GFX10) {
1197 /* GFX10 cache flush handling is quite different. */
1198 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1199 is_mec, flush_bits, gfx9_eop_bug_va);
1200 return;
1201 }
1202
1203 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1204 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1205 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1206 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1207
1208 if (chip_class <= GFX8) {
1209 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1210 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1211 S_0085F0_CB0_DEST_BASE_ENA(1) |
1212 S_0085F0_CB1_DEST_BASE_ENA(1) |
1213 S_0085F0_CB2_DEST_BASE_ENA(1) |
1214 S_0085F0_CB3_DEST_BASE_ENA(1) |
1215 S_0085F0_CB4_DEST_BASE_ENA(1) |
1216 S_0085F0_CB5_DEST_BASE_ENA(1) |
1217 S_0085F0_CB6_DEST_BASE_ENA(1) |
1218 S_0085F0_CB7_DEST_BASE_ENA(1);
1219
1220 /* Necessary for DCC */
1221 if (chip_class >= GFX8) {
1222 si_cs_emit_write_event_eop(cs,
1223 chip_class,
1224 is_mec,
1225 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1226 0,
1227 EOP_DST_SEL_MEM,
1228 EOP_DATA_SEL_DISCARD,
1229 0, 0,
1230 gfx9_eop_bug_va);
1231 }
1232 }
1233 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1234 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1235 S_0085F0_DB_DEST_BASE_ENA(1);
1236 }
1237 }
1238
1239 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1240 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1241 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1242 }
1243
1244 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1245 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1246 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1247 }
1248
1249 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1250 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1251 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1252 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1253 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1254 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1255 }
1256
1257 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1258 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1259 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1260 }
1261
1262 if (chip_class == GFX9 && flush_cb_db) {
1263 unsigned cb_db_event, tc_flags;
1264
1265 /* Set the CB/DB flush event. */
1266 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1267
1268 /* These are the only allowed combinations. If you need to
1269 * do multiple operations at once, do them separately.
1270 * All operations that invalidate L2 also seem to invalidate
1271 * metadata. Volatile (VOL) and WC flushes are not listed here.
1272 *
1273 * TC | TC_WB = writeback & invalidate L2 & L1
1274 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1275 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1276 * TC | TC_NC = invalidate L2 for MTYPE == NC
1277 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1278 * TCL1 = invalidate L1
1279 */
1280 tc_flags = EVENT_TC_ACTION_ENA |
1281 EVENT_TC_MD_ACTION_ENA;
1282
1283 /* Ideally flush TC together with CB/DB. */
1284 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1285 /* Writeback and invalidate everything in L2 & L1. */
1286 tc_flags = EVENT_TC_ACTION_ENA |
1287 EVENT_TC_WB_ACTION_ENA;
1288
1289
1290 /* Clear the flags. */
1291 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1292 RADV_CMD_FLAG_WB_L2 |
1293 RADV_CMD_FLAG_INV_VCACHE);
1294 }
1295 assert(flush_cnt);
1296 (*flush_cnt)++;
1297
1298 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1299 EOP_DST_SEL_MEM,
1300 EOP_DATA_SEL_VALUE_32BIT,
1301 flush_va, *flush_cnt,
1302 gfx9_eop_bug_va);
1303 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1304 *flush_cnt, 0xffffffff);
1305 }
1306
1307 /* VGT state sync */
1308 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1309 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1310 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1311 }
1312
1313 /* VGT streamout state sync */
1314 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1315 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1316 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1317 }
1318
1319 /* Make sure ME is idle (it executes most packets) before continuing.
1320 * This prevents read-after-write hazards between PFP and ME.
1321 */
1322 if ((cp_coher_cntl ||
1323 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1324 RADV_CMD_FLAG_INV_VCACHE |
1325 RADV_CMD_FLAG_INV_L2 |
1326 RADV_CMD_FLAG_WB_L2))) &&
1327 !is_mec) {
1328 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1329 radeon_emit(cs, 0);
1330 }
1331
1332 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1333 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1334 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1335 cp_coher_cntl |
1336 S_0085F0_TC_ACTION_ENA(1) |
1337 S_0085F0_TCL1_ACTION_ENA(1) |
1338 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1339 cp_coher_cntl = 0;
1340 } else {
1341 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1342 /* WB = write-back
1343 * NC = apply to non-coherent MTYPEs
1344 * (i.e. MTYPE <= 1, which is what we use everywhere)
1345 *
1346 * WB doesn't work without NC.
1347 */
1348 si_emit_acquire_mem(cs, is_mec,
1349 chip_class == GFX9,
1350 cp_coher_cntl |
1351 S_0301F0_TC_WB_ACTION_ENA(1) |
1352 S_0301F0_TC_NC_ACTION_ENA(1));
1353 cp_coher_cntl = 0;
1354 }
1355 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1356 si_emit_acquire_mem(cs, is_mec,
1357 chip_class == GFX9,
1358 cp_coher_cntl |
1359 S_0085F0_TCL1_ACTION_ENA(1));
1360 cp_coher_cntl = 0;
1361 }
1362 }
1363
1364 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1365 * Therefore, it should be last. Done in PFP.
1366 */
1367 if (cp_coher_cntl)
1368 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1369
1370 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1371 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1372 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1373 EVENT_INDEX(0));
1374 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1375 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1376 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1377 EVENT_INDEX(0));
1378 }
1379 }
1380
1381 void
1382 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1383 {
1384 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1385
1386 if (is_compute)
1387 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1388 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1389 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1390 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1391 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1392 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1393 RADV_CMD_FLAG_VGT_FLUSH |
1394 RADV_CMD_FLAG_START_PIPELINE_STATS |
1395 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1396
1397 if (!cmd_buffer->state.flush_bits)
1398 return;
1399
1400 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1401
1402 si_cs_emit_cache_flush(cmd_buffer->cs,
1403 cmd_buffer->device->physical_device->rad_info.chip_class,
1404 &cmd_buffer->gfx9_fence_idx,
1405 cmd_buffer->gfx9_fence_va,
1406 radv_cmd_buffer_uses_mec(cmd_buffer),
1407 cmd_buffer->state.flush_bits,
1408 cmd_buffer->gfx9_eop_bug_va);
1409
1410
1411 if (unlikely(cmd_buffer->device->trace_bo))
1412 radv_cmd_buffer_trace_emit(cmd_buffer);
1413
1414 /* Clear the caches that have been flushed to avoid syncing too much
1415 * when there is some pending active queries.
1416 */
1417 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1418
1419 cmd_buffer->state.flush_bits = 0;
1420
1421 /* If the driver used a compute shader for resetting a query pool, it
1422 * should be finished at this point.
1423 */
1424 cmd_buffer->pending_reset_query = false;
1425 }
1426
1427 /* sets the CP predication state using a boolean stored at va */
1428 void
1429 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1430 bool draw_visible, uint64_t va)
1431 {
1432 uint32_t op = 0;
1433
1434 if (va) {
1435 op = PRED_OP(PREDICATION_OP_BOOL64);
1436
1437 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1438 * zero, all rendering commands are discarded. Otherwise, they
1439 * are discarded if the value is non zero.
1440 */
1441 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1442 PREDICATION_DRAW_NOT_VISIBLE;
1443 }
1444 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1445 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1446 radeon_emit(cmd_buffer->cs, op);
1447 radeon_emit(cmd_buffer->cs, va);
1448 radeon_emit(cmd_buffer->cs, va >> 32);
1449 } else {
1450 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1451 radeon_emit(cmd_buffer->cs, va);
1452 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1453 }
1454 }
1455
1456 /* Set this if you want the 3D engine to wait until CP DMA is done.
1457 * It should be set on the last CP DMA packet. */
1458 #define CP_DMA_SYNC (1 << 0)
1459
1460 /* Set this if the source data was used as a destination in a previous CP DMA
1461 * packet. It's for preventing a read-after-write (RAW) hazard between two
1462 * CP DMA packets. */
1463 #define CP_DMA_RAW_WAIT (1 << 1)
1464 #define CP_DMA_USE_L2 (1 << 2)
1465 #define CP_DMA_CLEAR (1 << 3)
1466
1467 /* Alignment for optimal performance. */
1468 #define SI_CPDMA_ALIGNMENT 32
1469
1470 /* The max number of bytes that can be copied per packet. */
1471 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1472 {
1473 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1474 S_414_BYTE_COUNT_GFX9(~0u) :
1475 S_414_BYTE_COUNT_GFX6(~0u);
1476
1477 /* make it aligned for optimal performance */
1478 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1479 }
1480
1481 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1482 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1483 * clear value.
1484 */
1485 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1486 uint64_t dst_va, uint64_t src_va,
1487 unsigned size, unsigned flags)
1488 {
1489 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1490 uint32_t header = 0, command = 0;
1491
1492 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1493
1494 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1495 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1496 command |= S_414_BYTE_COUNT_GFX9(size);
1497 else
1498 command |= S_414_BYTE_COUNT_GFX6(size);
1499
1500 /* Sync flags. */
1501 if (flags & CP_DMA_SYNC)
1502 header |= S_411_CP_SYNC(1);
1503 else {
1504 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1505 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1506 else
1507 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1508 }
1509
1510 if (flags & CP_DMA_RAW_WAIT)
1511 command |= S_414_RAW_WAIT(1);
1512
1513 /* Src and dst flags. */
1514 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1515 !(flags & CP_DMA_CLEAR) &&
1516 src_va == dst_va)
1517 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1518 else if (flags & CP_DMA_USE_L2)
1519 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1520
1521 if (flags & CP_DMA_CLEAR)
1522 header |= S_411_SRC_SEL(V_411_DATA);
1523 else if (flags & CP_DMA_USE_L2)
1524 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1525
1526 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1527 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1528 radeon_emit(cs, header);
1529 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1530 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1531 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1532 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1533 radeon_emit(cs, command);
1534 } else {
1535 assert(!(flags & CP_DMA_USE_L2));
1536 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1537 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1538 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1539 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1540 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1541 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1542 radeon_emit(cs, command);
1543 }
1544
1545 /* CP DMA is executed in ME, but index buffers are read by PFP.
1546 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1547 * indices. If we wanted to execute CP DMA in PFP, this packet
1548 * should precede it.
1549 */
1550 if (flags & CP_DMA_SYNC) {
1551 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1552 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1553 radeon_emit(cs, 0);
1554 }
1555
1556 /* CP will see the sync flag and wait for all DMAs to complete. */
1557 cmd_buffer->state.dma_is_busy = false;
1558 }
1559
1560 if (unlikely(cmd_buffer->device->trace_bo))
1561 radv_cmd_buffer_trace_emit(cmd_buffer);
1562 }
1563
1564 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1565 unsigned size)
1566 {
1567 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1568 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1569
1570 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1571 aligned_size, CP_DMA_USE_L2);
1572 }
1573
1574 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1575 uint64_t remaining_size, unsigned *flags)
1576 {
1577
1578 /* Flush the caches for the first copy only.
1579 * Also wait for the previous CP DMA operations.
1580 */
1581 if (cmd_buffer->state.flush_bits) {
1582 si_emit_cache_flush(cmd_buffer);
1583 *flags |= CP_DMA_RAW_WAIT;
1584 }
1585
1586 /* Do the synchronization after the last dma, so that all data
1587 * is written to memory.
1588 */
1589 if (byte_count == remaining_size)
1590 *flags |= CP_DMA_SYNC;
1591 }
1592
1593 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1594 {
1595 uint64_t va;
1596 uint32_t offset;
1597 unsigned dma_flags = 0;
1598 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1599 void *ptr;
1600
1601 assert(size < SI_CPDMA_ALIGNMENT);
1602
1603 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1604
1605 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1606 va += offset;
1607
1608 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1609
1610 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1611 dma_flags);
1612 }
1613
1614 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1615 uint64_t src_va, uint64_t dest_va,
1616 uint64_t size)
1617 {
1618 uint64_t main_src_va, main_dest_va;
1619 uint64_t skipped_size = 0, realign_size = 0;
1620
1621 /* Assume that we are not going to sync after the last DMA operation. */
1622 cmd_buffer->state.dma_is_busy = true;
1623
1624 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1625 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1626 /* If the size is not aligned, we must add a dummy copy at the end
1627 * just to align the internal counter. Otherwise, the DMA engine
1628 * would slow down by an order of magnitude for following copies.
1629 */
1630 if (size % SI_CPDMA_ALIGNMENT)
1631 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1632
1633 /* If the copy begins unaligned, we must start copying from the next
1634 * aligned block and the skipped part should be copied after everything
1635 * else has been copied. Only the src alignment matters, not dst.
1636 */
1637 if (src_va % SI_CPDMA_ALIGNMENT) {
1638 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1639 /* The main part will be skipped if the size is too small. */
1640 skipped_size = MIN2(skipped_size, size);
1641 size -= skipped_size;
1642 }
1643 }
1644 main_src_va = src_va + skipped_size;
1645 main_dest_va = dest_va + skipped_size;
1646
1647 while (size) {
1648 unsigned dma_flags = 0;
1649 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1650
1651 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1652 /* DMA operations via L2 are coherent and faster.
1653 * TODO: GFX7-GFX9 should also support this but it
1654 * requires tests/benchmarks.
1655 */
1656 dma_flags |= CP_DMA_USE_L2;
1657 }
1658
1659 si_cp_dma_prepare(cmd_buffer, byte_count,
1660 size + skipped_size + realign_size,
1661 &dma_flags);
1662
1663 dma_flags &= ~CP_DMA_SYNC;
1664
1665 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1666 byte_count, dma_flags);
1667
1668 size -= byte_count;
1669 main_src_va += byte_count;
1670 main_dest_va += byte_count;
1671 }
1672
1673 if (skipped_size) {
1674 unsigned dma_flags = 0;
1675
1676 si_cp_dma_prepare(cmd_buffer, skipped_size,
1677 size + skipped_size + realign_size,
1678 &dma_flags);
1679
1680 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1681 skipped_size, dma_flags);
1682 }
1683 if (realign_size)
1684 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1685 }
1686
1687 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1688 uint64_t size, unsigned value)
1689 {
1690
1691 if (!size)
1692 return;
1693
1694 assert(va % 4 == 0 && size % 4 == 0);
1695
1696 /* Assume that we are not going to sync after the last DMA operation. */
1697 cmd_buffer->state.dma_is_busy = true;
1698
1699 while (size) {
1700 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1701 unsigned dma_flags = CP_DMA_CLEAR;
1702
1703 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1704 /* DMA operations via L2 are coherent and faster.
1705 * TODO: GFX7-GFX9 should also support this but it
1706 * requires tests/benchmarks.
1707 */
1708 dma_flags |= CP_DMA_USE_L2;
1709 }
1710
1711 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1712
1713 /* Emit the clear packet. */
1714 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1715 dma_flags);
1716
1717 size -= byte_count;
1718 va += byte_count;
1719 }
1720 }
1721
1722 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1723 {
1724 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1725 return;
1726
1727 if (!cmd_buffer->state.dma_is_busy)
1728 return;
1729
1730 /* Issue a dummy DMA that copies zero bytes.
1731 *
1732 * The DMA engine will see that there's no work to do and skip this
1733 * DMA request, however, the CP will see the sync flag and still wait
1734 * for all DMAs to complete.
1735 */
1736 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1737
1738 cmd_buffer->state.dma_is_busy = false;
1739 }
1740
1741 /* For MSAA sample positions. */
1742 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1743 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1744 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1745 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1746 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1747
1748 /* For obtaining location coordinates from registers */
1749 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1750 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1751 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1752 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1753
1754 /* 1x MSAA */
1755 static const uint32_t sample_locs_1x =
1756 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1757 static const unsigned max_dist_1x = 0;
1758 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1759
1760 /* 2xMSAA */
1761 static const uint32_t sample_locs_2x =
1762 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1763 static const unsigned max_dist_2x = 4;
1764 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1765
1766 /* 4xMSAA */
1767 static const uint32_t sample_locs_4x =
1768 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1769 static const unsigned max_dist_4x = 6;
1770 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1771
1772 /* 8xMSAA */
1773 static const uint32_t sample_locs_8x[] = {
1774 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1775 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1776 /* The following are unused by hardware, but we emit them to IBs
1777 * instead of multiple SET_CONTEXT_REG packets. */
1778 0,
1779 0,
1780 };
1781 static const unsigned max_dist_8x = 7;
1782 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1783
1784 unsigned radv_get_default_max_sample_dist(int log_samples)
1785 {
1786 unsigned max_dist[] = {
1787 max_dist_1x,
1788 max_dist_2x,
1789 max_dist_4x,
1790 max_dist_8x,
1791 };
1792 return max_dist[log_samples];
1793 }
1794
1795 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1796 {
1797 switch (nr_samples) {
1798 default:
1799 case 1:
1800 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1801 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1802 radeon_emit(cs, centroid_priority_1x >> 32);
1803 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1804 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1805 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1806 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1807 break;
1808 case 2:
1809 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1810 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1811 radeon_emit(cs, centroid_priority_2x >> 32);
1812 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1813 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1814 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1815 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1816 break;
1817 case 4:
1818 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1819 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1820 radeon_emit(cs, centroid_priority_4x >> 32);
1821 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1822 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1823 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1824 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1825 break;
1826 case 8:
1827 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1828 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1829 radeon_emit(cs, centroid_priority_8x >> 32);
1830 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1831 radeon_emit_array(cs, sample_locs_8x, 4);
1832 radeon_emit_array(cs, sample_locs_8x, 4);
1833 radeon_emit_array(cs, sample_locs_8x, 4);
1834 radeon_emit_array(cs, sample_locs_8x, 2);
1835 break;
1836 }
1837 }
1838
1839 static void radv_get_sample_position(struct radv_device *device,
1840 unsigned sample_count,
1841 unsigned sample_index, float *out_value)
1842 {
1843 const uint32_t *sample_locs;
1844
1845 switch (sample_count) {
1846 case 1:
1847 default:
1848 sample_locs = &sample_locs_1x;
1849 break;
1850 case 2:
1851 sample_locs = &sample_locs_2x;
1852 break;
1853 case 4:
1854 sample_locs = &sample_locs_4x;
1855 break;
1856 case 8:
1857 sample_locs = sample_locs_8x;
1858 break;
1859 }
1860
1861 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1862 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1863 }
1864
1865 void radv_device_init_msaa(struct radv_device *device)
1866 {
1867 int i;
1868
1869 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1870
1871 for (i = 0; i < 2; i++)
1872 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1873 for (i = 0; i < 4; i++)
1874 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1875 for (i = 0; i < 8; i++)
1876 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1877 }