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configure.ac: split the wayland client/server confusion
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
151 SE_INDEX(se) | SH_BROADCAST_WRITES |
152 INSTANCE_BROADCAST_WRITES);
153 else
154 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
155 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
158 if (physical_device->rad_info.chip_class >= CIK)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
160 }
161
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device->rad_info.chip_class < CIK)
164 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
165 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
166 INSTANCE_BROADCAST_WRITES);
167 else
168 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
171 }
172
173 static void
174 si_emit_compute(struct radv_physical_device *physical_device,
175 struct radeon_winsys_cs *cs)
176 {
177 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
178 radeon_emit(cs, 0);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181
182 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
183 radeon_emit(cs, 0);
184 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
185 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
186 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
187
188 if (physical_device->rad_info.chip_class >= CIK) {
189 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
190 radeon_set_sh_reg_seq(cs,
191 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
192 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
193 S_00B864_SH1_CU_EN(0xffff));
194 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
195 S_00B868_SH1_CU_EN(0xffff));
196 }
197
198 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
199 * and is now per pipe, so it should be handled in the
200 * kernel if we want to use something other than the default value,
201 * which is now 0x22f.
202 */
203 if (physical_device->rad_info.chip_class <= SI) {
204 /* XXX: This should be:
205 * (number of compute units) * 4 * (waves per simd) - 1 */
206
207 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
208 0x190 /* Default value */);
209 }
210 }
211
212 void
213 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
214 {
215 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
216 si_emit_compute(physical_device, cmd_buffer->cs);
217 }
218
219 static void
220 si_emit_config(struct radv_physical_device *physical_device,
221 struct radeon_winsys_cs *cs)
222 {
223 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
224 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
225 unsigned raster_config, raster_config_1;
226 int i;
227
228 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
229 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
230 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
231
232 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
233 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
234
235 /* FIXME calculate these values somehow ??? */
236 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
237 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
238 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
239
240 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
241 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
242
243 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
244 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
245 if (physical_device->rad_info.chip_class >= GFX9)
246 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, 0);
247 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
248 if (physical_device->rad_info.chip_class < CIK)
249 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
250 S_008A14_CLIP_VTX_REORDER_ENA(1));
251
252 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
253 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
254
255 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
256
257 for (i = 0; i < 16; i++) {
258 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
259 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
260 }
261
262 switch (physical_device->rad_info.family) {
263 case CHIP_TAHITI:
264 case CHIP_PITCAIRN:
265 raster_config = 0x2a00126a;
266 raster_config_1 = 0x00000000;
267 break;
268 case CHIP_VERDE:
269 raster_config = 0x0000124a;
270 raster_config_1 = 0x00000000;
271 break;
272 case CHIP_OLAND:
273 raster_config = 0x00000082;
274 raster_config_1 = 0x00000000;
275 break;
276 case CHIP_HAINAN:
277 raster_config = 0x00000000;
278 raster_config_1 = 0x00000000;
279 break;
280 case CHIP_BONAIRE:
281 raster_config = 0x16000012;
282 raster_config_1 = 0x00000000;
283 break;
284 case CHIP_HAWAII:
285 raster_config = 0x3a00161a;
286 raster_config_1 = 0x0000002e;
287 break;
288 case CHIP_FIJI:
289 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
290 /* old kernels with old tiling config */
291 raster_config = 0x16000012;
292 raster_config_1 = 0x0000002a;
293 } else {
294 raster_config = 0x3a00161a;
295 raster_config_1 = 0x0000002e;
296 }
297 break;
298 case CHIP_POLARIS10:
299 raster_config = 0x16000012;
300 raster_config_1 = 0x0000002a;
301 break;
302 case CHIP_POLARIS11:
303 case CHIP_POLARIS12:
304 raster_config = 0x16000012;
305 raster_config_1 = 0x00000000;
306 break;
307 case CHIP_TONGA:
308 raster_config = 0x16000012;
309 raster_config_1 = 0x0000002a;
310 break;
311 case CHIP_ICELAND:
312 if (num_rb == 1)
313 raster_config = 0x00000000;
314 else
315 raster_config = 0x00000002;
316 raster_config_1 = 0x00000000;
317 break;
318 case CHIP_CARRIZO:
319 raster_config = 0x00000002;
320 raster_config_1 = 0x00000000;
321 break;
322 case CHIP_KAVERI:
323 /* KV should be 0x00000002, but that causes problems with radeon */
324 raster_config = 0x00000000; /* 0x00000002 */
325 raster_config_1 = 0x00000000;
326 break;
327 case CHIP_KABINI:
328 case CHIP_MULLINS:
329 case CHIP_STONEY:
330 raster_config = 0x00000000;
331 raster_config_1 = 0x00000000;
332 break;
333 default:
334 if (physical_device->rad_info.chip_class <= VI) {
335 fprintf(stderr,
336 "radeonsi: Unknown GPU, using 0 for raster_config\n");
337 raster_config = 0x00000000;
338 raster_config_1 = 0x00000000;
339 }
340 break;
341 }
342
343 /* Always use the default config when all backends are enabled
344 * (or when we failed to determine the enabled backends).
345 */
346 if (physical_device->rad_info.chip_class <= VI) {
347 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
348 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
349 raster_config);
350 if (physical_device->rad_info.chip_class >= CIK)
351 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
352 raster_config_1);
353 } else {
354 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
355 }
356 }
357
358 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
359 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
360 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
361 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
362 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
363 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
364 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
365
366 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
367 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
368 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
369 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
370 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
371
372 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
373 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
374 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
375 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
376 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
377 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
378
379 if (physical_device->rad_info.chip_class >= GFX9) {
380 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
381 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
382 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
383 } else {
384 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
385 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
386 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
387 }
388
389 if (physical_device->rad_info.chip_class >= CIK) {
390 if (physical_device->rad_info.chip_class >= GFX9) {
391 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
392 } else {
393 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
394 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
395 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
396 /* If this is 0, Bonaire can hang even if GS isn't being used.
397 * Other chips are unaffected. These are suboptimal values,
398 * but we don't use on-chip GS.
399 */
400 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
401 S_028A44_ES_VERTS_PER_SUBGRP(64) |
402 S_028A44_GS_PRIMS_PER_SUBGRP(4));
403 }
404 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
405
406 if (physical_device->rad_info.num_good_compute_units /
407 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
408 /* Too few available compute units per SH. Disallowing
409 * VS to run on CU0 could hurt us more than late VS
410 * allocation would help.
411 *
412 * LATE_ALLOC_VS = 2 is the highest safe number.
413 */
414 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
415 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
416 } else {
417 /* Set LATE_ALLOC_VS == 31. It should be less than
418 * the number of scratch waves. Limitations:
419 * - VS can't execute on CU0.
420 * - If HS writes outputs to LDS, LS can't execute on CU0.
421 */
422 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
423 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
424 }
425
426 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
427 }
428
429 if (physical_device->rad_info.chip_class >= VI) {
430 uint32_t vgt_tess_distribution;
431 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
432 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
433 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
434 if (physical_device->rad_info.family < CHIP_POLARIS10)
435 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
436 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
437
438 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
439 S_028B50_ACCUM_TRI(11) |
440 S_028B50_ACCUM_QUAD(11) |
441 S_028B50_DONUT_SPLIT(16);
442
443 if (physical_device->rad_info.family == CHIP_FIJI ||
444 physical_device->rad_info.family >= CHIP_POLARIS10)
445 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
446
447 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
448 vgt_tess_distribution);
449 } else {
450 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
451 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
452 }
453
454 if (physical_device->has_rbplus)
455 radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
456
457 if (physical_device->rad_info.chip_class >= GFX9) {
458 unsigned num_se = physical_device->rad_info.max_se;
459 unsigned pc_lines = 0;
460
461 switch (physical_device->rad_info.family) {
462 case CHIP_VEGA10:
463 pc_lines = 4096;
464 break;
465 case CHIP_RAVEN:
466 pc_lines = 1024;
467 break;
468 default:
469 assert(0);
470 }
471
472 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
473 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
474 radeon_set_context_reg(cs, R_028064_DB_RENDER_FILTER, 0);
475 /* TODO: We can use this to disable RBs for rendering to GART: */
476 radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
477 radeon_set_context_reg(cs, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
478 /* TODO: Enable the binner: */
479 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
480 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
481 S_028C44_DISABLE_START_OF_PRIM(1));
482 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
483 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
484 S_028C48_MAX_PRIM_PER_BATCH(1023));
485 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
486 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
487 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
488 }
489 si_emit_compute(physical_device, cs);
490 }
491
492 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
493 {
494 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
495
496 si_emit_config(physical_device, cmd_buffer->cs);
497 }
498
499 void
500 cik_create_gfx_config(struct radv_device *device)
501 {
502 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
503 if (!cs)
504 return;
505
506 si_emit_config(device->physical_device, cs);
507
508 while (cs->cdw & 7) {
509 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
510 radeon_emit(cs, 0x80000000);
511 else
512 radeon_emit(cs, 0xffff1000);
513 }
514
515 device->gfx_init = device->ws->buffer_create(device->ws,
516 cs->cdw * 4, 4096,
517 RADEON_DOMAIN_GTT,
518 RADEON_FLAG_CPU_ACCESS);
519 if (!device->gfx_init)
520 goto fail;
521
522 void *map = device->ws->buffer_map(device->gfx_init);
523 if (!map) {
524 device->ws->buffer_destroy(device->gfx_init);
525 device->gfx_init = NULL;
526 goto fail;
527 }
528 memcpy(map, cs->buf, cs->cdw * 4);
529
530 device->ws->buffer_unmap(device->gfx_init);
531 device->gfx_init_size_dw = cs->cdw;
532 fail:
533 device->ws->cs_destroy(cs);
534 }
535
536 static void
537 get_viewport_xform(const VkViewport *viewport,
538 float scale[3], float translate[3])
539 {
540 float x = viewport->x;
541 float y = viewport->y;
542 float half_width = 0.5f * viewport->width;
543 float half_height = 0.5f * viewport->height;
544 double n = viewport->minDepth;
545 double f = viewport->maxDepth;
546
547 scale[0] = half_width;
548 translate[0] = half_width + x;
549 scale[1] = half_height;
550 translate[1] = half_height + y;
551
552 scale[2] = (f - n);
553 translate[2] = n;
554 }
555
556 void
557 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
558 int count, const VkViewport *viewports)
559 {
560 int i;
561
562 assert(count);
563 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
564 first_vp * 4 * 6, count * 6);
565
566 for (i = 0; i < count; i++) {
567 float scale[3], translate[3];
568
569
570 get_viewport_xform(&viewports[i], scale, translate);
571 radeon_emit(cs, fui(scale[0]));
572 radeon_emit(cs, fui(translate[0]));
573 radeon_emit(cs, fui(scale[1]));
574 radeon_emit(cs, fui(translate[1]));
575 radeon_emit(cs, fui(scale[2]));
576 radeon_emit(cs, fui(translate[2]));
577 }
578
579 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
580 first_vp * 4 * 2, count * 2);
581 for (i = 0; i < count; i++) {
582 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
583 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
584 radeon_emit(cs, fui(zmin));
585 radeon_emit(cs, fui(zmax));
586 }
587 }
588
589 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
590 {
591 float scale[3], translate[3];
592 VkRect2D rect;
593
594 get_viewport_xform(viewport, scale, translate);
595
596 rect.offset.x = translate[0] - abs(scale[0]);
597 rect.offset.y = translate[1] - abs(scale[1]);
598 rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
599 rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y;
600
601 return rect;
602 }
603
604 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
605 VkRect2D ret;
606 ret.offset.x = MAX2(a->offset.x, b->offset.x);
607 ret.offset.y = MAX2(a->offset.y, b->offset.y);
608 ret.extent.width = MIN2(a->offset.x + a->extent.width,
609 b->offset.x + b->extent.width) - ret.offset.x;
610 ret.extent.height = MIN2(a->offset.y + a->extent.height,
611 b->offset.y + b->extent.height) - ret.offset.y;
612 return ret;
613 }
614
615 void
616 si_write_scissors(struct radeon_winsys_cs *cs, int first,
617 int count, const VkRect2D *scissors,
618 const VkViewport *viewports, bool can_use_guardband)
619 {
620 int i;
621 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
622 const float max_range = 32767.0f;
623 assert(count);
624
625 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
626 for (i = 0; i < count; i++) {
627 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
628 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
629
630 get_viewport_xform(viewports + i, scale, translate);
631 scale[0] = abs(scale[0]);
632 scale[1] = abs(scale[1]);
633
634 if (scale[0] < 0.5)
635 scale[0] = 0.5;
636 if (scale[1] < 0.5)
637 scale[1] = 0.5;
638
639 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
640 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
641
642 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
643 S_028250_TL_Y(scissor.offset.y) |
644 S_028250_WINDOW_OFFSET_DISABLE(1));
645 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
646 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
647 }
648 if (!can_use_guardband) {
649 guardband_x = 1.0;
650 guardband_y = 1.0;
651 }
652
653 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
654 radeon_emit(cs, fui(guardband_y));
655 radeon_emit(cs, fui(1.0));
656 radeon_emit(cs, fui(guardband_x));
657 radeon_emit(cs, fui(1.0));
658 }
659
660 static inline unsigned
661 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
662 {
663 if (num == 0)
664 return 0;
665
666 if (info->incr == 0)
667 return 0;
668
669 if (num < info->min)
670 return 0;
671
672 return 1 + ((num - info->min) / info->incr);
673 }
674
675 uint32_t
676 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
677 bool instanced_draw, bool indirect_draw,
678 uint32_t draw_vertex_count)
679 {
680 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
681 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
682 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
683 const unsigned max_primgroup_in_wave = 2;
684 /* SWITCH_ON_EOP(0) is always preferable. */
685 bool wd_switch_on_eop = false;
686 bool ia_switch_on_eop = false;
687 bool ia_switch_on_eoi = false;
688 bool partial_vs_wave = false;
689 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.partial_es_wave;
690 bool multi_instances_smaller_than_primgroup;
691
692 multi_instances_smaller_than_primgroup = indirect_draw;
693 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
694 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
695 if (num_prims < cmd_buffer->state.pipeline->graphics.primgroup_size)
696 multi_instances_smaller_than_primgroup = true;
697 }
698
699 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_switch_on_eoi;
700 partial_vs_wave = cmd_buffer->state.pipeline->graphics.partial_vs_wave;
701
702 if (chip_class >= CIK) {
703 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.wd_switch_on_eop;
704
705 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
706 * We don't know that for indirect drawing, so treat it as
707 * always problematic. */
708 if (family == CHIP_HAWAII &&
709 (instanced_draw || indirect_draw))
710 wd_switch_on_eop = true;
711
712 /* Performance recommendation for 4 SE Gfx7-8 parts if
713 * instances are smaller than a primgroup.
714 * Assume indirect draws always use small instances.
715 * This is needed for good VS wave utilization.
716 */
717 if (chip_class <= VI &&
718 info->max_se == 4 &&
719 multi_instances_smaller_than_primgroup)
720 wd_switch_on_eop = true;
721
722 /* Required on CIK and later. */
723 if (info->max_se > 2 && !wd_switch_on_eop)
724 ia_switch_on_eoi = true;
725
726 /* Required by Hawaii and, for some special cases, by VI. */
727 if (ia_switch_on_eoi &&
728 (family == CHIP_HAWAII ||
729 (chip_class == VI &&
730 /* max primgroup in wave is always 2 - leave this for documentation */
731 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
732 partial_vs_wave = true;
733
734 /* Instancing bug on Bonaire. */
735 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
736 (instanced_draw || indirect_draw))
737 partial_vs_wave = true;
738
739 /* If the WD switch is false, the IA switch must be false too. */
740 assert(wd_switch_on_eop || !ia_switch_on_eop);
741 }
742 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
743 if (chip_class <= VI && ia_switch_on_eoi)
744 partial_es_wave = true;
745
746 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
747 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
748 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
749 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
750 */
751 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
752 bool set_vgt_flush = indirect_draw;
753 if (!set_vgt_flush && instanced_draw) {
754 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
755 if (num_prims <= 1)
756 set_vgt_flush = true;
757 }
758 if (set_vgt_flush)
759 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
760 }
761 }
762
763 return cmd_buffer->state.pipeline->graphics.base_ia_multi_vgt_param |
764 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
765 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
766 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
767 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
768 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
769
770 }
771
772 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
773 bool predicated,
774 enum chip_class chip_class,
775 bool is_mec,
776 unsigned event, unsigned event_flags,
777 unsigned data_sel,
778 uint64_t va,
779 uint32_t old_fence,
780 uint32_t new_fence)
781 {
782 unsigned op = EVENT_TYPE(event) |
783 EVENT_INDEX(5) |
784 event_flags;
785 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
786
787 if (chip_class >= GFX9 || is_gfx8_mec) {
788 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated));
789 radeon_emit(cs, op);
790 radeon_emit(cs, EOP_DATA_SEL(data_sel));
791 radeon_emit(cs, va); /* address lo */
792 radeon_emit(cs, va >> 32); /* address hi */
793 radeon_emit(cs, new_fence); /* immediate data lo */
794 radeon_emit(cs, 0); /* immediate data hi */
795 if (!is_gfx8_mec)
796 radeon_emit(cs, 0); /* unused */
797 } else {
798 if (chip_class == CIK ||
799 chip_class == VI) {
800 /* Two EOP events are required to make all engines go idle
801 * (and optional cache flushes executed) before the timestamp
802 * is written.
803 */
804 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
805 radeon_emit(cs, op);
806 radeon_emit(cs, va);
807 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
808 radeon_emit(cs, old_fence); /* immediate data */
809 radeon_emit(cs, 0); /* unused */
810 }
811
812 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
813 radeon_emit(cs, op);
814 radeon_emit(cs, va);
815 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
816 radeon_emit(cs, new_fence); /* immediate data */
817 radeon_emit(cs, 0); /* unused */
818 }
819 }
820
821 void
822 si_emit_wait_fence(struct radeon_winsys_cs *cs,
823 bool predicated,
824 uint64_t va, uint32_t ref,
825 uint32_t mask)
826 {
827 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated));
828 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
829 radeon_emit(cs, va);
830 radeon_emit(cs, va >> 32);
831 radeon_emit(cs, ref); /* reference value */
832 radeon_emit(cs, mask); /* mask */
833 radeon_emit(cs, 4); /* poll interval */
834 }
835
836 static void
837 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
838 bool is_mec,
839 bool predicated,
840 bool is_gfx9,
841 unsigned cp_coher_cntl)
842 {
843 if (is_mec || is_gfx9) {
844 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
845 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) |
846 PKT3_SHADER_TYPE_S(is_mec));
847 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
848 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
849 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
850 radeon_emit(cs, 0); /* CP_COHER_BASE */
851 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
852 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
853 } else {
854 /* ACQUIRE_MEM is only required on a compute ring. */
855 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated));
856 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
857 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
858 radeon_emit(cs, 0); /* CP_COHER_BASE */
859 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
860 }
861 }
862
863 void
864 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
865 bool predicated,
866 enum chip_class chip_class,
867 uint32_t *flush_cnt,
868 uint64_t flush_va,
869 bool is_mec,
870 enum radv_cmd_flush_bits flush_bits)
871 {
872 unsigned cp_coher_cntl = 0;
873 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
874 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
875
876 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
877 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
878 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
879 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
880
881 if (chip_class <= VI) {
882 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
883 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
884 S_0085F0_CB0_DEST_BASE_ENA(1) |
885 S_0085F0_CB1_DEST_BASE_ENA(1) |
886 S_0085F0_CB2_DEST_BASE_ENA(1) |
887 S_0085F0_CB3_DEST_BASE_ENA(1) |
888 S_0085F0_CB4_DEST_BASE_ENA(1) |
889 S_0085F0_CB5_DEST_BASE_ENA(1) |
890 S_0085F0_CB6_DEST_BASE_ENA(1) |
891 S_0085F0_CB7_DEST_BASE_ENA(1);
892
893 /* Necessary for DCC */
894 if (chip_class >= VI) {
895 si_cs_emit_write_event_eop(cs,
896 predicated,
897 chip_class,
898 is_mec,
899 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
900 0, 0, 0, 0, 0);
901 }
902 }
903 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
904 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
905 S_0085F0_DB_DEST_BASE_ENA(1);
906 }
907 }
908
909 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
910 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
911 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
912 }
913
914 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
915 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
916 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
917 }
918
919 if (!flush_cb_db) {
920 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
921 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
922 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
923 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
924 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
925 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
926 }
927 }
928
929 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
930 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
931 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
932 }
933
934 if (chip_class >= GFX9 && flush_cb_db) {
935 unsigned cb_db_event, tc_flags;
936
937 /* Set the CB/DB flush event. */
938 switch (flush_cb_db) {
939 case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
940 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
941 break;
942 case RADV_CMD_FLAG_FLUSH_AND_INV_DB:
943 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
944 break;
945 default:
946 /* both CB & DB */
947 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
948 }
949
950 /* TC | TC_WB = invalidate L2 data
951 * TC_MD | TC_WB = invalidate L2 metadata
952 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
953 *
954 * The metadata cache must always be invalidated for coherency
955 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
956 *
957 * TC must be invalidated on GFX9 only if the CB/DB surface is
958 * not pipe-aligned. If the surface is RB-aligned, it might not
959 * strictly be pipe-aligned since RB alignment takes precendence.
960 */
961 tc_flags = EVENT_TC_WB_ACTION_ENA |
962 EVENT_TC_MD_ACTION_ENA;
963
964 /* Ideally flush TC together with CB/DB. */
965 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
966 tc_flags |= EVENT_TC_ACTION_ENA |
967 EVENT_TCL1_ACTION_ENA;
968
969 /* Clear the flags. */
970 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
971 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
972 RADV_CMD_FLAG_INV_VMEM_L1);
973 }
974 assert(flush_cnt);
975 uint32_t old_fence = (*flush_cnt)++;
976
977 si_cs_emit_write_event_eop(cs, predicated, chip_class, false, cb_db_event, tc_flags, 1,
978 flush_va, old_fence, *flush_cnt);
979 si_emit_wait_fence(cs, predicated, flush_va, *flush_cnt, 0xffffffff);
980 }
981
982 /* VGT state sync */
983 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
984 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
985 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
986 }
987
988 /* Make sure ME is idle (it executes most packets) before continuing.
989 * This prevents read-after-write hazards between PFP and ME.
990 */
991 if ((cp_coher_cntl ||
992 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
993 RADV_CMD_FLAG_INV_VMEM_L1 |
994 RADV_CMD_FLAG_INV_GLOBAL_L2 |
995 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
996 !is_mec) {
997 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, predicated));
998 radeon_emit(cs, 0);
999 }
1000
1001 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
1002 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
1003 si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9,
1004 cp_coher_cntl |
1005 S_0085F0_TC_ACTION_ENA(1) |
1006 S_0085F0_TCL1_ACTION_ENA(1) |
1007 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
1008 cp_coher_cntl = 0;
1009 } else {
1010 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
1011 /* WB = write-back
1012 * NC = apply to non-coherent MTYPEs
1013 * (i.e. MTYPE <= 1, which is what we use everywhere)
1014 *
1015 * WB doesn't work without NC.
1016 */
1017 si_emit_acquire_mem(cs, is_mec, predicated,
1018 chip_class >= GFX9,
1019 cp_coher_cntl |
1020 S_0301F0_TC_WB_ACTION_ENA(1) |
1021 S_0301F0_TC_NC_ACTION_ENA(1));
1022 cp_coher_cntl = 0;
1023 }
1024 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
1025 si_emit_acquire_mem(cs, is_mec,
1026 predicated, chip_class >= GFX9,
1027 cp_coher_cntl |
1028 S_0085F0_TCL1_ACTION_ENA(1));
1029 cp_coher_cntl = 0;
1030 }
1031 }
1032
1033 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1034 * Therefore, it should be last. Done in PFP.
1035 */
1036 if (cp_coher_cntl)
1037 si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9, cp_coher_cntl);
1038 }
1039
1040 void
1041 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1042 {
1043 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1044
1045 if (is_compute)
1046 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1047 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1048 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1049 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1050 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1051 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1052 RADV_CMD_FLAG_VGT_FLUSH);
1053
1054 if (!cmd_buffer->state.flush_bits)
1055 return;
1056
1057 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
1058 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1059
1060 uint32_t *ptr = NULL;
1061 uint64_t va = 0;
1062 if (chip_class == GFX9) {
1063 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
1064 ptr = &cmd_buffer->gfx9_fence_idx;
1065 }
1066 si_cs_emit_cache_flush(cmd_buffer->cs,
1067 cmd_buffer->state.predicating,
1068 cmd_buffer->device->physical_device->rad_info.chip_class,
1069 ptr, va,
1070 radv_cmd_buffer_uses_mec(cmd_buffer),
1071 cmd_buffer->state.flush_bits);
1072
1073
1074 radv_cmd_buffer_trace_emit(cmd_buffer);
1075 cmd_buffer->state.flush_bits = 0;
1076 }
1077
1078 /* sets the CP predication state using a boolean stored at va */
1079 void
1080 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1081 {
1082 uint32_t op = 0;
1083
1084 if (va)
1085 op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
1086 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1087 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1088 radeon_emit(cmd_buffer->cs, op);
1089 radeon_emit(cmd_buffer->cs, va);
1090 radeon_emit(cmd_buffer->cs, va >> 32);
1091 } else {
1092 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1093 radeon_emit(cmd_buffer->cs, va);
1094 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1095 }
1096 }
1097
1098 /* Set this if you want the 3D engine to wait until CP DMA is done.
1099 * It should be set on the last CP DMA packet. */
1100 #define CP_DMA_SYNC (1 << 0)
1101
1102 /* Set this if the source data was used as a destination in a previous CP DMA
1103 * packet. It's for preventing a read-after-write (RAW) hazard between two
1104 * CP DMA packets. */
1105 #define CP_DMA_RAW_WAIT (1 << 1)
1106 #define CP_DMA_USE_L2 (1 << 2)
1107 #define CP_DMA_CLEAR (1 << 3)
1108
1109 /* Alignment for optimal performance. */
1110 #define SI_CPDMA_ALIGNMENT 32
1111
1112 /* The max number of bytes that can be copied per packet. */
1113 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1114 {
1115 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1116 S_414_BYTE_COUNT_GFX9(~0u) :
1117 S_414_BYTE_COUNT_GFX6(~0u);
1118
1119 /* make it aligned for optimal performance */
1120 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1121 }
1122
1123 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1124 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1125 * clear value.
1126 */
1127 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1128 uint64_t dst_va, uint64_t src_va,
1129 unsigned size, unsigned flags)
1130 {
1131 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1132 uint32_t header = 0, command = 0;
1133
1134 assert(size);
1135 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1136
1137 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1138 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1139 command |= S_414_BYTE_COUNT_GFX9(size);
1140 else
1141 command |= S_414_BYTE_COUNT_GFX6(size);
1142
1143 /* Sync flags. */
1144 if (flags & CP_DMA_SYNC)
1145 header |= S_411_CP_SYNC(1);
1146 else {
1147 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1148 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1149 else
1150 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1151 }
1152
1153 if (flags & CP_DMA_RAW_WAIT)
1154 command |= S_414_RAW_WAIT(1);
1155
1156 /* Src and dst flags. */
1157 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1158 !(flags & CP_DMA_CLEAR) &&
1159 src_va == dst_va)
1160 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
1161 else if (flags & CP_DMA_USE_L2)
1162 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
1163
1164 if (flags & CP_DMA_CLEAR)
1165 header |= S_411_SRC_SEL(V_411_DATA);
1166 else if (flags & CP_DMA_USE_L2)
1167 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1168
1169 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1170 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1171 radeon_emit(cs, header);
1172 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1173 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1174 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1175 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1176 radeon_emit(cs, command);
1177 } else {
1178 assert(!(flags & CP_DMA_USE_L2));
1179 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1180 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1181 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1182 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1183 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1184 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1185 radeon_emit(cs, command);
1186 }
1187
1188 /* CP DMA is executed in ME, but index buffers are read by PFP.
1189 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1190 * indices. If we wanted to execute CP DMA in PFP, this packet
1191 * should precede it.
1192 */
1193 if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1194 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1195 radeon_emit(cs, 0);
1196 }
1197
1198 radv_cmd_buffer_trace_emit(cmd_buffer);
1199 }
1200
1201 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1202 unsigned size)
1203 {
1204 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1205 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1206
1207 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1208 aligned_size, CP_DMA_USE_L2);
1209 }
1210
1211 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1212 uint64_t remaining_size, unsigned *flags)
1213 {
1214
1215 /* Flush the caches for the first copy only.
1216 * Also wait for the previous CP DMA operations.
1217 */
1218 if (cmd_buffer->state.flush_bits) {
1219 si_emit_cache_flush(cmd_buffer);
1220 *flags |= CP_DMA_RAW_WAIT;
1221 }
1222
1223 /* Do the synchronization after the last dma, so that all data
1224 * is written to memory.
1225 */
1226 if (byte_count == remaining_size)
1227 *flags |= CP_DMA_SYNC;
1228 }
1229
1230 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1231 {
1232 uint64_t va;
1233 uint32_t offset;
1234 unsigned dma_flags = 0;
1235 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1236 void *ptr;
1237
1238 assert(size < SI_CPDMA_ALIGNMENT);
1239
1240 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1241
1242 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1243 va += offset;
1244
1245 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1246
1247 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1248 dma_flags);
1249 }
1250
1251 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1252 uint64_t src_va, uint64_t dest_va,
1253 uint64_t size)
1254 {
1255 uint64_t main_src_va, main_dest_va;
1256 uint64_t skipped_size = 0, realign_size = 0;
1257
1258
1259 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1260 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1261 /* If the size is not aligned, we must add a dummy copy at the end
1262 * just to align the internal counter. Otherwise, the DMA engine
1263 * would slow down by an order of magnitude for following copies.
1264 */
1265 if (size % SI_CPDMA_ALIGNMENT)
1266 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1267
1268 /* If the copy begins unaligned, we must start copying from the next
1269 * aligned block and the skipped part should be copied after everything
1270 * else has been copied. Only the src alignment matters, not dst.
1271 */
1272 if (src_va % SI_CPDMA_ALIGNMENT) {
1273 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1274 /* The main part will be skipped if the size is too small. */
1275 skipped_size = MIN2(skipped_size, size);
1276 size -= skipped_size;
1277 }
1278 }
1279 main_src_va = src_va + skipped_size;
1280 main_dest_va = dest_va + skipped_size;
1281
1282 while (size) {
1283 unsigned dma_flags = 0;
1284 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1285
1286 si_cp_dma_prepare(cmd_buffer, byte_count,
1287 size + skipped_size + realign_size,
1288 &dma_flags);
1289
1290 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1291 byte_count, dma_flags);
1292
1293 size -= byte_count;
1294 main_src_va += byte_count;
1295 main_dest_va += byte_count;
1296 }
1297
1298 if (skipped_size) {
1299 unsigned dma_flags = 0;
1300
1301 si_cp_dma_prepare(cmd_buffer, skipped_size,
1302 size + skipped_size + realign_size,
1303 &dma_flags);
1304
1305 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1306 skipped_size, dma_flags);
1307 }
1308 if (realign_size)
1309 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1310 }
1311
1312 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1313 uint64_t size, unsigned value)
1314 {
1315
1316 if (!size)
1317 return;
1318
1319 assert(va % 4 == 0 && size % 4 == 0);
1320
1321 while (size) {
1322 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1323 unsigned dma_flags = CP_DMA_CLEAR;
1324
1325 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1326
1327 /* Emit the clear packet. */
1328 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1329 dma_flags);
1330
1331 size -= byte_count;
1332 va += byte_count;
1333 }
1334 }
1335
1336 /* For MSAA sample positions. */
1337 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1338 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1339 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1340 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1341 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1342
1343
1344 /* 2xMSAA
1345 * There are two locations (4, 4), (-4, -4). */
1346 const uint32_t eg_sample_locs_2x[4] = {
1347 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1348 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1349 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1350 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1351 };
1352 const unsigned eg_max_dist_2x = 4;
1353 /* 4xMSAA
1354 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1355 const uint32_t eg_sample_locs_4x[4] = {
1356 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1357 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1358 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1359 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1360 };
1361 const unsigned eg_max_dist_4x = 6;
1362
1363 /* Cayman 8xMSAA */
1364 static const uint32_t cm_sample_locs_8x[] = {
1365 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1366 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1367 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1368 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1369 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1370 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1371 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1372 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1373 };
1374 static const unsigned cm_max_dist_8x = 8;
1375 /* Cayman 16xMSAA */
1376 static const uint32_t cm_sample_locs_16x[] = {
1377 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1378 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1379 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1380 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1381 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1382 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1383 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1384 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1385 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1386 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1387 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1388 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1389 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1390 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1391 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1392 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1393 };
1394 static const unsigned cm_max_dist_16x = 8;
1395
1396 unsigned radv_cayman_get_maxdist(int log_samples)
1397 {
1398 unsigned max_dist[] = {
1399 0,
1400 eg_max_dist_2x,
1401 eg_max_dist_4x,
1402 cm_max_dist_8x,
1403 cm_max_dist_16x
1404 };
1405 return max_dist[log_samples];
1406 }
1407
1408 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1409 {
1410 switch (nr_samples) {
1411 default:
1412 case 1:
1413 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1414 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1415 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1416 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1417 break;
1418 case 2:
1419 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1420 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1421 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1422 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1423 break;
1424 case 4:
1425 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1426 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1427 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1428 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1429 break;
1430 case 8:
1431 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1432 radeon_emit(cs, cm_sample_locs_8x[0]);
1433 radeon_emit(cs, cm_sample_locs_8x[4]);
1434 radeon_emit(cs, 0);
1435 radeon_emit(cs, 0);
1436 radeon_emit(cs, cm_sample_locs_8x[1]);
1437 radeon_emit(cs, cm_sample_locs_8x[5]);
1438 radeon_emit(cs, 0);
1439 radeon_emit(cs, 0);
1440 radeon_emit(cs, cm_sample_locs_8x[2]);
1441 radeon_emit(cs, cm_sample_locs_8x[6]);
1442 radeon_emit(cs, 0);
1443 radeon_emit(cs, 0);
1444 radeon_emit(cs, cm_sample_locs_8x[3]);
1445 radeon_emit(cs, cm_sample_locs_8x[7]);
1446 break;
1447 case 16:
1448 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1449 radeon_emit(cs, cm_sample_locs_16x[0]);
1450 radeon_emit(cs, cm_sample_locs_16x[4]);
1451 radeon_emit(cs, cm_sample_locs_16x[8]);
1452 radeon_emit(cs, cm_sample_locs_16x[12]);
1453 radeon_emit(cs, cm_sample_locs_16x[1]);
1454 radeon_emit(cs, cm_sample_locs_16x[5]);
1455 radeon_emit(cs, cm_sample_locs_16x[9]);
1456 radeon_emit(cs, cm_sample_locs_16x[13]);
1457 radeon_emit(cs, cm_sample_locs_16x[2]);
1458 radeon_emit(cs, cm_sample_locs_16x[6]);
1459 radeon_emit(cs, cm_sample_locs_16x[10]);
1460 radeon_emit(cs, cm_sample_locs_16x[14]);
1461 radeon_emit(cs, cm_sample_locs_16x[3]);
1462 radeon_emit(cs, cm_sample_locs_16x[7]);
1463 radeon_emit(cs, cm_sample_locs_16x[11]);
1464 radeon_emit(cs, cm_sample_locs_16x[15]);
1465 break;
1466 }
1467 }
1468
1469 static void radv_cayman_get_sample_position(struct radv_device *device,
1470 unsigned sample_count,
1471 unsigned sample_index, float *out_value)
1472 {
1473 int offset, index;
1474 struct {
1475 int idx:4;
1476 } val;
1477 switch (sample_count) {
1478 case 1:
1479 default:
1480 out_value[0] = out_value[1] = 0.5;
1481 break;
1482 case 2:
1483 offset = 4 * (sample_index * 2);
1484 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1485 out_value[0] = (float)(val.idx + 8) / 16.0f;
1486 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1487 out_value[1] = (float)(val.idx + 8) / 16.0f;
1488 break;
1489 case 4:
1490 offset = 4 * (sample_index * 2);
1491 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1492 out_value[0] = (float)(val.idx + 8) / 16.0f;
1493 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1494 out_value[1] = (float)(val.idx + 8) / 16.0f;
1495 break;
1496 case 8:
1497 offset = 4 * (sample_index % 4 * 2);
1498 index = (sample_index / 4) * 4;
1499 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1500 out_value[0] = (float)(val.idx + 8) / 16.0f;
1501 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1502 out_value[1] = (float)(val.idx + 8) / 16.0f;
1503 break;
1504 case 16:
1505 offset = 4 * (sample_index % 4 * 2);
1506 index = (sample_index / 4) * 4;
1507 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1508 out_value[0] = (float)(val.idx + 8) / 16.0f;
1509 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1510 out_value[1] = (float)(val.idx + 8) / 16.0f;
1511 break;
1512 }
1513 }
1514
1515 void radv_device_init_msaa(struct radv_device *device)
1516 {
1517 int i;
1518 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1519
1520 for (i = 0; i < 2; i++)
1521 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1522 for (i = 0; i < 4; i++)
1523 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1524 for (i = 0; i < 8; i++)
1525 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1526 for (i = 0; i < 16; i++)
1527 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1528 }