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ac5f8e7036e1faa8739ca45e0fa3d10ae80ffbb0
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35
36 static void
37 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
38 struct radeon_cmdbuf *cs,
39 unsigned raster_config,
40 unsigned raster_config_1)
41 {
42 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
43 unsigned raster_config_se[4];
44 unsigned se;
45
46 ac_get_harvested_configs(&physical_device->rad_info,
47 raster_config,
48 &raster_config_1,
49 raster_config_se);
50
51 for (se = 0; se < num_se; se++) {
52 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
53 if (physical_device->rad_info.chip_class < GFX7)
54 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
55 S_00802C_SE_INDEX(se) |
56 S_00802C_SH_BROADCAST_WRITES(1) |
57 S_00802C_INSTANCE_BROADCAST_WRITES(1));
58 else
59 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
60 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
61 S_030800_INSTANCE_BROADCAST_WRITES(1));
62 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
63 }
64
65 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
66 if (physical_device->rad_info.chip_class < GFX7)
67 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
68 S_00802C_SE_BROADCAST_WRITES(1) |
69 S_00802C_SH_BROADCAST_WRITES(1) |
70 S_00802C_INSTANCE_BROADCAST_WRITES(1));
71 else
72 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
73 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
74 S_030800_INSTANCE_BROADCAST_WRITES(1));
75
76 if (physical_device->rad_info.chip_class >= GFX7)
77 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
78 }
79
80 void
81 si_emit_compute(struct radv_device *device,
82 struct radeon_cmdbuf *cs)
83 {
84 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
85 radeon_emit(cs, 0);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88
89 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
90 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
91 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (device->physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103
104 if (device->border_color_data.bo) {
105 uint64_t bc_va = radv_buffer_get_va(device->border_color_data.bo);
106
107 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
108 radeon_emit(cs, bc_va >> 8);
109 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40));
110 }
111 }
112
113 if (device->physical_device->rad_info.chip_class >= GFX9) {
114 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
115 device->physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0);
116 }
117
118 if (device->physical_device->rad_info.chip_class >= GFX10) {
119 radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0);
120 radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0);
121 radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0);
122 radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0);
123 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
124 radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0);
125 }
126
127 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
128 * and is now per pipe, so it should be handled in the
129 * kernel if we want to use something other than the default value,
130 * which is now 0x22f.
131 */
132 if (device->physical_device->rad_info.chip_class <= GFX6) {
133 /* XXX: This should be:
134 * (number of compute units) * 4 * (waves per simd) - 1 */
135
136 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
137 0x190 /* Default value */);
138
139 if (device->border_color_data.bo) {
140 uint64_t bc_va = radv_buffer_get_va(device->border_color_data.bo);
141 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
142 }
143 }
144 }
145
146 /* 12.4 fixed-point */
147 static unsigned radv_pack_float_12p4(float x)
148 {
149 return x <= 0 ? 0 :
150 x >= 4096 ? 0xffff : x * 16;
151 }
152
153 static void
154 si_set_raster_config(struct radv_physical_device *physical_device,
155 struct radeon_cmdbuf *cs)
156 {
157 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
158 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
159 unsigned raster_config, raster_config_1;
160
161 ac_get_raster_config(&physical_device->rad_info,
162 &raster_config,
163 &raster_config_1, NULL);
164
165 /* Always use the default config when all backends are enabled
166 * (or when we failed to determine the enabled backends).
167 */
168 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
169 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
170 raster_config);
171 if (physical_device->rad_info.chip_class >= GFX7)
172 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
173 raster_config_1);
174 } else {
175 si_write_harvested_raster_configs(physical_device, cs,
176 raster_config,
177 raster_config_1);
178 }
179 }
180
181 void
182 si_emit_graphics(struct radv_device *device,
183 struct radeon_cmdbuf *cs)
184 {
185 struct radv_physical_device *physical_device = device->physical_device;
186
187 bool has_clear_state = physical_device->rad_info.has_clear_state;
188 int i;
189
190 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
191 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
192 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
193
194 if (has_clear_state) {
195 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
196 radeon_emit(cs, 0);
197 }
198
199 if (physical_device->rad_info.chip_class <= GFX8)
200 si_set_raster_config(physical_device, cs);
201
202 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
203 if (!has_clear_state)
204 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
205
206 /* FIXME calculate these values somehow ??? */
207 if (physical_device->rad_info.chip_class <= GFX8) {
208 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
209 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
210 }
211
212 if (!has_clear_state) {
213 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
214 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
215 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
216 }
217
218 if (physical_device->rad_info.chip_class <= GFX9)
219 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
220 if (!has_clear_state)
221 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
222 if (physical_device->rad_info.chip_class < GFX7)
223 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
224 S_008A14_CLIP_VTX_REORDER_ENA(1));
225
226 if (!has_clear_state)
227 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
228
229 /* CLEAR_STATE doesn't clear these correctly on certain generations.
230 * I don't know why. Deduced by trial and error.
231 */
232 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) {
233 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
234 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
235 S_028204_WINDOW_OFFSET_DISABLE(1));
236 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
237 S_028240_WINDOW_OFFSET_DISABLE(1));
238 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
239 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
240 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
241 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
242 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
243 }
244
245 if (!has_clear_state) {
246 for (i = 0; i < 16; i++) {
247 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
248 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
249 }
250 }
251
252 if (!has_clear_state) {
253 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
254 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
255 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
256 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
257 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
258 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
259 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
260 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
261 }
262
263 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
264 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
265 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
266
267 if (physical_device->rad_info.chip_class >= GFX10) {
268 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
269 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
270 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
271 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
272 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
273 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
274 } else if (physical_device->rad_info.chip_class == GFX9) {
275 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
276 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
277 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
278 } else {
279 /* These registers, when written, also overwrite the
280 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
281 * them. It would be an issue if there was another UMD
282 * changing them.
283 */
284 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
285 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
286 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
287 }
288
289 if (physical_device->rad_info.chip_class >= GFX7) {
290 if (physical_device->rad_info.chip_class >= GFX10) {
291 /* Logical CUs 16 - 31 */
292 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
293 3, S_00B404_CU_EN(0xffff));
294 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
295 3, S_00B104_CU_EN(0xffff));
296 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
297 3, S_00B004_CU_EN(0xffff));
298 }
299
300 if (physical_device->rad_info.chip_class >= GFX9) {
301 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
302 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
303 } else {
304 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
305 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
306 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
307 S_00B41C_WAVE_LIMIT(0x3F));
308 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
309 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
310 /* If this is 0, Bonaire can hang even if GS isn't being used.
311 * Other chips are unaffected. These are suboptimal values,
312 * but we don't use on-chip GS.
313 */
314 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
315 S_028A44_ES_VERTS_PER_SUBGRP(64) |
316 S_028A44_GS_PRIMS_PER_SUBGRP(4));
317 }
318
319 /* Compute LATE_ALLOC_VS.LIMIT. */
320 unsigned num_cu_per_sh = physical_device->rad_info.min_good_cu_per_sa;
321 unsigned late_alloc_wave64 = 0; /* The limit is per SA. */
322 unsigned late_alloc_wave64_gs = 0;
323 unsigned cu_mask_vs = 0xffff;
324 unsigned cu_mask_gs = 0xffff;
325
326 if (physical_device->rad_info.chip_class >= GFX10) {
327 /* For Wave32, the hw will launch twice the number of late
328 * alloc waves, so 1 == 2x wave32.
329 */
330 if (!physical_device->rad_info.use_late_alloc) {
331 late_alloc_wave64 = 0;
332 } else if (num_cu_per_sh <= 6) {
333 late_alloc_wave64 = num_cu_per_sh - 2;
334 } else {
335 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
336
337 /* CU2 & CU3 disabled because of the dual CU design */
338 cu_mask_vs = 0xfff3;
339 cu_mask_gs = 0xfff3; /* NGG only */
340 }
341
342 late_alloc_wave64_gs = late_alloc_wave64;
343
344 /* Don't use late alloc for NGG on Navi14 due to a hw
345 * bug. If NGG is never used, enable all CUs.
346 */
347 if (!physical_device->use_ngg ||
348 physical_device->rad_info.family == CHIP_NAVI14) {
349 late_alloc_wave64_gs = 0;
350 cu_mask_gs = 0xffff;
351 }
352
353 /* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
354 if (physical_device->rad_info.chip_class == GFX10)
355 late_alloc_wave64_gs = MIN2(late_alloc_wave64_gs, 64);
356 } else {
357 if (!physical_device->rad_info.use_late_alloc) {
358 late_alloc_wave64 = 0;
359 } else if (num_cu_per_sh <= 4) {
360 /* Too few available compute units per SA.
361 * Disallowing VS to run on one CU could hurt
362 * us more than late VS allocation would help.
363 *
364 * 2 is the highest safe number that allows us
365 * to keep all CUs enabled.
366 */
367 late_alloc_wave64 = 2;
368 } else {
369 /* This is a good initial value, allowing 1
370 * late_alloc wave per SIMD on num_cu - 2.
371 */
372 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
373 }
374
375 if (late_alloc_wave64 > 2)
376 cu_mask_vs = 0xfffe; /* 1 CU disabled */
377 }
378
379 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
380 3, S_00B118_CU_EN(cu_mask_vs) |
381 S_00B118_WAVE_LIMIT(0x3F));
382 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
383 S_00B11C_LIMIT(late_alloc_wave64));
384
385 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
386 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
387
388 if (physical_device->rad_info.chip_class >= GFX10) {
389 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
390 3, S_00B204_CU_EN(0xffff) |
391 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64_gs));
392 }
393
394 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
395 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
396 }
397
398 if (physical_device->rad_info.chip_class >= GFX10) {
399 /* Break up a pixel wave if it contains deallocs for more than
400 * half the parameter cache.
401 *
402 * To avoid a deadlock where pixel waves aren't launched
403 * because they're waiting for more pixels while the frontend
404 * is stuck waiting for PC space, the maximum allowed value is
405 * the size of the PC minus the largest possible allocation for
406 * a single primitive shader subgroup.
407 */
408 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
409 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
410 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
411 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
412
413 radeon_set_sh_reg(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 0);
414 radeon_set_sh_reg(cs, R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1, 0);
415 radeon_set_sh_reg(cs, R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2, 0);
416 radeon_set_sh_reg(cs, R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3, 0);
417 radeon_set_sh_reg(cs, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 0);
418 radeon_set_sh_reg(cs, R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1, 0);
419 radeon_set_sh_reg(cs, R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2, 0);
420 radeon_set_sh_reg(cs, R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3, 0);
421 radeon_set_sh_reg(cs, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 0);
422 radeon_set_sh_reg(cs, R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1, 0);
423 radeon_set_sh_reg(cs, R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2, 0);
424 radeon_set_sh_reg(cs, R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3, 0);
425 radeon_set_sh_reg(cs, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 0);
426 radeon_set_sh_reg(cs, R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1, 0);
427 radeon_set_sh_reg(cs, R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2, 0);
428 radeon_set_sh_reg(cs, R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3, 0);
429
430 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
431 S_00B0C0_SOFT_GROUPING_EN(1) |
432 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
433 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
434
435 if (physical_device->rad_info.chip_class >= GFX10_3) {
436 radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103, 0xff);
437 radeon_set_context_reg(cs, 0x28848, 1 << 9); /* This fixes sample shading. */
438 }
439
440 if (physical_device->rad_info.chip_class == GFX10) {
441 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
442 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
443 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
444 }
445
446 /* TODO: For culling, replace 128 with 256. */
447 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
448 S_030980_OVERSUB_EN(physical_device->rad_info.use_late_alloc) |
449 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
450 }
451
452 if (physical_device->rad_info.chip_class >= GFX9) {
453 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
454 S_028B50_ACCUM_ISOLINE(40) |
455 S_028B50_ACCUM_TRI(30) |
456 S_028B50_ACCUM_QUAD(24) |
457 S_028B50_DONUT_SPLIT(24) |
458 S_028B50_TRAP_SPLIT(6));
459 } else if (physical_device->rad_info.chip_class >= GFX8) {
460 uint32_t vgt_tess_distribution;
461
462 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
463 S_028B50_ACCUM_TRI(11) |
464 S_028B50_ACCUM_QUAD(11) |
465 S_028B50_DONUT_SPLIT(16);
466
467 if (physical_device->rad_info.family == CHIP_FIJI ||
468 physical_device->rad_info.family >= CHIP_POLARIS10)
469 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
470
471 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
472 vgt_tess_distribution);
473 } else if (!has_clear_state) {
474 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
475 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
476 }
477
478 if (device->border_color_data.bo) {
479 uint64_t border_color_va = radv_buffer_get_va(device->border_color_data.bo);
480
481 radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
482 if (physical_device->rad_info.chip_class >= GFX7) {
483 radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI,
484 S_028084_ADDRESS(border_color_va >> 40));
485 }
486 }
487
488 if (physical_device->rad_info.chip_class >= GFX9) {
489 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
490 S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
491 S_028C48_MAX_PRIM_PER_BATCH(1023));
492 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
493 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
494 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
495 }
496
497 unsigned tmp = (unsigned)(1.0 * 8.0);
498 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
499 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
500 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
501 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
502 S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875/2)));
503
504 if (!has_clear_state) {
505 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
506 S_028004_ZPASS_INCREMENT_DISABLE(1));
507 }
508
509 /* Enable the Polaris small primitive filter control.
510 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
511 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
512 * and AMDVLK doesn't have a workaround as well.
513 */
514 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
515 unsigned small_prim_filter_cntl =
516 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
517 /* Workaround for a hw line bug. */
518 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
519
520 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
521 small_prim_filter_cntl);
522 }
523
524 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
525 S_0286D4_FLAT_SHADE_ENA(1) |
526 S_0286D4_PNT_SPRITE_ENA(1) |
527 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
528 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
529 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
530 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
531 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
532
533 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
534 S_028BE4_PIX_CENTER(1) |
535 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
536 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
537
538 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
539 S_028818_VTX_W0_FMT(1) |
540 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
541 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
542 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
543
544 si_emit_compute(device, cs);
545 }
546
547 void
548 cik_create_gfx_config(struct radv_device *device)
549 {
550 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
551 if (!cs)
552 return;
553
554 si_emit_graphics(device, cs);
555
556 while (cs->cdw & 7) {
557 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
558 radeon_emit(cs, PKT2_NOP_PAD);
559 else
560 radeon_emit(cs, PKT3_NOP_PAD);
561 }
562
563 device->gfx_init = device->ws->buffer_create(device->ws,
564 cs->cdw * 4, 4096,
565 RADEON_DOMAIN_GTT,
566 RADEON_FLAG_CPU_ACCESS|
567 RADEON_FLAG_NO_INTERPROCESS_SHARING |
568 RADEON_FLAG_READ_ONLY |
569 RADEON_FLAG_GTT_WC,
570 RADV_BO_PRIORITY_CS);
571 if (!device->gfx_init)
572 goto fail;
573
574 void *map = device->ws->buffer_map(device->gfx_init);
575 if (!map) {
576 device->ws->buffer_destroy(device->gfx_init);
577 device->gfx_init = NULL;
578 goto fail;
579 }
580 memcpy(map, cs->buf, cs->cdw * 4);
581
582 device->ws->buffer_unmap(device->gfx_init);
583 device->gfx_init_size_dw = cs->cdw;
584 fail:
585 device->ws->cs_destroy(cs);
586 }
587
588 static void
589 get_viewport_xform(const VkViewport *viewport,
590 float scale[3], float translate[3])
591 {
592 float x = viewport->x;
593 float y = viewport->y;
594 float half_width = 0.5f * viewport->width;
595 float half_height = 0.5f * viewport->height;
596 double n = viewport->minDepth;
597 double f = viewport->maxDepth;
598
599 scale[0] = half_width;
600 translate[0] = half_width + x;
601 scale[1] = half_height;
602 translate[1] = half_height + y;
603
604 scale[2] = (f - n);
605 translate[2] = n;
606 }
607
608 void
609 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
610 int count, const VkViewport *viewports)
611 {
612 int i;
613
614 assert(count);
615 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
616 first_vp * 4 * 6, count * 6);
617
618 for (i = 0; i < count; i++) {
619 float scale[3], translate[3];
620
621
622 get_viewport_xform(&viewports[i], scale, translate);
623 radeon_emit(cs, fui(scale[0]));
624 radeon_emit(cs, fui(translate[0]));
625 radeon_emit(cs, fui(scale[1]));
626 radeon_emit(cs, fui(translate[1]));
627 radeon_emit(cs, fui(scale[2]));
628 radeon_emit(cs, fui(translate[2]));
629 }
630
631 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
632 first_vp * 4 * 2, count * 2);
633 for (i = 0; i < count; i++) {
634 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
635 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
636 radeon_emit(cs, fui(zmin));
637 radeon_emit(cs, fui(zmax));
638 }
639 }
640
641 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
642 {
643 float scale[3], translate[3];
644 VkRect2D rect;
645
646 get_viewport_xform(viewport, scale, translate);
647
648 rect.offset.x = translate[0] - fabsf(scale[0]);
649 rect.offset.y = translate[1] - fabsf(scale[1]);
650 rect.extent.width = ceilf(translate[0] + fabsf(scale[0])) - rect.offset.x;
651 rect.extent.height = ceilf(translate[1] + fabsf(scale[1])) - rect.offset.y;
652
653 return rect;
654 }
655
656 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
657 VkRect2D ret;
658 ret.offset.x = MAX2(a->offset.x, b->offset.x);
659 ret.offset.y = MAX2(a->offset.y, b->offset.y);
660 ret.extent.width = MIN2(a->offset.x + a->extent.width,
661 b->offset.x + b->extent.width) - ret.offset.x;
662 ret.extent.height = MIN2(a->offset.y + a->extent.height,
663 b->offset.y + b->extent.height) - ret.offset.y;
664 return ret;
665 }
666
667 void
668 si_write_scissors(struct radeon_cmdbuf *cs, int first,
669 int count, const VkRect2D *scissors,
670 const VkViewport *viewports, bool can_use_guardband)
671 {
672 int i;
673 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
674 const float max_range = 32767.0f;
675 if (!count)
676 return;
677
678 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
679 for (i = 0; i < count; i++) {
680 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
681 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
682
683 get_viewport_xform(viewports + i, scale, translate);
684 scale[0] = fabsf(scale[0]);
685 scale[1] = fabsf(scale[1]);
686
687 if (scale[0] < 0.5)
688 scale[0] = 0.5;
689 if (scale[1] < 0.5)
690 scale[1] = 0.5;
691
692 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
693 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
694
695 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
696 S_028250_TL_Y(scissor.offset.y) |
697 S_028250_WINDOW_OFFSET_DISABLE(1));
698 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
699 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
700 }
701 if (!can_use_guardband) {
702 guardband_x = 1.0;
703 guardband_y = 1.0;
704 }
705
706 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
707 radeon_emit(cs, fui(guardband_y));
708 radeon_emit(cs, fui(1.0));
709 radeon_emit(cs, fui(guardband_x));
710 radeon_emit(cs, fui(1.0));
711 }
712
713 static inline unsigned
714 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
715 {
716 if (num == 0)
717 return 0;
718
719 if (info->incr == 0)
720 return 0;
721
722 if (num < info->min)
723 return 0;
724
725 return 1 + ((num - info->min) / info->incr);
726 }
727
728 static const struct radv_prim_vertex_count prim_size_table[] = {
729 [V_008958_DI_PT_NONE] = {0, 0},
730 [V_008958_DI_PT_POINTLIST] = {1, 1},
731 [V_008958_DI_PT_LINELIST] = {2, 2},
732 [V_008958_DI_PT_LINESTRIP] = {2, 1},
733 [V_008958_DI_PT_TRILIST] = {3, 3},
734 [V_008958_DI_PT_TRIFAN] = {3, 1},
735 [V_008958_DI_PT_TRISTRIP] = {3, 1},
736 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
737 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
738 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
739 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
740 [V_008958_DI_PT_RECTLIST] = {3, 3},
741 [V_008958_DI_PT_LINELOOP] = {2, 1},
742 [V_008958_DI_PT_POLYGON] = {3, 1},
743 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
744 };
745
746 uint32_t
747 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
748 bool instanced_draw, bool indirect_draw,
749 bool count_from_stream_output,
750 uint32_t draw_vertex_count,
751 unsigned topology)
752 {
753 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
754 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
755 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
756 const unsigned max_primgroup_in_wave = 2;
757 /* SWITCH_ON_EOP(0) is always preferable. */
758 bool wd_switch_on_eop = false;
759 bool ia_switch_on_eop = false;
760 bool ia_switch_on_eoi = false;
761 bool partial_vs_wave = false;
762 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
763 bool multi_instances_smaller_than_primgroup;
764 struct radv_prim_vertex_count prim_vertex_count = prim_size_table[topology];
765
766 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline)) {
767 if (topology == V_008958_DI_PT_PATCH) {
768 prim_vertex_count.min = cmd_buffer->state.pipeline->graphics.tess_patch_control_points;
769 prim_vertex_count.incr = 1;
770 }
771 }
772
773 multi_instances_smaller_than_primgroup = indirect_draw;
774 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
775 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
776 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
777 multi_instances_smaller_than_primgroup = true;
778 }
779
780 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
781 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
782
783 if (chip_class >= GFX7) {
784 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
785 * 4 shader engines. Set 1 to pass the assertion below.
786 * The other cases are hardware requirements. */
787 if (cmd_buffer->device->physical_device->rad_info.max_se < 4 ||
788 topology == V_008958_DI_PT_POLYGON ||
789 topology == V_008958_DI_PT_LINELOOP ||
790 topology == V_008958_DI_PT_TRIFAN ||
791 topology == V_008958_DI_PT_TRISTRIP_ADJ ||
792 (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
793 (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
794 (topology != V_008958_DI_PT_POINTLIST &&
795 topology != V_008958_DI_PT_LINESTRIP))))
796 wd_switch_on_eop = true;
797
798 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
799 * We don't know that for indirect drawing, so treat it as
800 * always problematic. */
801 if (family == CHIP_HAWAII &&
802 (instanced_draw || indirect_draw))
803 wd_switch_on_eop = true;
804
805 /* Performance recommendation for 4 SE Gfx7-8 parts if
806 * instances are smaller than a primgroup.
807 * Assume indirect draws always use small instances.
808 * This is needed for good VS wave utilization.
809 */
810 if (chip_class <= GFX8 &&
811 info->max_se == 4 &&
812 multi_instances_smaller_than_primgroup)
813 wd_switch_on_eop = true;
814
815 /* Required on GFX7 and later. */
816 if (info->max_se > 2 && !wd_switch_on_eop)
817 ia_switch_on_eoi = true;
818
819 /* Required by Hawaii and, for some special cases, by GFX8. */
820 if (ia_switch_on_eoi &&
821 (family == CHIP_HAWAII ||
822 (chip_class == GFX8 &&
823 /* max primgroup in wave is always 2 - leave this for documentation */
824 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
825 partial_vs_wave = true;
826
827 /* Instancing bug on Bonaire. */
828 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
829 (instanced_draw || indirect_draw))
830 partial_vs_wave = true;
831
832 /* Hardware requirement when drawing primitives from a stream
833 * output buffer.
834 */
835 if (count_from_stream_output)
836 wd_switch_on_eop = true;
837
838 /* If the WD switch is false, the IA switch must be false too. */
839 assert(wd_switch_on_eop || !ia_switch_on_eop);
840 }
841 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
842 if (chip_class <= GFX8 && ia_switch_on_eoi)
843 partial_es_wave = true;
844
845 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
846 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
847 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
848 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
849 */
850 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
851 bool set_vgt_flush = indirect_draw;
852 if (!set_vgt_flush && instanced_draw) {
853 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
854 if (num_prims <= 1)
855 set_vgt_flush = true;
856 }
857 if (set_vgt_flush)
858 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
859 }
860 }
861
862 /* Workaround for a VGT hang when strip primitive types are used with
863 * primitive restart.
864 */
865 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
866 (topology == V_008958_DI_PT_LINESTRIP ||
867 topology == V_008958_DI_PT_TRISTRIP ||
868 topology == V_008958_DI_PT_LINESTRIP_ADJ ||
869 topology == V_008958_DI_PT_TRISTRIP_ADJ)) {
870 partial_vs_wave = true;
871 }
872
873 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
874 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
875 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
876 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
877 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
878 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
879
880 }
881
882 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
883 enum chip_class chip_class,
884 bool is_mec,
885 unsigned event, unsigned event_flags,
886 unsigned dst_sel, unsigned data_sel,
887 uint64_t va,
888 uint32_t new_fence,
889 uint64_t gfx9_eop_bug_va)
890 {
891 unsigned op = EVENT_TYPE(event) |
892 EVENT_INDEX(event == V_028A90_CS_DONE ||
893 event == V_028A90_PS_DONE ? 6 : 5) |
894 event_flags;
895 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
896 unsigned sel = EOP_DST_SEL(dst_sel) |
897 EOP_DATA_SEL(data_sel);
898
899 /* Wait for write confirmation before writing data, but don't send
900 * an interrupt. */
901 if (data_sel != EOP_DATA_SEL_DISCARD)
902 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
903
904 if (chip_class >= GFX9 || is_gfx8_mec) {
905 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
906 * counters) must immediately precede every timestamp event to
907 * prevent a GPU hang on GFX9.
908 */
909 if (chip_class == GFX9 && !is_mec) {
910 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
911 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
912 radeon_emit(cs, gfx9_eop_bug_va);
913 radeon_emit(cs, gfx9_eop_bug_va >> 32);
914 }
915
916 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
917 radeon_emit(cs, op);
918 radeon_emit(cs, sel);
919 radeon_emit(cs, va); /* address lo */
920 radeon_emit(cs, va >> 32); /* address hi */
921 radeon_emit(cs, new_fence); /* immediate data lo */
922 radeon_emit(cs, 0); /* immediate data hi */
923 if (!is_gfx8_mec)
924 radeon_emit(cs, 0); /* unused */
925 } else {
926 if (chip_class == GFX7 ||
927 chip_class == GFX8) {
928 /* Two EOP events are required to make all engines go idle
929 * (and optional cache flushes executed) before the timestamp
930 * is written.
931 */
932 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
933 radeon_emit(cs, op);
934 radeon_emit(cs, va);
935 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
936 radeon_emit(cs, 0); /* immediate data */
937 radeon_emit(cs, 0); /* unused */
938 }
939
940 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
941 radeon_emit(cs, op);
942 radeon_emit(cs, va);
943 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
944 radeon_emit(cs, new_fence); /* immediate data */
945 radeon_emit(cs, 0); /* unused */
946 }
947 }
948
949 void
950 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
951 uint32_t ref, uint32_t mask)
952 {
953 assert(op == WAIT_REG_MEM_EQUAL ||
954 op == WAIT_REG_MEM_NOT_EQUAL ||
955 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
956
957 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
958 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
959 radeon_emit(cs, va);
960 radeon_emit(cs, va >> 32);
961 radeon_emit(cs, ref); /* reference value */
962 radeon_emit(cs, mask); /* mask */
963 radeon_emit(cs, 4); /* poll interval */
964 }
965
966 static void
967 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
968 bool is_mec,
969 bool is_gfx9,
970 unsigned cp_coher_cntl)
971 {
972 if (is_mec || is_gfx9) {
973 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
974 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
975 PKT3_SHADER_TYPE_S(is_mec));
976 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
977 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
978 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
979 radeon_emit(cs, 0); /* CP_COHER_BASE */
980 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
981 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
982 } else {
983 /* ACQUIRE_MEM is only required on a compute ring. */
984 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
985 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
986 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
987 radeon_emit(cs, 0); /* CP_COHER_BASE */
988 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
989 }
990 }
991
992 static void
993 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
994 enum chip_class chip_class,
995 uint32_t *flush_cnt,
996 uint64_t flush_va,
997 bool is_mec,
998 enum radv_cmd_flush_bits flush_bits,
999 uint64_t gfx9_eop_bug_va)
1000 {
1001 uint32_t gcr_cntl = 0;
1002 unsigned cb_db_event = 0;
1003
1004 /* We don't need these. */
1005 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
1006
1007 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1008 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1009 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
1010 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1011 * to FORWARD when both L1 and L2 are written out (WB or INV).
1012 */
1013 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1014 }
1015 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
1016 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1017 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1018 /* Writeback and invalidate everything in L2. */
1019 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
1020 S_586_GLM_INV(1) | S_586_GLM_WB(1);
1021 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
1022 /* Writeback but do not invalidate.
1023 * GLM doesn't support WB alone. If WB is set, INV must be set too.
1024 */
1025 gcr_cntl |= S_586_GL2_WB(1) |
1026 S_586_GLM_WB(1) | S_586_GLM_INV(1);
1027 }
1028
1029 /* TODO: Implement this new flag for GFX9+.
1030 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
1031 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
1032 */
1033
1034 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1035 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
1036 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1037 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1038 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1039 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1040 EVENT_INDEX(0));
1041 }
1042
1043 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
1044 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1045 /* Flush HTILE. Will wait for idle later. */
1046 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1047 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1048 EVENT_INDEX(0));
1049 }
1050
1051 /* First flush CB/DB, then L1/L2. */
1052 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1053
1054 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
1055 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1056 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1057 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1058 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1059 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1060 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1061 } else {
1062 assert(0);
1063 }
1064 } else {
1065 /* Wait for graphics shaders to go idle if requested. */
1066 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1067 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1068 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1069 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1070 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1071 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1072 }
1073 }
1074
1075 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1076 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1077 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1078 }
1079
1080 if (cb_db_event) {
1081 /* CB/DB flush and invalidate (or possibly just a wait for a
1082 * meta flush) via RELEASE_MEM.
1083 *
1084 * Combine this with other cache flushes when possible; this
1085 * requires affected shaders to be idle, so do it after the
1086 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1087 * implied).
1088 */
1089 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1090 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1091 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1092 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1093 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1094 assert(G_586_GL2_US(gcr_cntl) == 0);
1095 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1096 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1097 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1098 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1099 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1100
1101 gcr_cntl &= C_586_GLM_WB &
1102 C_586_GLM_INV &
1103 C_586_GLV_INV &
1104 C_586_GL1_INV &
1105 C_586_GL2_INV &
1106 C_586_GL2_WB; /* keep SEQ */
1107
1108 assert(flush_cnt);
1109 (*flush_cnt)++;
1110
1111 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
1112 S_490_GLM_WB(glm_wb) |
1113 S_490_GLM_INV(glm_inv) |
1114 S_490_GLV_INV(glv_inv) |
1115 S_490_GL1_INV(gl1_inv) |
1116 S_490_GL2_INV(gl2_inv) |
1117 S_490_GL2_WB(gl2_wb) |
1118 S_490_SEQ(gcr_seq),
1119 EOP_DST_SEL_MEM,
1120 EOP_DATA_SEL_VALUE_32BIT,
1121 flush_va, *flush_cnt,
1122 gfx9_eop_bug_va);
1123
1124 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1125 *flush_cnt, 0xffffffff);
1126 }
1127
1128 /* VGT state sync */
1129 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1130 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1131 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1132 }
1133
1134 /* Ignore fields that only modify the behavior of other fields. */
1135 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1136 /* Flush caches and wait for the caches to assert idle.
1137 * The cache flush is executed in the ME, but the PFP waits
1138 * for completion.
1139 */
1140 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1141 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1142 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1143 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1144 radeon_emit(cs, 0); /* CP_COHER_BASE */
1145 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1146 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1147 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1148 } else if ((cb_db_event ||
1149 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1150 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1151 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1152 && !is_mec) {
1153 /* We need to ensure that PFP waits as well. */
1154 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1155 radeon_emit(cs, 0);
1156 }
1157
1158 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1159 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1160 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1161 EVENT_INDEX(0));
1162 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1163 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1164 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1165 EVENT_INDEX(0));
1166 }
1167 }
1168
1169 void
1170 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1171 enum chip_class chip_class,
1172 uint32_t *flush_cnt,
1173 uint64_t flush_va,
1174 bool is_mec,
1175 enum radv_cmd_flush_bits flush_bits,
1176 uint64_t gfx9_eop_bug_va)
1177 {
1178 unsigned cp_coher_cntl = 0;
1179 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1180 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1181
1182 if (chip_class >= GFX10) {
1183 /* GFX10 cache flush handling is quite different. */
1184 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1185 is_mec, flush_bits, gfx9_eop_bug_va);
1186 return;
1187 }
1188
1189 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1190 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1191 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1192 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1193
1194 if (chip_class <= GFX8) {
1195 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1196 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1197 S_0085F0_CB0_DEST_BASE_ENA(1) |
1198 S_0085F0_CB1_DEST_BASE_ENA(1) |
1199 S_0085F0_CB2_DEST_BASE_ENA(1) |
1200 S_0085F0_CB3_DEST_BASE_ENA(1) |
1201 S_0085F0_CB4_DEST_BASE_ENA(1) |
1202 S_0085F0_CB5_DEST_BASE_ENA(1) |
1203 S_0085F0_CB6_DEST_BASE_ENA(1) |
1204 S_0085F0_CB7_DEST_BASE_ENA(1);
1205
1206 /* Necessary for DCC */
1207 if (chip_class >= GFX8) {
1208 si_cs_emit_write_event_eop(cs,
1209 chip_class,
1210 is_mec,
1211 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1212 0,
1213 EOP_DST_SEL_MEM,
1214 EOP_DATA_SEL_DISCARD,
1215 0, 0,
1216 gfx9_eop_bug_va);
1217 }
1218 }
1219 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1220 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1221 S_0085F0_DB_DEST_BASE_ENA(1);
1222 }
1223 }
1224
1225 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1226 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1227 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1228 }
1229
1230 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1231 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1232 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1233 }
1234
1235 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1236 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1237 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1238 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1239 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1240 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1241 }
1242
1243 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1244 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1245 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1246 }
1247
1248 if (chip_class == GFX9 && flush_cb_db) {
1249 unsigned cb_db_event, tc_flags;
1250
1251 /* Set the CB/DB flush event. */
1252 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1253
1254 /* These are the only allowed combinations. If you need to
1255 * do multiple operations at once, do them separately.
1256 * All operations that invalidate L2 also seem to invalidate
1257 * metadata. Volatile (VOL) and WC flushes are not listed here.
1258 *
1259 * TC | TC_WB = writeback & invalidate L2 & L1
1260 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1261 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1262 * TC | TC_NC = invalidate L2 for MTYPE == NC
1263 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1264 * TCL1 = invalidate L1
1265 */
1266 tc_flags = EVENT_TC_ACTION_ENA |
1267 EVENT_TC_MD_ACTION_ENA;
1268
1269 /* Ideally flush TC together with CB/DB. */
1270 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1271 /* Writeback and invalidate everything in L2 & L1. */
1272 tc_flags = EVENT_TC_ACTION_ENA |
1273 EVENT_TC_WB_ACTION_ENA;
1274
1275
1276 /* Clear the flags. */
1277 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1278 RADV_CMD_FLAG_WB_L2 |
1279 RADV_CMD_FLAG_INV_VCACHE);
1280 }
1281 assert(flush_cnt);
1282 (*flush_cnt)++;
1283
1284 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1285 EOP_DST_SEL_MEM,
1286 EOP_DATA_SEL_VALUE_32BIT,
1287 flush_va, *flush_cnt,
1288 gfx9_eop_bug_va);
1289 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1290 *flush_cnt, 0xffffffff);
1291 }
1292
1293 /* VGT state sync */
1294 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1295 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1296 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1297 }
1298
1299 /* VGT streamout state sync */
1300 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1301 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1302 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1303 }
1304
1305 /* Make sure ME is idle (it executes most packets) before continuing.
1306 * This prevents read-after-write hazards between PFP and ME.
1307 */
1308 if ((cp_coher_cntl ||
1309 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1310 RADV_CMD_FLAG_INV_VCACHE |
1311 RADV_CMD_FLAG_INV_L2 |
1312 RADV_CMD_FLAG_WB_L2))) &&
1313 !is_mec) {
1314 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1315 radeon_emit(cs, 0);
1316 }
1317
1318 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1319 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1320 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1321 cp_coher_cntl |
1322 S_0085F0_TC_ACTION_ENA(1) |
1323 S_0085F0_TCL1_ACTION_ENA(1) |
1324 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1325 cp_coher_cntl = 0;
1326 } else {
1327 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1328 /* WB = write-back
1329 * NC = apply to non-coherent MTYPEs
1330 * (i.e. MTYPE <= 1, which is what we use everywhere)
1331 *
1332 * WB doesn't work without NC.
1333 */
1334 si_emit_acquire_mem(cs, is_mec,
1335 chip_class == GFX9,
1336 cp_coher_cntl |
1337 S_0301F0_TC_WB_ACTION_ENA(1) |
1338 S_0301F0_TC_NC_ACTION_ENA(1));
1339 cp_coher_cntl = 0;
1340 }
1341 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1342 si_emit_acquire_mem(cs, is_mec,
1343 chip_class == GFX9,
1344 cp_coher_cntl |
1345 S_0085F0_TCL1_ACTION_ENA(1));
1346 cp_coher_cntl = 0;
1347 }
1348 }
1349
1350 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1351 * Therefore, it should be last. Done in PFP.
1352 */
1353 if (cp_coher_cntl)
1354 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1355
1356 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1357 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1358 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1359 EVENT_INDEX(0));
1360 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1361 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1362 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1363 EVENT_INDEX(0));
1364 }
1365 }
1366
1367 void
1368 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1369 {
1370 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1371
1372 if (is_compute)
1373 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1374 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1375 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1376 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1377 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1378 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1379 RADV_CMD_FLAG_VGT_FLUSH |
1380 RADV_CMD_FLAG_START_PIPELINE_STATS |
1381 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1382
1383 if (!cmd_buffer->state.flush_bits)
1384 return;
1385
1386 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1387
1388 si_cs_emit_cache_flush(cmd_buffer->cs,
1389 cmd_buffer->device->physical_device->rad_info.chip_class,
1390 &cmd_buffer->gfx9_fence_idx,
1391 cmd_buffer->gfx9_fence_va,
1392 radv_cmd_buffer_uses_mec(cmd_buffer),
1393 cmd_buffer->state.flush_bits,
1394 cmd_buffer->gfx9_eop_bug_va);
1395
1396
1397 if (unlikely(cmd_buffer->device->trace_bo))
1398 radv_cmd_buffer_trace_emit(cmd_buffer);
1399
1400 /* Clear the caches that have been flushed to avoid syncing too much
1401 * when there is some pending active queries.
1402 */
1403 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1404
1405 cmd_buffer->state.flush_bits = 0;
1406
1407 /* If the driver used a compute shader for resetting a query pool, it
1408 * should be finished at this point.
1409 */
1410 cmd_buffer->pending_reset_query = false;
1411 }
1412
1413 /* sets the CP predication state using a boolean stored at va */
1414 void
1415 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1416 bool draw_visible, uint64_t va)
1417 {
1418 uint32_t op = 0;
1419
1420 if (va) {
1421 op = PRED_OP(PREDICATION_OP_BOOL64);
1422
1423 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1424 * zero, all rendering commands are discarded. Otherwise, they
1425 * are discarded if the value is non zero.
1426 */
1427 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1428 PREDICATION_DRAW_NOT_VISIBLE;
1429 }
1430 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1431 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1432 radeon_emit(cmd_buffer->cs, op);
1433 radeon_emit(cmd_buffer->cs, va);
1434 radeon_emit(cmd_buffer->cs, va >> 32);
1435 } else {
1436 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1437 radeon_emit(cmd_buffer->cs, va);
1438 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1439 }
1440 }
1441
1442 /* Set this if you want the 3D engine to wait until CP DMA is done.
1443 * It should be set on the last CP DMA packet. */
1444 #define CP_DMA_SYNC (1 << 0)
1445
1446 /* Set this if the source data was used as a destination in a previous CP DMA
1447 * packet. It's for preventing a read-after-write (RAW) hazard between two
1448 * CP DMA packets. */
1449 #define CP_DMA_RAW_WAIT (1 << 1)
1450 #define CP_DMA_USE_L2 (1 << 2)
1451 #define CP_DMA_CLEAR (1 << 3)
1452
1453 /* Alignment for optimal performance. */
1454 #define SI_CPDMA_ALIGNMENT 32
1455
1456 /* The max number of bytes that can be copied per packet. */
1457 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1458 {
1459 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1460 S_414_BYTE_COUNT_GFX9(~0u) :
1461 S_414_BYTE_COUNT_GFX6(~0u);
1462
1463 /* make it aligned for optimal performance */
1464 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1465 }
1466
1467 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1468 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1469 * clear value.
1470 */
1471 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1472 uint64_t dst_va, uint64_t src_va,
1473 unsigned size, unsigned flags)
1474 {
1475 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1476 uint32_t header = 0, command = 0;
1477
1478 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1479
1480 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1481 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1482 command |= S_414_BYTE_COUNT_GFX9(size);
1483 else
1484 command |= S_414_BYTE_COUNT_GFX6(size);
1485
1486 /* Sync flags. */
1487 if (flags & CP_DMA_SYNC)
1488 header |= S_411_CP_SYNC(1);
1489 else {
1490 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1491 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1492 else
1493 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1494 }
1495
1496 if (flags & CP_DMA_RAW_WAIT)
1497 command |= S_414_RAW_WAIT(1);
1498
1499 /* Src and dst flags. */
1500 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1501 !(flags & CP_DMA_CLEAR) &&
1502 src_va == dst_va)
1503 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1504 else if (flags & CP_DMA_USE_L2)
1505 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1506
1507 if (flags & CP_DMA_CLEAR)
1508 header |= S_411_SRC_SEL(V_411_DATA);
1509 else if (flags & CP_DMA_USE_L2)
1510 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1511
1512 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1513 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1514 radeon_emit(cs, header);
1515 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1516 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1517 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1518 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1519 radeon_emit(cs, command);
1520 } else {
1521 assert(!(flags & CP_DMA_USE_L2));
1522 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1523 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1524 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1525 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1526 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1527 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1528 radeon_emit(cs, command);
1529 }
1530
1531 /* CP DMA is executed in ME, but index buffers are read by PFP.
1532 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1533 * indices. If we wanted to execute CP DMA in PFP, this packet
1534 * should precede it.
1535 */
1536 if (flags & CP_DMA_SYNC) {
1537 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1538 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1539 radeon_emit(cs, 0);
1540 }
1541
1542 /* CP will see the sync flag and wait for all DMAs to complete. */
1543 cmd_buffer->state.dma_is_busy = false;
1544 }
1545
1546 if (unlikely(cmd_buffer->device->trace_bo))
1547 radv_cmd_buffer_trace_emit(cmd_buffer);
1548 }
1549
1550 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1551 unsigned size)
1552 {
1553 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1554 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1555
1556 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1557 aligned_size, CP_DMA_USE_L2);
1558 }
1559
1560 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1561 uint64_t remaining_size, unsigned *flags)
1562 {
1563
1564 /* Flush the caches for the first copy only.
1565 * Also wait for the previous CP DMA operations.
1566 */
1567 if (cmd_buffer->state.flush_bits) {
1568 si_emit_cache_flush(cmd_buffer);
1569 *flags |= CP_DMA_RAW_WAIT;
1570 }
1571
1572 /* Do the synchronization after the last dma, so that all data
1573 * is written to memory.
1574 */
1575 if (byte_count == remaining_size)
1576 *flags |= CP_DMA_SYNC;
1577 }
1578
1579 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1580 {
1581 uint64_t va;
1582 uint32_t offset;
1583 unsigned dma_flags = 0;
1584 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1585 void *ptr;
1586
1587 assert(size < SI_CPDMA_ALIGNMENT);
1588
1589 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1590
1591 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1592 va += offset;
1593
1594 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1595
1596 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1597 dma_flags);
1598 }
1599
1600 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1601 uint64_t src_va, uint64_t dest_va,
1602 uint64_t size)
1603 {
1604 uint64_t main_src_va, main_dest_va;
1605 uint64_t skipped_size = 0, realign_size = 0;
1606
1607 /* Assume that we are not going to sync after the last DMA operation. */
1608 cmd_buffer->state.dma_is_busy = true;
1609
1610 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1611 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1612 /* If the size is not aligned, we must add a dummy copy at the end
1613 * just to align the internal counter. Otherwise, the DMA engine
1614 * would slow down by an order of magnitude for following copies.
1615 */
1616 if (size % SI_CPDMA_ALIGNMENT)
1617 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1618
1619 /* If the copy begins unaligned, we must start copying from the next
1620 * aligned block and the skipped part should be copied after everything
1621 * else has been copied. Only the src alignment matters, not dst.
1622 */
1623 if (src_va % SI_CPDMA_ALIGNMENT) {
1624 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1625 /* The main part will be skipped if the size is too small. */
1626 skipped_size = MIN2(skipped_size, size);
1627 size -= skipped_size;
1628 }
1629 }
1630 main_src_va = src_va + skipped_size;
1631 main_dest_va = dest_va + skipped_size;
1632
1633 while (size) {
1634 unsigned dma_flags = 0;
1635 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1636
1637 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1638 /* DMA operations via L2 are coherent and faster.
1639 * TODO: GFX7-GFX9 should also support this but it
1640 * requires tests/benchmarks.
1641 */
1642 dma_flags |= CP_DMA_USE_L2;
1643 }
1644
1645 si_cp_dma_prepare(cmd_buffer, byte_count,
1646 size + skipped_size + realign_size,
1647 &dma_flags);
1648
1649 dma_flags &= ~CP_DMA_SYNC;
1650
1651 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1652 byte_count, dma_flags);
1653
1654 size -= byte_count;
1655 main_src_va += byte_count;
1656 main_dest_va += byte_count;
1657 }
1658
1659 if (skipped_size) {
1660 unsigned dma_flags = 0;
1661
1662 si_cp_dma_prepare(cmd_buffer, skipped_size,
1663 size + skipped_size + realign_size,
1664 &dma_flags);
1665
1666 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1667 skipped_size, dma_flags);
1668 }
1669 if (realign_size)
1670 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1671 }
1672
1673 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1674 uint64_t size, unsigned value)
1675 {
1676
1677 if (!size)
1678 return;
1679
1680 assert(va % 4 == 0 && size % 4 == 0);
1681
1682 /* Assume that we are not going to sync after the last DMA operation. */
1683 cmd_buffer->state.dma_is_busy = true;
1684
1685 while (size) {
1686 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1687 unsigned dma_flags = CP_DMA_CLEAR;
1688
1689 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1690 /* DMA operations via L2 are coherent and faster.
1691 * TODO: GFX7-GFX9 should also support this but it
1692 * requires tests/benchmarks.
1693 */
1694 dma_flags |= CP_DMA_USE_L2;
1695 }
1696
1697 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1698
1699 /* Emit the clear packet. */
1700 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1701 dma_flags);
1702
1703 size -= byte_count;
1704 va += byte_count;
1705 }
1706 }
1707
1708 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1709 {
1710 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1711 return;
1712
1713 if (!cmd_buffer->state.dma_is_busy)
1714 return;
1715
1716 /* Issue a dummy DMA that copies zero bytes.
1717 *
1718 * The DMA engine will see that there's no work to do and skip this
1719 * DMA request, however, the CP will see the sync flag and still wait
1720 * for all DMAs to complete.
1721 */
1722 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1723
1724 cmd_buffer->state.dma_is_busy = false;
1725 }
1726
1727 /* For MSAA sample positions. */
1728 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1729 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1730 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1731 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1732 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1733
1734 /* For obtaining location coordinates from registers */
1735 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1736 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1737 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1738 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1739
1740 /* 1x MSAA */
1741 static const uint32_t sample_locs_1x =
1742 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1743 static const unsigned max_dist_1x = 0;
1744 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1745
1746 /* 2xMSAA */
1747 static const uint32_t sample_locs_2x =
1748 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1749 static const unsigned max_dist_2x = 4;
1750 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1751
1752 /* 4xMSAA */
1753 static const uint32_t sample_locs_4x =
1754 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1755 static const unsigned max_dist_4x = 6;
1756 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1757
1758 /* 8xMSAA */
1759 static const uint32_t sample_locs_8x[] = {
1760 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1761 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1762 /* The following are unused by hardware, but we emit them to IBs
1763 * instead of multiple SET_CONTEXT_REG packets. */
1764 0,
1765 0,
1766 };
1767 static const unsigned max_dist_8x = 7;
1768 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1769
1770 unsigned radv_get_default_max_sample_dist(int log_samples)
1771 {
1772 unsigned max_dist[] = {
1773 max_dist_1x,
1774 max_dist_2x,
1775 max_dist_4x,
1776 max_dist_8x,
1777 };
1778 return max_dist[log_samples];
1779 }
1780
1781 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1782 {
1783 switch (nr_samples) {
1784 default:
1785 case 1:
1786 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1787 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1788 radeon_emit(cs, centroid_priority_1x >> 32);
1789 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1790 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1791 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1792 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1793 break;
1794 case 2:
1795 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1796 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1797 radeon_emit(cs, centroid_priority_2x >> 32);
1798 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1799 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1800 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1801 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1802 break;
1803 case 4:
1804 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1805 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1806 radeon_emit(cs, centroid_priority_4x >> 32);
1807 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1808 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1809 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1810 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1811 break;
1812 case 8:
1813 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1814 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1815 radeon_emit(cs, centroid_priority_8x >> 32);
1816 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1817 radeon_emit_array(cs, sample_locs_8x, 4);
1818 radeon_emit_array(cs, sample_locs_8x, 4);
1819 radeon_emit_array(cs, sample_locs_8x, 4);
1820 radeon_emit_array(cs, sample_locs_8x, 2);
1821 break;
1822 }
1823 }
1824
1825 static void radv_get_sample_position(struct radv_device *device,
1826 unsigned sample_count,
1827 unsigned sample_index, float *out_value)
1828 {
1829 const uint32_t *sample_locs;
1830
1831 switch (sample_count) {
1832 case 1:
1833 default:
1834 sample_locs = &sample_locs_1x;
1835 break;
1836 case 2:
1837 sample_locs = &sample_locs_2x;
1838 break;
1839 case 4:
1840 sample_locs = &sample_locs_4x;
1841 break;
1842 case 8:
1843 sample_locs = sample_locs_8x;
1844 break;
1845 }
1846
1847 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1848 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1849 }
1850
1851 void radv_device_init_msaa(struct radv_device *device)
1852 {
1853 int i;
1854
1855 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1856
1857 for (i = 0; i < 2; i++)
1858 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1859 for (i = 0; i < 4; i++)
1860 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1861 for (i = 0; i < 8; i++)
1862 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1863 }