2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
6 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 /* command buffer handling for AMD GCN */
30 #include "radv_private.h"
31 #include "radv_shader.h"
34 #include "radv_util.h"
37 si_write_harvested_raster_configs(struct radv_physical_device
*physical_device
,
38 struct radeon_cmdbuf
*cs
,
39 unsigned raster_config
,
40 unsigned raster_config_1
)
42 unsigned num_se
= MAX2(physical_device
->rad_info
.max_se
, 1);
43 unsigned raster_config_se
[4];
46 ac_get_harvested_configs(&physical_device
->rad_info
,
51 for (se
= 0; se
< num_se
; se
++) {
52 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
53 if (physical_device
->rad_info
.chip_class
< GFX7
)
54 radeon_set_config_reg(cs
, R_00802C_GRBM_GFX_INDEX
,
55 S_00802C_SE_INDEX(se
) |
56 S_00802C_SH_BROADCAST_WRITES(1) |
57 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
60 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
61 S_030800_INSTANCE_BROADCAST_WRITES(1));
62 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
65 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
66 if (physical_device
->rad_info
.chip_class
< GFX7
)
67 radeon_set_config_reg(cs
, R_00802C_GRBM_GFX_INDEX
,
68 S_00802C_SE_BROADCAST_WRITES(1) |
69 S_00802C_SH_BROADCAST_WRITES(1) |
70 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
73 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
74 S_030800_INSTANCE_BROADCAST_WRITES(1));
76 if (physical_device
->rad_info
.chip_class
>= GFX7
)
77 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
81 si_emit_compute(struct radv_physical_device
*physical_device
,
82 struct radeon_cmdbuf
*cs
)
84 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
89 radeon_set_sh_reg_seq(cs
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
, 2);
90 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
91 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
92 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
95 if (physical_device
->rad_info
.chip_class
>= GFX7
) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs
,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
99 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
105 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
106 radeon_set_uconfig_reg(cs
, R_0301EC_CP_COHER_START_DELAY
,
107 physical_device
->rad_info
.chip_class
>= GFX10
? 0x20 : 0);
110 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
111 radeon_set_sh_reg(cs
, R_00B890_COMPUTE_USER_ACCUM_0
, 0);
112 radeon_set_sh_reg(cs
, R_00B894_COMPUTE_USER_ACCUM_1
, 0);
113 radeon_set_sh_reg(cs
, R_00B898_COMPUTE_USER_ACCUM_2
, 0);
114 radeon_set_sh_reg(cs
, R_00B89C_COMPUTE_USER_ACCUM_3
, 0);
115 radeon_set_sh_reg(cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, 0);
116 radeon_set_sh_reg(cs
, R_00B9F4_COMPUTE_DISPATCH_TUNNEL
, 0);
119 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
120 * and is now per pipe, so it should be handled in the
121 * kernel if we want to use something other than the default value,
122 * which is now 0x22f.
124 if (physical_device
->rad_info
.chip_class
<= GFX6
) {
125 /* XXX: This should be:
126 * (number of compute units) * 4 * (waves per simd) - 1 */
128 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
129 0x190 /* Default value */);
133 /* 12.4 fixed-point */
134 static unsigned radv_pack_float_12p4(float x
)
137 x
>= 4096 ? 0xffff : x
* 16;
141 si_set_raster_config(struct radv_physical_device
*physical_device
,
142 struct radeon_cmdbuf
*cs
)
144 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
145 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
146 unsigned raster_config
, raster_config_1
;
148 ac_get_raster_config(&physical_device
->rad_info
,
150 &raster_config_1
, NULL
);
152 /* Always use the default config when all backends are enabled
153 * (or when we failed to determine the enabled backends).
155 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
156 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
,
158 if (physical_device
->rad_info
.chip_class
>= GFX7
)
159 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
,
162 si_write_harvested_raster_configs(physical_device
, cs
,
169 si_emit_graphics(struct radv_device
*device
,
170 struct radeon_cmdbuf
*cs
)
172 struct radv_physical_device
*physical_device
= device
->physical_device
;
174 bool has_clear_state
= physical_device
->rad_info
.has_clear_state
;
177 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
178 radeon_emit(cs
, CC0_UPDATE_LOAD_ENABLES(1));
179 radeon_emit(cs
, CC1_UPDATE_SHADOW_ENABLES(1));
181 if (has_clear_state
) {
182 radeon_emit(cs
, PKT3(PKT3_CLEAR_STATE
, 0, 0));
186 if (physical_device
->rad_info
.chip_class
<= GFX8
)
187 si_set_raster_config(physical_device
, cs
);
189 radeon_set_context_reg(cs
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
190 if (!has_clear_state
)
191 radeon_set_context_reg(cs
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
193 /* FIXME calculate these values somehow ??? */
194 if (physical_device
->rad_info
.chip_class
<= GFX8
) {
195 radeon_set_context_reg(cs
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
196 radeon_set_context_reg(cs
, R_028A58_VGT_ES_PER_GS
, 0x40);
199 if (!has_clear_state
) {
200 radeon_set_context_reg(cs
, R_028A5C_VGT_GS_PER_VS
, 0x2);
201 radeon_set_context_reg(cs
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
202 radeon_set_context_reg(cs
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
205 if (physical_device
->rad_info
.chip_class
<= GFX9
)
206 radeon_set_context_reg(cs
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
207 if (!has_clear_state
)
208 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
209 if (physical_device
->rad_info
.chip_class
< GFX7
)
210 radeon_set_config_reg(cs
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
211 S_008A14_CLIP_VTX_REORDER_ENA(1));
213 if (!has_clear_state
)
214 radeon_set_context_reg(cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
216 /* CLEAR_STATE doesn't clear these correctly on certain generations.
217 * I don't know why. Deduced by trial and error.
219 if (physical_device
->rad_info
.chip_class
<= GFX7
|| !has_clear_state
) {
220 radeon_set_context_reg(cs
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
221 radeon_set_context_reg(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
,
222 S_028204_WINDOW_OFFSET_DISABLE(1));
223 radeon_set_context_reg(cs
, R_028240_PA_SC_GENERIC_SCISSOR_TL
,
224 S_028240_WINDOW_OFFSET_DISABLE(1));
225 radeon_set_context_reg(cs
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
226 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
227 radeon_set_context_reg(cs
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
228 radeon_set_context_reg(cs
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
229 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
232 if (!has_clear_state
) {
233 for (i
= 0; i
< 16; i
++) {
234 radeon_set_context_reg(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+ i
*8, 0);
235 radeon_set_context_reg(cs
, R_0282D4_PA_SC_VPORT_ZMAX_0
+ i
*8, fui(1.0));
239 if (!has_clear_state
) {
240 radeon_set_context_reg(cs
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
241 radeon_set_context_reg(cs
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
242 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
243 radeon_set_context_reg(cs
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
244 radeon_set_context_reg(cs
, R_028820_PA_CL_NANINF_CNTL
, 0);
245 radeon_set_context_reg(cs
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
246 radeon_set_context_reg(cs
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
247 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
250 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
,
251 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
252 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
254 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
255 radeon_set_context_reg(cs
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
256 radeon_set_uconfig_reg(cs
, R_030964_GE_MAX_VTX_INDX
, ~0);
257 radeon_set_uconfig_reg(cs
, R_030924_GE_MIN_VTX_INDX
, 0);
258 radeon_set_uconfig_reg(cs
, R_030928_GE_INDX_OFFSET
, 0);
259 radeon_set_uconfig_reg(cs
, R_03097C_GE_STEREO_CNTL
, 0);
260 radeon_set_uconfig_reg(cs
, R_030988_GE_USER_VGPR_EN
, 0);
261 } else if (physical_device
->rad_info
.chip_class
== GFX9
) {
262 radeon_set_uconfig_reg(cs
, R_030920_VGT_MAX_VTX_INDX
, ~0);
263 radeon_set_uconfig_reg(cs
, R_030924_VGT_MIN_VTX_INDX
, 0);
264 radeon_set_uconfig_reg(cs
, R_030928_VGT_INDX_OFFSET
, 0);
266 /* These registers, when written, also overwrite the
267 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
268 * them. It would be an issue if there was another UMD
271 radeon_set_context_reg(cs
, R_028400_VGT_MAX_VTX_INDX
, ~0);
272 radeon_set_context_reg(cs
, R_028404_VGT_MIN_VTX_INDX
, 0);
273 radeon_set_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, 0);
276 if (physical_device
->rad_info
.chip_class
>= GFX7
) {
277 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
278 /* Logical CUs 16 - 31 */
279 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
,
280 3, S_00B404_CU_EN(0xffff));
281 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
,
282 3, S_00B104_CU_EN(0xffff));
283 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
,
284 3, S_00B004_CU_EN(0xffff));
287 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
288 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
289 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
291 radeon_set_sh_reg(cs
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
292 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
293 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
294 S_00B41C_WAVE_LIMIT(0x3F));
295 radeon_set_sh_reg(cs
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
296 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
297 /* If this is 0, Bonaire can hang even if GS isn't being used.
298 * Other chips are unaffected. These are suboptimal values,
299 * but we don't use on-chip GS.
301 radeon_set_context_reg(cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
302 S_028A44_ES_VERTS_PER_SUBGRP(64) |
303 S_028A44_GS_PRIMS_PER_SUBGRP(4));
306 /* Compute LATE_ALLOC_VS.LIMIT. */
307 unsigned num_cu_per_sh
= physical_device
->rad_info
.min_good_cu_per_sa
;
308 unsigned late_alloc_wave64
= 0; /* The limit is per SA. */
309 unsigned late_alloc_wave64_gs
= 0;
310 unsigned cu_mask_vs
= 0xffff;
311 unsigned cu_mask_gs
= 0xffff;
313 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
314 /* For Wave32, the hw will launch twice the number of late
315 * alloc waves, so 1 == 2x wave32.
317 if (!physical_device
->rad_info
.use_late_alloc
) {
318 late_alloc_wave64
= 0;
319 } else if (num_cu_per_sh
<= 6) {
320 late_alloc_wave64
= num_cu_per_sh
- 2;
322 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
324 /* CU2 & CU3 disabled because of the dual CU design */
326 cu_mask_gs
= 0xfff3; /* NGG only */
329 late_alloc_wave64_gs
= late_alloc_wave64
;
331 /* Don't use late alloc for NGG on Navi14 due to a hw
332 * bug. If NGG is never used, enable all CUs.
334 if (!physical_device
->use_ngg
||
335 physical_device
->rad_info
.family
== CHIP_NAVI14
) {
336 late_alloc_wave64_gs
= 0;
340 /* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
341 if (physical_device
->rad_info
.chip_class
== GFX10
)
342 late_alloc_wave64_gs
= MIN2(late_alloc_wave64_gs
, 64);
344 if (!physical_device
->rad_info
.use_late_alloc
) {
345 late_alloc_wave64
= 0;
346 } else if (num_cu_per_sh
<= 4) {
347 /* Too few available compute units per SA.
348 * Disallowing VS to run on one CU could hurt
349 * us more than late VS allocation would help.
351 * 2 is the highest safe number that allows us
352 * to keep all CUs enabled.
354 late_alloc_wave64
= 2;
356 /* This is a good initial value, allowing 1
357 * late_alloc wave per SIMD on num_cu - 2.
359 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
362 if (late_alloc_wave64
> 2)
363 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
366 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
367 3, S_00B118_CU_EN(cu_mask_vs
) |
368 S_00B118_WAVE_LIMIT(0x3F));
369 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
370 S_00B11C_LIMIT(late_alloc_wave64
));
372 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
373 3, S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
375 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
376 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
377 3, S_00B204_CU_EN(0xffff) |
378 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64_gs
));
381 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
382 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
385 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
386 /* Break up a pixel wave if it contains deallocs for more than
387 * half the parameter cache.
389 * To avoid a deadlock where pixel waves aren't launched
390 * because they're waiting for more pixels while the frontend
391 * is stuck waiting for PC space, the maximum allowed value is
392 * the size of the PC minus the largest possible allocation for
393 * a single primitive shader subgroup.
395 radeon_set_context_reg(cs
, R_028C50_PA_SC_NGG_MODE_CNTL
,
396 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
397 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
399 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
400 unsigned meta_write_policy
, meta_read_policy
;
402 /* TODO: investigate whether LRU improves performance on other chips too */
403 if (physical_device
->rad_info
.num_render_backends
<= 4) {
404 meta_write_policy
= V_02807C_CACHE_LRU_WR
; /* cache writes */
405 meta_read_policy
= V_02807C_CACHE_LRU_RD
; /* cache reads */
407 meta_write_policy
= V_02807C_CACHE_STREAM_WR
; /* write combine */
408 meta_read_policy
= V_02807C_CACHE_NOA_RD
; /* don't cache reads */
411 radeon_set_context_reg(cs
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
412 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
413 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
414 S_02807C_HTILE_WR_POLICY(meta_write_policy
) |
415 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
416 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
417 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
418 S_02807C_HTILE_RD_POLICY(meta_read_policy
));
420 radeon_set_context_reg(cs
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
421 S_028410_CMASK_WR_POLICY(meta_write_policy
) |
422 S_028410_FMASK_WR_POLICY(meta_write_policy
) |
423 S_028410_DCC_WR_POLICY(meta_write_policy
) |
424 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
425 S_028410_CMASK_RD_POLICY(meta_read_policy
) |
426 S_028410_FMASK_RD_POLICY(meta_read_policy
) |
427 S_028410_DCC_RD_POLICY(meta_read_policy
) |
428 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
429 radeon_set_context_reg(cs
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
431 radeon_set_sh_reg(cs
, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0
, 0);
432 radeon_set_sh_reg(cs
, R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1
, 0);
433 radeon_set_sh_reg(cs
, R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2
, 0);
434 radeon_set_sh_reg(cs
, R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3
, 0);
435 radeon_set_sh_reg(cs
, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0
, 0);
436 radeon_set_sh_reg(cs
, R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1
, 0);
437 radeon_set_sh_reg(cs
, R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2
, 0);
438 radeon_set_sh_reg(cs
, R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3
, 0);
439 radeon_set_sh_reg(cs
, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0
, 0);
440 radeon_set_sh_reg(cs
, R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1
, 0);
441 radeon_set_sh_reg(cs
, R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2
, 0);
442 radeon_set_sh_reg(cs
, R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3
, 0);
443 radeon_set_sh_reg(cs
, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0
, 0);
444 radeon_set_sh_reg(cs
, R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1
, 0);
445 radeon_set_sh_reg(cs
, R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2
, 0);
446 radeon_set_sh_reg(cs
, R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3
, 0);
448 radeon_set_sh_reg(cs
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
449 S_00B0C0_SOFT_GROUPING_EN(1) |
450 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
451 radeon_set_sh_reg(cs
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
453 if (physical_device
->rad_info
.chip_class
>= GFX10_3
) {
454 radeon_set_context_reg(cs
, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103
, 0xff);
455 radeon_set_context_reg(cs
, 0x28848, 1 << 9); /* This fixes sample shading. */
458 if (physical_device
->rad_info
.chip_class
== GFX10
) {
459 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
460 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
461 radeon_emit(cs
, EVENT_TYPE(V_028A90_SQ_NON_EVENT
) | EVENT_INDEX(0));
464 /* TODO: For culling, replace 128 with 256. */
465 radeon_set_uconfig_reg(cs
, R_030980_GE_PC_ALLOC
,
466 S_030980_OVERSUB_EN(physical_device
->rad_info
.use_late_alloc
) |
467 S_030980_NUM_PC_LINES(128 * physical_device
->rad_info
.max_se
- 1));
470 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
471 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
472 S_028B50_ACCUM_ISOLINE(40) |
473 S_028B50_ACCUM_TRI(30) |
474 S_028B50_ACCUM_QUAD(24) |
475 S_028B50_DONUT_SPLIT(24) |
476 S_028B50_TRAP_SPLIT(6));
477 } else if (physical_device
->rad_info
.chip_class
>= GFX8
) {
478 uint32_t vgt_tess_distribution
;
480 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) |
481 S_028B50_ACCUM_TRI(11) |
482 S_028B50_ACCUM_QUAD(11) |
483 S_028B50_DONUT_SPLIT(16);
485 if (physical_device
->rad_info
.family
== CHIP_FIJI
||
486 physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
487 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
489 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
490 vgt_tess_distribution
);
491 } else if (!has_clear_state
) {
492 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
493 radeon_set_context_reg(cs
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
496 if (device
->border_color_data
.bo
) {
497 uint64_t border_color_va
= radv_buffer_get_va(device
->border_color_data
.bo
);
499 radeon_set_context_reg(cs
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
500 if (physical_device
->rad_info
.chip_class
>= GFX7
) {
501 radeon_set_context_reg(cs
, R_028084_TA_BC_BASE_ADDR_HI
,
502 S_028084_ADDRESS(border_color_va
>> 40));
506 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
507 radeon_set_context_reg(cs
, R_028C48_PA_SC_BINNER_CNTL_1
,
508 S_028C48_MAX_ALLOC_COUNT(physical_device
->rad_info
.pbb_max_alloc_count
- 1) |
509 S_028C48_MAX_PRIM_PER_BATCH(1023));
510 radeon_set_context_reg(cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
511 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
512 radeon_set_uconfig_reg(cs
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
515 unsigned tmp
= (unsigned)(1.0 * 8.0);
516 radeon_set_context_reg_seq(cs
, R_028A00_PA_SU_POINT_SIZE
, 1);
517 radeon_emit(cs
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
518 radeon_set_context_reg_seq(cs
, R_028A04_PA_SU_POINT_MINMAX
, 1);
519 radeon_emit(cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
520 S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875/2)));
522 if (!has_clear_state
) {
523 radeon_set_context_reg(cs
, R_028004_DB_COUNT_CONTROL
,
524 S_028004_ZPASS_INCREMENT_DISABLE(1));
527 /* Enable the Polaris small primitive filter control.
528 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
529 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
530 * and AMDVLK doesn't have a workaround as well.
532 if (physical_device
->rad_info
.family
>= CHIP_POLARIS10
) {
533 unsigned small_prim_filter_cntl
=
534 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
535 /* Workaround for a hw line bug. */
536 S_028830_LINE_FILTER_DISABLE(physical_device
->rad_info
.family
<= CHIP_POLARIS12
);
538 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
539 small_prim_filter_cntl
);
542 radeon_set_context_reg(cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
543 S_0286D4_FLAT_SHADE_ENA(1) |
544 S_0286D4_PNT_SPRITE_ENA(1) |
545 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
546 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
547 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
548 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
549 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
551 radeon_set_context_reg(cs
, R_028BE4_PA_SU_VTX_CNTL
,
552 S_028BE4_PIX_CENTER(1) |
553 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
554 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
556 radeon_set_context_reg(cs
, R_028818_PA_CL_VTE_CNTL
,
557 S_028818_VTX_W0_FMT(1) |
558 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
559 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
560 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
562 si_emit_compute(physical_device
, cs
);
566 cik_create_gfx_config(struct radv_device
*device
)
568 struct radeon_cmdbuf
*cs
= device
->ws
->cs_create(device
->ws
, RING_GFX
);
572 si_emit_graphics(device
, cs
);
574 while (cs
->cdw
& 7) {
575 if (device
->physical_device
->rad_info
.gfx_ib_pad_with_type2
)
576 radeon_emit(cs
, PKT2_NOP_PAD
);
578 radeon_emit(cs
, PKT3_NOP_PAD
);
581 device
->gfx_init
= device
->ws
->buffer_create(device
->ws
,
584 RADEON_FLAG_CPU_ACCESS
|
585 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
586 RADEON_FLAG_READ_ONLY
|
588 RADV_BO_PRIORITY_CS
);
589 if (!device
->gfx_init
)
592 void *map
= device
->ws
->buffer_map(device
->gfx_init
);
594 device
->ws
->buffer_destroy(device
->gfx_init
);
595 device
->gfx_init
= NULL
;
598 memcpy(map
, cs
->buf
, cs
->cdw
* 4);
600 device
->ws
->buffer_unmap(device
->gfx_init
);
601 device
->gfx_init_size_dw
= cs
->cdw
;
603 device
->ws
->cs_destroy(cs
);
607 get_viewport_xform(const VkViewport
*viewport
,
608 float scale
[3], float translate
[3])
610 float x
= viewport
->x
;
611 float y
= viewport
->y
;
612 float half_width
= 0.5f
* viewport
->width
;
613 float half_height
= 0.5f
* viewport
->height
;
614 double n
= viewport
->minDepth
;
615 double f
= viewport
->maxDepth
;
617 scale
[0] = half_width
;
618 translate
[0] = half_width
+ x
;
619 scale
[1] = half_height
;
620 translate
[1] = half_height
+ y
;
627 si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
628 int count
, const VkViewport
*viewports
)
633 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
634 first_vp
* 4 * 6, count
* 6);
636 for (i
= 0; i
< count
; i
++) {
637 float scale
[3], translate
[3];
640 get_viewport_xform(&viewports
[i
], scale
, translate
);
641 radeon_emit(cs
, fui(scale
[0]));
642 radeon_emit(cs
, fui(translate
[0]));
643 radeon_emit(cs
, fui(scale
[1]));
644 radeon_emit(cs
, fui(translate
[1]));
645 radeon_emit(cs
, fui(scale
[2]));
646 radeon_emit(cs
, fui(translate
[2]));
649 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
650 first_vp
* 4 * 2, count
* 2);
651 for (i
= 0; i
< count
; i
++) {
652 float zmin
= MIN2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
653 float zmax
= MAX2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
654 radeon_emit(cs
, fui(zmin
));
655 radeon_emit(cs
, fui(zmax
));
659 static VkRect2D
si_scissor_from_viewport(const VkViewport
*viewport
)
661 float scale
[3], translate
[3];
664 get_viewport_xform(viewport
, scale
, translate
);
666 rect
.offset
.x
= translate
[0] - fabsf(scale
[0]);
667 rect
.offset
.y
= translate
[1] - fabsf(scale
[1]);
668 rect
.extent
.width
= ceilf(translate
[0] + fabsf(scale
[0])) - rect
.offset
.x
;
669 rect
.extent
.height
= ceilf(translate
[1] + fabsf(scale
[1])) - rect
.offset
.y
;
674 static VkRect2D
si_intersect_scissor(const VkRect2D
*a
, const VkRect2D
*b
) {
676 ret
.offset
.x
= MAX2(a
->offset
.x
, b
->offset
.x
);
677 ret
.offset
.y
= MAX2(a
->offset
.y
, b
->offset
.y
);
678 ret
.extent
.width
= MIN2(a
->offset
.x
+ a
->extent
.width
,
679 b
->offset
.x
+ b
->extent
.width
) - ret
.offset
.x
;
680 ret
.extent
.height
= MIN2(a
->offset
.y
+ a
->extent
.height
,
681 b
->offset
.y
+ b
->extent
.height
) - ret
.offset
.y
;
686 si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
687 int count
, const VkRect2D
*scissors
,
688 const VkViewport
*viewports
, bool can_use_guardband
)
691 float scale
[3], translate
[3], guardband_x
= INFINITY
, guardband_y
= INFINITY
;
692 const float max_range
= 32767.0f
;
696 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ first
* 4 * 2, count
* 2);
697 for (i
= 0; i
< count
; i
++) {
698 VkRect2D viewport_scissor
= si_scissor_from_viewport(viewports
+ i
);
699 VkRect2D scissor
= si_intersect_scissor(&scissors
[i
], &viewport_scissor
);
701 get_viewport_xform(viewports
+ i
, scale
, translate
);
702 scale
[0] = fabsf(scale
[0]);
703 scale
[1] = fabsf(scale
[1]);
710 guardband_x
= MIN2(guardband_x
, (max_range
- fabsf(translate
[0])) / scale
[0]);
711 guardband_y
= MIN2(guardband_y
, (max_range
- fabsf(translate
[1])) / scale
[1]);
713 radeon_emit(cs
, S_028250_TL_X(scissor
.offset
.x
) |
714 S_028250_TL_Y(scissor
.offset
.y
) |
715 S_028250_WINDOW_OFFSET_DISABLE(1));
716 radeon_emit(cs
, S_028254_BR_X(scissor
.offset
.x
+ scissor
.extent
.width
) |
717 S_028254_BR_Y(scissor
.offset
.y
+ scissor
.extent
.height
));
719 if (!can_use_guardband
) {
724 radeon_set_context_reg_seq(cs
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
725 radeon_emit(cs
, fui(guardband_y
));
726 radeon_emit(cs
, fui(1.0));
727 radeon_emit(cs
, fui(guardband_x
));
728 radeon_emit(cs
, fui(1.0));
731 static inline unsigned
732 radv_prims_for_vertices(struct radv_prim_vertex_count
*info
, unsigned num
)
743 return 1 + ((num
- info
->min
) / info
->incr
);
746 static const struct radv_prim_vertex_count prim_size_table
[] = {
747 [V_008958_DI_PT_NONE
] = {0, 0},
748 [V_008958_DI_PT_POINTLIST
] = {1, 1},
749 [V_008958_DI_PT_LINELIST
] = {2, 2},
750 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
751 [V_008958_DI_PT_TRILIST
] = {3, 3},
752 [V_008958_DI_PT_TRIFAN
] = {3, 1},
753 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
754 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
755 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
756 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
757 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
758 [V_008958_DI_PT_RECTLIST
] = {3, 3},
759 [V_008958_DI_PT_LINELOOP
] = {2, 1},
760 [V_008958_DI_PT_POLYGON
] = {3, 1},
761 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
765 si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
766 bool instanced_draw
, bool indirect_draw
,
767 bool count_from_stream_output
,
768 uint32_t draw_vertex_count
,
771 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
772 enum radeon_family family
= cmd_buffer
->device
->physical_device
->rad_info
.family
;
773 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
774 const unsigned max_primgroup_in_wave
= 2;
775 /* SWITCH_ON_EOP(0) is always preferable. */
776 bool wd_switch_on_eop
= false;
777 bool ia_switch_on_eop
= false;
778 bool ia_switch_on_eoi
= false;
779 bool partial_vs_wave
= false;
780 bool partial_es_wave
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.partial_es_wave
;
781 bool multi_instances_smaller_than_primgroup
;
782 struct radv_prim_vertex_count prim_vertex_count
= prim_size_table
[topology
];
784 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
)) {
785 if (topology
== V_008958_DI_PT_PATCH
) {
786 prim_vertex_count
.min
= cmd_buffer
->state
.pipeline
->graphics
.tess_patch_control_points
;
787 prim_vertex_count
.incr
= 1;
791 multi_instances_smaller_than_primgroup
= indirect_draw
;
792 if (!multi_instances_smaller_than_primgroup
&& instanced_draw
) {
793 uint32_t num_prims
= radv_prims_for_vertices(&prim_vertex_count
, draw_vertex_count
);
794 if (num_prims
< cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.primgroup_size
)
795 multi_instances_smaller_than_primgroup
= true;
798 ia_switch_on_eoi
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.ia_switch_on_eoi
;
799 partial_vs_wave
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.partial_vs_wave
;
801 if (chip_class
>= GFX7
) {
802 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
803 * 4 shader engines. Set 1 to pass the assertion below.
804 * The other cases are hardware requirements. */
805 if (cmd_buffer
->device
->physical_device
->rad_info
.max_se
< 4 ||
806 topology
== V_008958_DI_PT_POLYGON
||
807 topology
== V_008958_DI_PT_LINELOOP
||
808 topology
== V_008958_DI_PT_TRIFAN
||
809 topology
== V_008958_DI_PT_TRISTRIP_ADJ
||
810 (cmd_buffer
->state
.pipeline
->graphics
.prim_restart_enable
&&
811 (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
812 (topology
!= V_008958_DI_PT_POINTLIST
&&
813 topology
!= V_008958_DI_PT_LINESTRIP
))))
814 wd_switch_on_eop
= true;
816 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
817 * We don't know that for indirect drawing, so treat it as
818 * always problematic. */
819 if (family
== CHIP_HAWAII
&&
820 (instanced_draw
|| indirect_draw
))
821 wd_switch_on_eop
= true;
823 /* Performance recommendation for 4 SE Gfx7-8 parts if
824 * instances are smaller than a primgroup.
825 * Assume indirect draws always use small instances.
826 * This is needed for good VS wave utilization.
828 if (chip_class
<= GFX8
&&
830 multi_instances_smaller_than_primgroup
)
831 wd_switch_on_eop
= true;
833 /* Required on GFX7 and later. */
834 if (info
->max_se
> 2 && !wd_switch_on_eop
)
835 ia_switch_on_eoi
= true;
837 /* Required by Hawaii and, for some special cases, by GFX8. */
838 if (ia_switch_on_eoi
&&
839 (family
== CHIP_HAWAII
||
840 (chip_class
== GFX8
&&
841 /* max primgroup in wave is always 2 - leave this for documentation */
842 (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
) || max_primgroup_in_wave
!= 2))))
843 partial_vs_wave
= true;
845 /* Instancing bug on Bonaire. */
846 if (family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
847 (instanced_draw
|| indirect_draw
))
848 partial_vs_wave
= true;
850 /* Hardware requirement when drawing primitives from a stream
853 if (count_from_stream_output
)
854 wd_switch_on_eop
= true;
856 /* If the WD switch is false, the IA switch must be false too. */
857 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
859 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
860 if (chip_class
<= GFX8
&& ia_switch_on_eoi
)
861 partial_es_wave
= true;
863 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
)) {
864 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
865 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
866 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
868 if (family
== CHIP_HAWAII
&& ia_switch_on_eoi
) {
869 bool set_vgt_flush
= indirect_draw
;
870 if (!set_vgt_flush
&& instanced_draw
) {
871 uint32_t num_prims
= radv_prims_for_vertices(&prim_vertex_count
, draw_vertex_count
);
873 set_vgt_flush
= true;
876 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
880 /* Workaround for a VGT hang when strip primitive types are used with
883 if (cmd_buffer
->state
.pipeline
->graphics
.prim_restart_enable
&&
884 (topology
== V_008958_DI_PT_LINESTRIP
||
885 topology
== V_008958_DI_PT_TRISTRIP
||
886 topology
== V_008958_DI_PT_LINESTRIP_ADJ
||
887 topology
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
888 partial_vs_wave
= true;
891 return cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.base
|
892 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
893 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
894 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
895 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
896 S_028AA8_WD_SWITCH_ON_EOP(chip_class
>= GFX7
? wd_switch_on_eop
: 0);
900 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
901 enum chip_class chip_class
,
903 unsigned event
, unsigned event_flags
,
904 unsigned dst_sel
, unsigned data_sel
,
907 uint64_t gfx9_eop_bug_va
)
909 unsigned op
= EVENT_TYPE(event
) |
910 EVENT_INDEX(event
== V_028A90_CS_DONE
||
911 event
== V_028A90_PS_DONE
? 6 : 5) |
913 unsigned is_gfx8_mec
= is_mec
&& chip_class
< GFX9
;
914 unsigned sel
= EOP_DST_SEL(dst_sel
) |
915 EOP_DATA_SEL(data_sel
);
917 /* Wait for write confirmation before writing data, but don't send
919 if (data_sel
!= EOP_DATA_SEL_DISCARD
)
920 sel
|= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
);
922 if (chip_class
>= GFX9
|| is_gfx8_mec
) {
923 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
924 * counters) must immediately precede every timestamp event to
925 * prevent a GPU hang on GFX9.
927 if (chip_class
== GFX9
&& !is_mec
) {
928 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
929 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
930 radeon_emit(cs
, gfx9_eop_bug_va
);
931 radeon_emit(cs
, gfx9_eop_bug_va
>> 32);
934 radeon_emit(cs
, PKT3(PKT3_RELEASE_MEM
, is_gfx8_mec
? 5 : 6, false));
936 radeon_emit(cs
, sel
);
937 radeon_emit(cs
, va
); /* address lo */
938 radeon_emit(cs
, va
>> 32); /* address hi */
939 radeon_emit(cs
, new_fence
); /* immediate data lo */
940 radeon_emit(cs
, 0); /* immediate data hi */
942 radeon_emit(cs
, 0); /* unused */
944 if (chip_class
== GFX7
||
945 chip_class
== GFX8
) {
946 /* Two EOP events are required to make all engines go idle
947 * (and optional cache flushes executed) before the timestamp
950 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, false));
953 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
954 radeon_emit(cs
, 0); /* immediate data */
955 radeon_emit(cs
, 0); /* unused */
958 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, false));
961 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
962 radeon_emit(cs
, new_fence
); /* immediate data */
963 radeon_emit(cs
, 0); /* unused */
968 radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
969 uint32_t ref
, uint32_t mask
)
971 assert(op
== WAIT_REG_MEM_EQUAL
||
972 op
== WAIT_REG_MEM_NOT_EQUAL
||
973 op
== WAIT_REG_MEM_GREATER_OR_EQUAL
);
975 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, false));
976 radeon_emit(cs
, op
| WAIT_REG_MEM_MEM_SPACE(1));
978 radeon_emit(cs
, va
>> 32);
979 radeon_emit(cs
, ref
); /* reference value */
980 radeon_emit(cs
, mask
); /* mask */
981 radeon_emit(cs
, 4); /* poll interval */
985 si_emit_acquire_mem(struct radeon_cmdbuf
*cs
,
988 unsigned cp_coher_cntl
)
990 if (is_mec
|| is_gfx9
) {
991 uint32_t hi_val
= is_gfx9
? 0xffffff : 0xff;
992 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, false) |
993 PKT3_SHADER_TYPE_S(is_mec
));
994 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
995 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
996 radeon_emit(cs
, hi_val
); /* CP_COHER_SIZE_HI */
997 radeon_emit(cs
, 0); /* CP_COHER_BASE */
998 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
999 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1001 /* ACQUIRE_MEM is only required on a compute ring. */
1002 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, false));
1003 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
1004 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
1005 radeon_emit(cs
, 0); /* CP_COHER_BASE */
1006 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1011 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1012 enum chip_class chip_class
,
1013 uint32_t *flush_cnt
,
1016 enum radv_cmd_flush_bits flush_bits
,
1017 uint64_t gfx9_eop_bug_va
)
1019 uint32_t gcr_cntl
= 0;
1020 unsigned cb_db_event
= 0;
1022 /* We don't need these. */
1023 assert(!(flush_bits
& (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
)));
1025 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
1026 gcr_cntl
|= S_586_GLI_INV(V_586_GLI_ALL
);
1027 if (flush_bits
& RADV_CMD_FLAG_INV_SCACHE
) {
1028 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1029 * to FORWARD when both L1 and L2 are written out (WB or INV).
1031 gcr_cntl
|= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1033 if (flush_bits
& RADV_CMD_FLAG_INV_VCACHE
)
1034 gcr_cntl
|= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1035 if (flush_bits
& RADV_CMD_FLAG_INV_L2
) {
1036 /* Writeback and invalidate everything in L2. */
1037 gcr_cntl
|= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
1038 S_586_GLM_INV(1) | S_586_GLM_WB(1);
1039 } else if (flush_bits
& RADV_CMD_FLAG_WB_L2
) {
1040 /* Writeback but do not invalidate.
1041 * GLM doesn't support WB alone. If WB is set, INV must be set too.
1043 gcr_cntl
|= S_586_GL2_WB(1) |
1044 S_586_GLM_WB(1) | S_586_GLM_INV(1);
1047 /* TODO: Implement this new flag for GFX9+.
1048 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
1049 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
1052 if (flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
| RADV_CMD_FLAG_FLUSH_AND_INV_DB
)) {
1053 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
1054 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
1055 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1056 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1057 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) |
1061 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
1062 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
1063 /* Flush HTILE. Will wait for idle later. */
1064 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1065 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) |
1069 /* First flush CB/DB, then L1/L2. */
1070 gcr_cntl
|= S_586_SEQ(V_586_SEQ_FORWARD
);
1072 if ((flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
| RADV_CMD_FLAG_FLUSH_AND_INV_DB
)) ==
1073 (RADV_CMD_FLAG_FLUSH_AND_INV_CB
| RADV_CMD_FLAG_FLUSH_AND_INV_DB
)) {
1074 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
1075 } else if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
1076 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
1077 } else if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
1078 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
1083 /* Wait for graphics shaders to go idle if requested. */
1084 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
1085 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1086 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1087 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
1088 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1089 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1093 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
1094 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1095 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
1099 /* CB/DB flush and invalidate (or possibly just a wait for a
1100 * meta flush) via RELEASE_MEM.
1102 * Combine this with other cache flushes when possible; this
1103 * requires affected shaders to be idle, so do it after the
1104 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1107 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1108 unsigned glm_wb
= G_586_GLM_WB(gcr_cntl
);
1109 unsigned glm_inv
= G_586_GLM_INV(gcr_cntl
);
1110 unsigned glv_inv
= G_586_GLV_INV(gcr_cntl
);
1111 unsigned gl1_inv
= G_586_GL1_INV(gcr_cntl
);
1112 assert(G_586_GL2_US(gcr_cntl
) == 0);
1113 assert(G_586_GL2_RANGE(gcr_cntl
) == 0);
1114 assert(G_586_GL2_DISCARD(gcr_cntl
) == 0);
1115 unsigned gl2_inv
= G_586_GL2_INV(gcr_cntl
);
1116 unsigned gl2_wb
= G_586_GL2_WB(gcr_cntl
);
1117 unsigned gcr_seq
= G_586_SEQ(gcr_cntl
);
1119 gcr_cntl
&= C_586_GLM_WB
&
1124 C_586_GL2_WB
; /* keep SEQ */
1129 si_cs_emit_write_event_eop(cs
, chip_class
, false, cb_db_event
,
1130 S_490_GLM_WB(glm_wb
) |
1131 S_490_GLM_INV(glm_inv
) |
1132 S_490_GLV_INV(glv_inv
) |
1133 S_490_GL1_INV(gl1_inv
) |
1134 S_490_GL2_INV(gl2_inv
) |
1135 S_490_GL2_WB(gl2_wb
) |
1138 EOP_DATA_SEL_VALUE_32BIT
,
1139 flush_va
, *flush_cnt
,
1142 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, flush_va
,
1143 *flush_cnt
, 0xffffffff);
1146 /* VGT state sync */
1147 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
1148 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1149 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1152 /* Ignore fields that only modify the behavior of other fields. */
1153 if (gcr_cntl
& C_586_GL1_RANGE
& C_586_GL2_RANGE
& C_586_SEQ
) {
1154 /* Flush caches and wait for the caches to assert idle.
1155 * The cache flush is executed in the ME, but the PFP waits
1158 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 6, 0));
1159 radeon_emit(cs
, 0); /* CP_COHER_CNTL */
1160 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
1161 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
1162 radeon_emit(cs
, 0); /* CP_COHER_BASE */
1163 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
1164 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1165 radeon_emit(cs
, gcr_cntl
); /* GCR_CNTL */
1166 } else if ((cb_db_event
||
1167 (flush_bits
& (RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
1168 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1169 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)))
1171 /* We need to ensure that PFP waits as well. */
1172 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1176 if (flush_bits
& RADV_CMD_FLAG_START_PIPELINE_STATS
) {
1177 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1178 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1180 } else if (flush_bits
& RADV_CMD_FLAG_STOP_PIPELINE_STATS
) {
1181 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1182 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1188 si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1189 enum chip_class chip_class
,
1190 uint32_t *flush_cnt
,
1193 enum radv_cmd_flush_bits flush_bits
,
1194 uint64_t gfx9_eop_bug_va
)
1196 unsigned cp_coher_cntl
= 0;
1197 uint32_t flush_cb_db
= flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1198 RADV_CMD_FLAG_FLUSH_AND_INV_DB
);
1200 if (chip_class
>= GFX10
) {
1201 /* GFX10 cache flush handling is quite different. */
1202 gfx10_cs_emit_cache_flush(cs
, chip_class
, flush_cnt
, flush_va
,
1203 is_mec
, flush_bits
, gfx9_eop_bug_va
);
1207 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
1208 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1209 if (flush_bits
& RADV_CMD_FLAG_INV_SCACHE
)
1210 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1212 if (chip_class
<= GFX8
) {
1213 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
1214 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
1215 S_0085F0_CB0_DEST_BASE_ENA(1) |
1216 S_0085F0_CB1_DEST_BASE_ENA(1) |
1217 S_0085F0_CB2_DEST_BASE_ENA(1) |
1218 S_0085F0_CB3_DEST_BASE_ENA(1) |
1219 S_0085F0_CB4_DEST_BASE_ENA(1) |
1220 S_0085F0_CB5_DEST_BASE_ENA(1) |
1221 S_0085F0_CB6_DEST_BASE_ENA(1) |
1222 S_0085F0_CB7_DEST_BASE_ENA(1);
1224 /* Necessary for DCC */
1225 if (chip_class
>= GFX8
) {
1226 si_cs_emit_write_event_eop(cs
,
1229 V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
1232 EOP_DATA_SEL_DISCARD
,
1237 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
1238 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
1239 S_0085F0_DB_DEST_BASE_ENA(1);
1243 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) {
1244 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1245 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
1248 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) {
1249 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1250 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
1253 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
1254 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1255 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1256 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
1257 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1258 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1261 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
1262 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1263 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1266 if (chip_class
== GFX9
&& flush_cb_db
) {
1267 unsigned cb_db_event
, tc_flags
;
1269 /* Set the CB/DB flush event. */
1270 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
1272 /* These are the only allowed combinations. If you need to
1273 * do multiple operations at once, do them separately.
1274 * All operations that invalidate L2 also seem to invalidate
1275 * metadata. Volatile (VOL) and WC flushes are not listed here.
1277 * TC | TC_WB = writeback & invalidate L2 & L1
1278 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1279 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1280 * TC | TC_NC = invalidate L2 for MTYPE == NC
1281 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1282 * TCL1 = invalidate L1
1284 tc_flags
= EVENT_TC_ACTION_ENA
|
1285 EVENT_TC_MD_ACTION_ENA
;
1287 /* Ideally flush TC together with CB/DB. */
1288 if (flush_bits
& RADV_CMD_FLAG_INV_L2
) {
1289 /* Writeback and invalidate everything in L2 & L1. */
1290 tc_flags
= EVENT_TC_ACTION_ENA
|
1291 EVENT_TC_WB_ACTION_ENA
;
1294 /* Clear the flags. */
1295 flush_bits
&= ~(RADV_CMD_FLAG_INV_L2
|
1296 RADV_CMD_FLAG_WB_L2
|
1297 RADV_CMD_FLAG_INV_VCACHE
);
1302 si_cs_emit_write_event_eop(cs
, chip_class
, false, cb_db_event
, tc_flags
,
1304 EOP_DATA_SEL_VALUE_32BIT
,
1305 flush_va
, *flush_cnt
,
1307 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, flush_va
,
1308 *flush_cnt
, 0xffffffff);
1311 /* VGT state sync */
1312 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
1313 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1314 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1317 /* VGT streamout state sync */
1318 if (flush_bits
& RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
) {
1319 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1320 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
1323 /* Make sure ME is idle (it executes most packets) before continuing.
1324 * This prevents read-after-write hazards between PFP and ME.
1326 if ((cp_coher_cntl
||
1327 (flush_bits
& (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
1328 RADV_CMD_FLAG_INV_VCACHE
|
1329 RADV_CMD_FLAG_INV_L2
|
1330 RADV_CMD_FLAG_WB_L2
))) &&
1332 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1336 if ((flush_bits
& RADV_CMD_FLAG_INV_L2
) ||
1337 (chip_class
<= GFX7
&& (flush_bits
& RADV_CMD_FLAG_WB_L2
))) {
1338 si_emit_acquire_mem(cs
, is_mec
, chip_class
== GFX9
,
1340 S_0085F0_TC_ACTION_ENA(1) |
1341 S_0085F0_TCL1_ACTION_ENA(1) |
1342 S_0301F0_TC_WB_ACTION_ENA(chip_class
>= GFX8
));
1345 if(flush_bits
& RADV_CMD_FLAG_WB_L2
) {
1347 * NC = apply to non-coherent MTYPEs
1348 * (i.e. MTYPE <= 1, which is what we use everywhere)
1350 * WB doesn't work without NC.
1352 si_emit_acquire_mem(cs
, is_mec
,
1355 S_0301F0_TC_WB_ACTION_ENA(1) |
1356 S_0301F0_TC_NC_ACTION_ENA(1));
1359 if (flush_bits
& RADV_CMD_FLAG_INV_VCACHE
) {
1360 si_emit_acquire_mem(cs
, is_mec
,
1363 S_0085F0_TCL1_ACTION_ENA(1));
1368 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1369 * Therefore, it should be last. Done in PFP.
1372 si_emit_acquire_mem(cs
, is_mec
, chip_class
== GFX9
, cp_coher_cntl
);
1374 if (flush_bits
& RADV_CMD_FLAG_START_PIPELINE_STATS
) {
1375 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1376 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1378 } else if (flush_bits
& RADV_CMD_FLAG_STOP_PIPELINE_STATS
) {
1379 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1380 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1386 si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
)
1388 bool is_compute
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
1391 cmd_buffer
->state
.flush_bits
&= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1392 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1393 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1394 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1395 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1396 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
1397 RADV_CMD_FLAG_VGT_FLUSH
|
1398 RADV_CMD_FLAG_START_PIPELINE_STATS
|
1399 RADV_CMD_FLAG_STOP_PIPELINE_STATS
);
1401 if (!cmd_buffer
->state
.flush_bits
)
1404 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 128);
1406 si_cs_emit_cache_flush(cmd_buffer
->cs
,
1407 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
1408 &cmd_buffer
->gfx9_fence_idx
,
1409 cmd_buffer
->gfx9_fence_va
,
1410 radv_cmd_buffer_uses_mec(cmd_buffer
),
1411 cmd_buffer
->state
.flush_bits
,
1412 cmd_buffer
->gfx9_eop_bug_va
);
1415 if (unlikely(cmd_buffer
->device
->trace_bo
))
1416 radv_cmd_buffer_trace_emit(cmd_buffer
);
1418 /* Clear the caches that have been flushed to avoid syncing too much
1419 * when there is some pending active queries.
1421 cmd_buffer
->active_query_flush_bits
&= ~cmd_buffer
->state
.flush_bits
;
1423 cmd_buffer
->state
.flush_bits
= 0;
1425 /* If the driver used a compute shader for resetting a query pool, it
1426 * should be finished at this point.
1428 cmd_buffer
->pending_reset_query
= false;
1431 /* sets the CP predication state using a boolean stored at va */
1433 si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1434 bool draw_visible
, uint64_t va
)
1439 op
= PRED_OP(PREDICATION_OP_BOOL64
);
1441 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1442 * zero, all rendering commands are discarded. Otherwise, they
1443 * are discarded if the value is non zero.
1445 op
|= draw_visible
? PREDICATION_DRAW_VISIBLE
:
1446 PREDICATION_DRAW_NOT_VISIBLE
;
1448 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1449 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 2, 0));
1450 radeon_emit(cmd_buffer
->cs
, op
);
1451 radeon_emit(cmd_buffer
->cs
, va
);
1452 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1454 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 1, 0));
1455 radeon_emit(cmd_buffer
->cs
, va
);
1456 radeon_emit(cmd_buffer
->cs
, op
| ((va
>> 32) & 0xFF));
1460 /* Set this if you want the 3D engine to wait until CP DMA is done.
1461 * It should be set on the last CP DMA packet. */
1462 #define CP_DMA_SYNC (1 << 0)
1464 /* Set this if the source data was used as a destination in a previous CP DMA
1465 * packet. It's for preventing a read-after-write (RAW) hazard between two
1466 * CP DMA packets. */
1467 #define CP_DMA_RAW_WAIT (1 << 1)
1468 #define CP_DMA_USE_L2 (1 << 2)
1469 #define CP_DMA_CLEAR (1 << 3)
1471 /* Alignment for optimal performance. */
1472 #define SI_CPDMA_ALIGNMENT 32
1474 /* The max number of bytes that can be copied per packet. */
1475 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer
*cmd_buffer
)
1477 unsigned max
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
?
1478 S_414_BYTE_COUNT_GFX9(~0u) :
1479 S_414_BYTE_COUNT_GFX6(~0u);
1481 /* make it aligned for optimal performance */
1482 return max
& ~(SI_CPDMA_ALIGNMENT
- 1);
1485 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1486 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1489 static void si_emit_cp_dma(struct radv_cmd_buffer
*cmd_buffer
,
1490 uint64_t dst_va
, uint64_t src_va
,
1491 unsigned size
, unsigned flags
)
1493 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1494 uint32_t header
= 0, command
= 0;
1496 assert(size
<= cp_dma_max_byte_count(cmd_buffer
));
1498 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 9);
1499 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1500 command
|= S_414_BYTE_COUNT_GFX9(size
);
1502 command
|= S_414_BYTE_COUNT_GFX6(size
);
1505 if (flags
& CP_DMA_SYNC
)
1506 header
|= S_411_CP_SYNC(1);
1508 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1509 command
|= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1511 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1514 if (flags
& CP_DMA_RAW_WAIT
)
1515 command
|= S_414_RAW_WAIT(1);
1517 /* Src and dst flags. */
1518 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1519 !(flags
& CP_DMA_CLEAR
) &&
1521 header
|= S_411_DST_SEL(V_411_NOWHERE
); /* prefetch only */
1522 else if (flags
& CP_DMA_USE_L2
)
1523 header
|= S_411_DST_SEL(V_411_DST_ADDR_TC_L2
);
1525 if (flags
& CP_DMA_CLEAR
)
1526 header
|= S_411_SRC_SEL(V_411_DATA
);
1527 else if (flags
& CP_DMA_USE_L2
)
1528 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
);
1530 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1531 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, cmd_buffer
->state
.predicating
));
1532 radeon_emit(cs
, header
);
1533 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1534 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
1535 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1536 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
1537 radeon_emit(cs
, command
);
1539 assert(!(flags
& CP_DMA_USE_L2
));
1540 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
1541 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, cmd_buffer
->state
.predicating
));
1542 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1543 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
1544 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1545 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1546 radeon_emit(cs
, command
);
1549 /* CP DMA is executed in ME, but index buffers are read by PFP.
1550 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1551 * indices. If we wanted to execute CP DMA in PFP, this packet
1552 * should precede it.
1554 if (flags
& CP_DMA_SYNC
) {
1555 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
1556 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1560 /* CP will see the sync flag and wait for all DMAs to complete. */
1561 cmd_buffer
->state
.dma_is_busy
= false;
1564 if (unlikely(cmd_buffer
->device
->trace_bo
))
1565 radv_cmd_buffer_trace_emit(cmd_buffer
);
1568 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1571 uint64_t aligned_va
= va
& ~(SI_CPDMA_ALIGNMENT
- 1);
1572 uint64_t aligned_size
= ((va
+ size
+ SI_CPDMA_ALIGNMENT
-1) & ~(SI_CPDMA_ALIGNMENT
- 1)) - aligned_va
;
1574 si_emit_cp_dma(cmd_buffer
, aligned_va
, aligned_va
,
1575 aligned_size
, CP_DMA_USE_L2
);
1578 static void si_cp_dma_prepare(struct radv_cmd_buffer
*cmd_buffer
, uint64_t byte_count
,
1579 uint64_t remaining_size
, unsigned *flags
)
1582 /* Flush the caches for the first copy only.
1583 * Also wait for the previous CP DMA operations.
1585 if (cmd_buffer
->state
.flush_bits
) {
1586 si_emit_cache_flush(cmd_buffer
);
1587 *flags
|= CP_DMA_RAW_WAIT
;
1590 /* Do the synchronization after the last dma, so that all data
1591 * is written to memory.
1593 if (byte_count
== remaining_size
)
1594 *flags
|= CP_DMA_SYNC
;
1597 static void si_cp_dma_realign_engine(struct radv_cmd_buffer
*cmd_buffer
, unsigned size
)
1601 unsigned dma_flags
= 0;
1602 unsigned buf_size
= SI_CPDMA_ALIGNMENT
* 2;
1605 assert(size
< SI_CPDMA_ALIGNMENT
);
1607 radv_cmd_buffer_upload_alloc(cmd_buffer
, buf_size
, SI_CPDMA_ALIGNMENT
, &offset
, &ptr
);
1609 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1612 si_cp_dma_prepare(cmd_buffer
, size
, size
, &dma_flags
);
1614 si_emit_cp_dma(cmd_buffer
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
,
1618 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1619 uint64_t src_va
, uint64_t dest_va
,
1622 uint64_t main_src_va
, main_dest_va
;
1623 uint64_t skipped_size
= 0, realign_size
= 0;
1625 /* Assume that we are not going to sync after the last DMA operation. */
1626 cmd_buffer
->state
.dma_is_busy
= true;
1628 if (cmd_buffer
->device
->physical_device
->rad_info
.family
<= CHIP_CARRIZO
||
1629 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
) {
1630 /* If the size is not aligned, we must add a dummy copy at the end
1631 * just to align the internal counter. Otherwise, the DMA engine
1632 * would slow down by an order of magnitude for following copies.
1634 if (size
% SI_CPDMA_ALIGNMENT
)
1635 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
1637 /* If the copy begins unaligned, we must start copying from the next
1638 * aligned block and the skipped part should be copied after everything
1639 * else has been copied. Only the src alignment matters, not dst.
1641 if (src_va
% SI_CPDMA_ALIGNMENT
) {
1642 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_va
% SI_CPDMA_ALIGNMENT
);
1643 /* The main part will be skipped if the size is too small. */
1644 skipped_size
= MIN2(skipped_size
, size
);
1645 size
-= skipped_size
;
1648 main_src_va
= src_va
+ skipped_size
;
1649 main_dest_va
= dest_va
+ skipped_size
;
1652 unsigned dma_flags
= 0;
1653 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1655 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1656 /* DMA operations via L2 are coherent and faster.
1657 * TODO: GFX7-GFX9 should also support this but it
1658 * requires tests/benchmarks.
1660 dma_flags
|= CP_DMA_USE_L2
;
1663 si_cp_dma_prepare(cmd_buffer
, byte_count
,
1664 size
+ skipped_size
+ realign_size
,
1667 dma_flags
&= ~CP_DMA_SYNC
;
1669 si_emit_cp_dma(cmd_buffer
, main_dest_va
, main_src_va
,
1670 byte_count
, dma_flags
);
1673 main_src_va
+= byte_count
;
1674 main_dest_va
+= byte_count
;
1678 unsigned dma_flags
= 0;
1680 si_cp_dma_prepare(cmd_buffer
, skipped_size
,
1681 size
+ skipped_size
+ realign_size
,
1684 si_emit_cp_dma(cmd_buffer
, dest_va
, src_va
,
1685 skipped_size
, dma_flags
);
1688 si_cp_dma_realign_engine(cmd_buffer
, realign_size
);
1691 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1692 uint64_t size
, unsigned value
)
1698 assert(va
% 4 == 0 && size
% 4 == 0);
1700 /* Assume that we are not going to sync after the last DMA operation. */
1701 cmd_buffer
->state
.dma_is_busy
= true;
1704 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1705 unsigned dma_flags
= CP_DMA_CLEAR
;
1707 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1708 /* DMA operations via L2 are coherent and faster.
1709 * TODO: GFX7-GFX9 should also support this but it
1710 * requires tests/benchmarks.
1712 dma_flags
|= CP_DMA_USE_L2
;
1715 si_cp_dma_prepare(cmd_buffer
, byte_count
, size
, &dma_flags
);
1717 /* Emit the clear packet. */
1718 si_emit_cp_dma(cmd_buffer
, va
, value
, byte_count
,
1726 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
)
1728 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
< GFX7
)
1731 if (!cmd_buffer
->state
.dma_is_busy
)
1734 /* Issue a dummy DMA that copies zero bytes.
1736 * The DMA engine will see that there's no work to do and skip this
1737 * DMA request, however, the CP will see the sync flag and still wait
1738 * for all DMAs to complete.
1740 si_emit_cp_dma(cmd_buffer
, 0, 0, 0, CP_DMA_SYNC
);
1742 cmd_buffer
->state
.dma_is_busy
= false;
1745 /* For MSAA sample positions. */
1746 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1747 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1748 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1749 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1750 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1752 /* For obtaining location coordinates from registers */
1753 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1754 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1755 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1756 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1759 static const uint32_t sample_locs_1x
=
1760 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1761 static const unsigned max_dist_1x
= 0;
1762 static const uint64_t centroid_priority_1x
= 0x0000000000000000ull
;
1765 static const uint32_t sample_locs_2x
=
1766 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1767 static const unsigned max_dist_2x
= 4;
1768 static const uint64_t centroid_priority_2x
= 0x1010101010101010ull
;
1771 static const uint32_t sample_locs_4x
=
1772 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1773 static const unsigned max_dist_4x
= 6;
1774 static const uint64_t centroid_priority_4x
= 0x3210321032103210ull
;
1777 static const uint32_t sample_locs_8x
[] = {
1778 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1779 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1780 /* The following are unused by hardware, but we emit them to IBs
1781 * instead of multiple SET_CONTEXT_REG packets. */
1785 static const unsigned max_dist_8x
= 7;
1786 static const uint64_t centroid_priority_8x
= 0x7654321076543210ull
;
1788 unsigned radv_get_default_max_sample_dist(int log_samples
)
1790 unsigned max_dist
[] = {
1796 return max_dist
[log_samples
];
1799 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
)
1801 switch (nr_samples
) {
1804 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1805 radeon_emit(cs
, (uint32_t)centroid_priority_1x
);
1806 radeon_emit(cs
, centroid_priority_1x
>> 32);
1807 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_1x
);
1808 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_1x
);
1809 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_1x
);
1810 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_1x
);
1813 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1814 radeon_emit(cs
, (uint32_t)centroid_priority_2x
);
1815 radeon_emit(cs
, centroid_priority_2x
>> 32);
1816 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
);
1817 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
);
1818 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
);
1819 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
);
1822 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1823 radeon_emit(cs
, (uint32_t)centroid_priority_4x
);
1824 radeon_emit(cs
, centroid_priority_4x
>> 32);
1825 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
);
1826 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
);
1827 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
);
1828 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
);
1831 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1832 radeon_emit(cs
, (uint32_t)centroid_priority_8x
);
1833 radeon_emit(cs
, centroid_priority_8x
>> 32);
1834 radeon_set_context_reg_seq(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
1835 radeon_emit_array(cs
, sample_locs_8x
, 4);
1836 radeon_emit_array(cs
, sample_locs_8x
, 4);
1837 radeon_emit_array(cs
, sample_locs_8x
, 4);
1838 radeon_emit_array(cs
, sample_locs_8x
, 2);
1843 static void radv_get_sample_position(struct radv_device
*device
,
1844 unsigned sample_count
,
1845 unsigned sample_index
, float *out_value
)
1847 const uint32_t *sample_locs
;
1849 switch (sample_count
) {
1852 sample_locs
= &sample_locs_1x
;
1855 sample_locs
= &sample_locs_2x
;
1858 sample_locs
= &sample_locs_4x
;
1861 sample_locs
= sample_locs_8x
;
1865 out_value
[0] = (GET_SX(sample_locs
, sample_index
) + 8) / 16.0f
;
1866 out_value
[1] = (GET_SY(sample_locs
, sample_index
) + 8) / 16.0f
;
1869 void radv_device_init_msaa(struct radv_device
*device
)
1873 radv_get_sample_position(device
, 1, 0, device
->sample_locations_1x
[0]);
1875 for (i
= 0; i
< 2; i
++)
1876 radv_get_sample_position(device
, 2, i
, device
->sample_locations_2x
[i
]);
1877 for (i
= 0; i
< 4; i
++)
1878 radv_get_sample_position(device
, 4, i
, device
->sample_locations_4x
[i
]);
1879 for (i
= 0; i
< 8; i
++)
1880 radv_get_sample_position(device
, 8, i
, device
->sample_locations_8x
[i
]);