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radv: s/abs/fabsf/ for floats
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_cmdbuf *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
45 unsigned raster_config_se[4];
46 unsigned se;
47
48 ac_get_harvested_configs(&physical_device->rad_info,
49 raster_config,
50 &raster_config_1,
51 raster_config_se);
52
53 for (se = 0; se < num_se; se++) {
54 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
55 if (physical_device->rad_info.chip_class < CIK)
56 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
57 S_00802C_SE_INDEX(se) |
58 S_00802C_SH_BROADCAST_WRITES(1) |
59 S_00802C_INSTANCE_BROADCAST_WRITES(1));
60 else
61 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
62 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
63 S_030800_INSTANCE_BROADCAST_WRITES(1));
64 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
65 }
66
67 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
68 if (physical_device->rad_info.chip_class < CIK)
69 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
70 S_00802C_SE_BROADCAST_WRITES(1) |
71 S_00802C_SH_BROADCAST_WRITES(1) |
72 S_00802C_INSTANCE_BROADCAST_WRITES(1));
73 else
74 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
75 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
76 S_030800_INSTANCE_BROADCAST_WRITES(1));
77
78 if (physical_device->rad_info.chip_class >= CIK)
79 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
80 }
81
82 void
83 si_emit_compute(struct radv_physical_device *physical_device,
84 struct radeon_cmdbuf *cs)
85 {
86 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89 radeon_emit(cs, 0);
90
91 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
92 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
95
96 if (physical_device->rad_info.chip_class >= CIK) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
100 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
101 S_00B864_SH1_CU_EN(0xffff));
102 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
103 S_00B868_SH1_CU_EN(0xffff));
104 }
105
106 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
107 * and is now per pipe, so it should be handled in the
108 * kernel if we want to use something other than the default value,
109 * which is now 0x22f.
110 */
111 if (physical_device->rad_info.chip_class <= SI) {
112 /* XXX: This should be:
113 * (number of compute units) * 4 * (waves per simd) - 1 */
114
115 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
116 0x190 /* Default value */);
117 }
118 }
119
120 /* 12.4 fixed-point */
121 static unsigned radv_pack_float_12p4(float x)
122 {
123 return x <= 0 ? 0 :
124 x >= 4096 ? 0xffff : x * 16;
125 }
126
127 static void
128 si_set_raster_config(struct radv_physical_device *physical_device,
129 struct radeon_cmdbuf *cs)
130 {
131 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
132 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
133 unsigned raster_config, raster_config_1;
134
135 ac_get_raster_config(&physical_device->rad_info,
136 &raster_config,
137 &raster_config_1, NULL);
138
139 /* Always use the default config when all backends are enabled
140 * (or when we failed to determine the enabled backends).
141 */
142 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
143 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
144 raster_config);
145 if (physical_device->rad_info.chip_class >= CIK)
146 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
147 raster_config_1);
148 } else {
149 si_write_harvested_raster_configs(physical_device, cs,
150 raster_config,
151 raster_config_1);
152 }
153 }
154
155 void
156 si_emit_graphics(struct radv_physical_device *physical_device,
157 struct radeon_cmdbuf *cs)
158 {
159 int i;
160
161 /* Only SI can disable CLEAR_STATE for now. */
162 assert(physical_device->has_clear_state ||
163 physical_device->rad_info.chip_class == SI);
164
165 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
166 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
167 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
168
169 if (physical_device->has_clear_state) {
170 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
171 radeon_emit(cs, 0);
172 }
173
174 if (physical_device->rad_info.chip_class <= VI)
175 si_set_raster_config(physical_device, cs);
176
177 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
178 if (!physical_device->has_clear_state)
179 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
180
181 /* FIXME calculate these values somehow ??? */
182 if (physical_device->rad_info.chip_class <= VI) {
183 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
184 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
185 }
186
187 if (!physical_device->has_clear_state) {
188 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
189 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
190 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
191 }
192
193 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
194 if (!physical_device->has_clear_state)
195 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
196 if (physical_device->rad_info.chip_class < CIK)
197 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
198 S_008A14_CLIP_VTX_REORDER_ENA(1));
199
200 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
201 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
202
203 if (!physical_device->has_clear_state)
204 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
205
206 /* CLEAR_STATE doesn't clear these correctly on certain generations.
207 * I don't know why. Deduced by trial and error.
208 */
209 if (physical_device->rad_info.chip_class <= CIK) {
210 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
211 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
212 S_028204_WINDOW_OFFSET_DISABLE(1));
213 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
214 S_028240_WINDOW_OFFSET_DISABLE(1));
215 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
216 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
217 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
218 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
219 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
220 }
221
222 if (!physical_device->has_clear_state) {
223 for (i = 0; i < 16; i++) {
224 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
225 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
226 }
227 }
228
229 if (!physical_device->has_clear_state) {
230 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
231 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
232 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
233 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
234 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
235 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
236 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
237 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
238 }
239
240 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
241 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
242 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
243
244 if (physical_device->rad_info.chip_class >= GFX9) {
245 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
246 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
247 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
248 } else {
249 /* These registers, when written, also overwrite the
250 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
251 * them. It would be an issue if there was another UMD
252 * changing them.
253 */
254 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
255 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
256 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
257 }
258
259 if (physical_device->rad_info.chip_class >= CIK) {
260 if (physical_device->rad_info.chip_class >= GFX9) {
261 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
262 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
263 } else {
264 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
265 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
266 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
267 S_00B41C_WAVE_LIMIT(0x3F));
268 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
269 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
270 /* If this is 0, Bonaire can hang even if GS isn't being used.
271 * Other chips are unaffected. These are suboptimal values,
272 * but we don't use on-chip GS.
273 */
274 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
275 S_028A44_ES_VERTS_PER_SUBGRP(64) |
276 S_028A44_GS_PRIMS_PER_SUBGRP(4));
277 }
278 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
279 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
280
281 if (physical_device->rad_info.num_good_compute_units /
282 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
283 /* Too few available compute units per SH. Disallowing
284 * VS to run on CU0 could hurt us more than late VS
285 * allocation would help.
286 *
287 * LATE_ALLOC_VS = 2 is the highest safe number.
288 */
289 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
290 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
291 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
292 } else {
293 /* Set LATE_ALLOC_VS == 31. It should be less than
294 * the number of scratch waves. Limitations:
295 * - VS can't execute on CU0.
296 * - If HS writes outputs to LDS, LS can't execute on CU0.
297 */
298 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
299 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
300 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
301 }
302
303 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
304 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
305 }
306
307 if (physical_device->rad_info.chip_class >= VI) {
308 uint32_t vgt_tess_distribution;
309 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
310 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
311 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
312
313 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
314 S_028B50_ACCUM_TRI(11) |
315 S_028B50_ACCUM_QUAD(11) |
316 S_028B50_DONUT_SPLIT(16);
317
318 if (physical_device->rad_info.family == CHIP_FIJI ||
319 physical_device->rad_info.family >= CHIP_POLARIS10)
320 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
321
322 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
323 vgt_tess_distribution);
324 } else if (!physical_device->has_clear_state) {
325 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
326 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
327 }
328
329 if (physical_device->rad_info.chip_class >= GFX9) {
330 unsigned num_se = physical_device->rad_info.max_se;
331 unsigned pc_lines = 0;
332
333 switch (physical_device->rad_info.family) {
334 case CHIP_VEGA10:
335 case CHIP_VEGA12:
336 case CHIP_VEGA20:
337 pc_lines = 4096;
338 break;
339 case CHIP_RAVEN:
340 pc_lines = 1024;
341 break;
342 default:
343 assert(0);
344 }
345
346 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
347 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
348 S_028C48_MAX_PRIM_PER_BATCH(1023));
349 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
350 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
351 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
352 }
353
354 unsigned tmp = (unsigned)(1.0 * 8.0);
355 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
356 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
357 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
358 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
359 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
360
361 if (!physical_device->has_clear_state) {
362 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
363 S_028004_ZPASS_INCREMENT_DISABLE(1));
364 }
365
366 /* Enable the Polaris small primitive filter control.
367 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
368 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
369 * and AMDVLK doesn't have a workaround as well.
370 */
371 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
372 unsigned small_prim_filter_cntl =
373 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
374 /* Workaround for a hw line bug. */
375 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
376
377 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
378 small_prim_filter_cntl);
379 }
380
381 si_emit_compute(physical_device, cs);
382 }
383
384 void
385 cik_create_gfx_config(struct radv_device *device)
386 {
387 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
388 if (!cs)
389 return;
390
391 si_emit_graphics(device->physical_device, cs);
392
393 while (cs->cdw & 7) {
394 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
395 radeon_emit(cs, 0x80000000);
396 else
397 radeon_emit(cs, 0xffff1000);
398 }
399
400 device->gfx_init = device->ws->buffer_create(device->ws,
401 cs->cdw * 4, 4096,
402 RADEON_DOMAIN_GTT,
403 RADEON_FLAG_CPU_ACCESS|
404 RADEON_FLAG_NO_INTERPROCESS_SHARING |
405 RADEON_FLAG_READ_ONLY);
406 if (!device->gfx_init)
407 goto fail;
408
409 void *map = device->ws->buffer_map(device->gfx_init);
410 if (!map) {
411 device->ws->buffer_destroy(device->gfx_init);
412 device->gfx_init = NULL;
413 goto fail;
414 }
415 memcpy(map, cs->buf, cs->cdw * 4);
416
417 device->ws->buffer_unmap(device->gfx_init);
418 device->gfx_init_size_dw = cs->cdw;
419 fail:
420 device->ws->cs_destroy(cs);
421 }
422
423 static void
424 get_viewport_xform(const VkViewport *viewport,
425 float scale[3], float translate[3])
426 {
427 float x = viewport->x;
428 float y = viewport->y;
429 float half_width = 0.5f * viewport->width;
430 float half_height = 0.5f * viewport->height;
431 double n = viewport->minDepth;
432 double f = viewport->maxDepth;
433
434 scale[0] = half_width;
435 translate[0] = half_width + x;
436 scale[1] = half_height;
437 translate[1] = half_height + y;
438
439 scale[2] = (f - n);
440 translate[2] = n;
441 }
442
443 void
444 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
445 int count, const VkViewport *viewports)
446 {
447 int i;
448
449 assert(count);
450 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
451 first_vp * 4 * 6, count * 6);
452
453 for (i = 0; i < count; i++) {
454 float scale[3], translate[3];
455
456
457 get_viewport_xform(&viewports[i], scale, translate);
458 radeon_emit(cs, fui(scale[0]));
459 radeon_emit(cs, fui(translate[0]));
460 radeon_emit(cs, fui(scale[1]));
461 radeon_emit(cs, fui(translate[1]));
462 radeon_emit(cs, fui(scale[2]));
463 radeon_emit(cs, fui(translate[2]));
464 }
465
466 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
467 first_vp * 4 * 2, count * 2);
468 for (i = 0; i < count; i++) {
469 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
470 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
471 radeon_emit(cs, fui(zmin));
472 radeon_emit(cs, fui(zmax));
473 }
474 }
475
476 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
477 {
478 float scale[3], translate[3];
479 VkRect2D rect;
480
481 get_viewport_xform(viewport, scale, translate);
482
483 rect.offset.x = translate[0] - fabs(scale[0]);
484 rect.offset.y = translate[1] - fabs(scale[1]);
485 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
486 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
487
488 return rect;
489 }
490
491 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
492 VkRect2D ret;
493 ret.offset.x = MAX2(a->offset.x, b->offset.x);
494 ret.offset.y = MAX2(a->offset.y, b->offset.y);
495 ret.extent.width = MIN2(a->offset.x + a->extent.width,
496 b->offset.x + b->extent.width) - ret.offset.x;
497 ret.extent.height = MIN2(a->offset.y + a->extent.height,
498 b->offset.y + b->extent.height) - ret.offset.y;
499 return ret;
500 }
501
502 void
503 si_write_scissors(struct radeon_cmdbuf *cs, int first,
504 int count, const VkRect2D *scissors,
505 const VkViewport *viewports, bool can_use_guardband)
506 {
507 int i;
508 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
509 const float max_range = 32767.0f;
510 if (!count)
511 return;
512
513 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
514 for (i = 0; i < count; i++) {
515 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
516 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
517
518 get_viewport_xform(viewports + i, scale, translate);
519 scale[0] = fabsf(scale[0]);
520 scale[1] = fabsf(scale[1]);
521
522 if (scale[0] < 0.5)
523 scale[0] = 0.5;
524 if (scale[1] < 0.5)
525 scale[1] = 0.5;
526
527 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
528 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
529
530 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
531 S_028250_TL_Y(scissor.offset.y) |
532 S_028250_WINDOW_OFFSET_DISABLE(1));
533 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
534 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
535 }
536 if (!can_use_guardband) {
537 guardband_x = 1.0;
538 guardband_y = 1.0;
539 }
540
541 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
542 radeon_emit(cs, fui(guardband_y));
543 radeon_emit(cs, fui(1.0));
544 radeon_emit(cs, fui(guardband_x));
545 radeon_emit(cs, fui(1.0));
546 }
547
548 static inline unsigned
549 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
550 {
551 if (num == 0)
552 return 0;
553
554 if (info->incr == 0)
555 return 0;
556
557 if (num < info->min)
558 return 0;
559
560 return 1 + ((num - info->min) / info->incr);
561 }
562
563 uint32_t
564 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
565 bool instanced_draw, bool indirect_draw,
566 uint32_t draw_vertex_count)
567 {
568 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
569 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
570 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
571 const unsigned max_primgroup_in_wave = 2;
572 /* SWITCH_ON_EOP(0) is always preferable. */
573 bool wd_switch_on_eop = false;
574 bool ia_switch_on_eop = false;
575 bool ia_switch_on_eoi = false;
576 bool partial_vs_wave = false;
577 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
578 bool multi_instances_smaller_than_primgroup;
579
580 multi_instances_smaller_than_primgroup = indirect_draw;
581 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
582 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
583 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
584 multi_instances_smaller_than_primgroup = true;
585 }
586
587 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
588 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
589
590 if (chip_class >= CIK) {
591 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
592
593 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
594 * We don't know that for indirect drawing, so treat it as
595 * always problematic. */
596 if (family == CHIP_HAWAII &&
597 (instanced_draw || indirect_draw))
598 wd_switch_on_eop = true;
599
600 /* Performance recommendation for 4 SE Gfx7-8 parts if
601 * instances are smaller than a primgroup.
602 * Assume indirect draws always use small instances.
603 * This is needed for good VS wave utilization.
604 */
605 if (chip_class <= VI &&
606 info->max_se == 4 &&
607 multi_instances_smaller_than_primgroup)
608 wd_switch_on_eop = true;
609
610 /* Required on CIK and later. */
611 if (info->max_se > 2 && !wd_switch_on_eop)
612 ia_switch_on_eoi = true;
613
614 /* Required by Hawaii and, for some special cases, by VI. */
615 if (ia_switch_on_eoi &&
616 (family == CHIP_HAWAII ||
617 (chip_class == VI &&
618 /* max primgroup in wave is always 2 - leave this for documentation */
619 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
620 partial_vs_wave = true;
621
622 /* Instancing bug on Bonaire. */
623 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
624 (instanced_draw || indirect_draw))
625 partial_vs_wave = true;
626
627 /* If the WD switch is false, the IA switch must be false too. */
628 assert(wd_switch_on_eop || !ia_switch_on_eop);
629 }
630 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
631 if (chip_class <= VI && ia_switch_on_eoi)
632 partial_es_wave = true;
633
634 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
635 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
636 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
637 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
638 */
639 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
640 bool set_vgt_flush = indirect_draw;
641 if (!set_vgt_flush && instanced_draw) {
642 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
643 if (num_prims <= 1)
644 set_vgt_flush = true;
645 }
646 if (set_vgt_flush)
647 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
648 }
649 }
650
651 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
652 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
653 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
654 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
655 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
656 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
657
658 }
659
660 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
661 enum chip_class chip_class,
662 bool is_mec,
663 unsigned event, unsigned event_flags,
664 unsigned data_sel,
665 uint64_t va,
666 uint32_t old_fence,
667 uint32_t new_fence,
668 uint64_t gfx9_eop_bug_va)
669 {
670 unsigned op = EVENT_TYPE(event) |
671 EVENT_INDEX(5) |
672 event_flags;
673 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
674 unsigned sel = EOP_DATA_SEL(data_sel);
675
676 /* Wait for write confirmation before writing data, but don't send
677 * an interrupt. */
678 if (data_sel != EOP_DATA_SEL_DISCARD)
679 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
680
681 if (chip_class >= GFX9 || is_gfx8_mec) {
682 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
683 * counters) must immediately precede every timestamp event to
684 * prevent a GPU hang on GFX9.
685 */
686 if (chip_class == GFX9 && !is_mec) {
687 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
688 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
689 radeon_emit(cs, gfx9_eop_bug_va);
690 radeon_emit(cs, gfx9_eop_bug_va >> 32);
691 }
692
693 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
694 radeon_emit(cs, op);
695 radeon_emit(cs, sel);
696 radeon_emit(cs, va); /* address lo */
697 radeon_emit(cs, va >> 32); /* address hi */
698 radeon_emit(cs, new_fence); /* immediate data lo */
699 radeon_emit(cs, 0); /* immediate data hi */
700 if (!is_gfx8_mec)
701 radeon_emit(cs, 0); /* unused */
702 } else {
703 if (chip_class == CIK ||
704 chip_class == VI) {
705 /* Two EOP events are required to make all engines go idle
706 * (and optional cache flushes executed) before the timestamp
707 * is written.
708 */
709 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
710 radeon_emit(cs, op);
711 radeon_emit(cs, va);
712 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
713 radeon_emit(cs, old_fence); /* immediate data */
714 radeon_emit(cs, 0); /* unused */
715 }
716
717 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
718 radeon_emit(cs, op);
719 radeon_emit(cs, va);
720 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
721 radeon_emit(cs, new_fence); /* immediate data */
722 radeon_emit(cs, 0); /* unused */
723 }
724 }
725
726 void
727 si_emit_wait_fence(struct radeon_cmdbuf *cs,
728 uint64_t va, uint32_t ref,
729 uint32_t mask)
730 {
731 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
732 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
733 radeon_emit(cs, va);
734 radeon_emit(cs, va >> 32);
735 radeon_emit(cs, ref); /* reference value */
736 radeon_emit(cs, mask); /* mask */
737 radeon_emit(cs, 4); /* poll interval */
738 }
739
740 static void
741 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
742 bool is_mec,
743 bool is_gfx9,
744 unsigned cp_coher_cntl)
745 {
746 if (is_mec || is_gfx9) {
747 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
748 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
749 PKT3_SHADER_TYPE_S(is_mec));
750 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
751 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
752 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
753 radeon_emit(cs, 0); /* CP_COHER_BASE */
754 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
755 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
756 } else {
757 /* ACQUIRE_MEM is only required on a compute ring. */
758 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
759 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
760 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
761 radeon_emit(cs, 0); /* CP_COHER_BASE */
762 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
763 }
764 }
765
766 void
767 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
768 enum chip_class chip_class,
769 uint32_t *flush_cnt,
770 uint64_t flush_va,
771 bool is_mec,
772 enum radv_cmd_flush_bits flush_bits,
773 uint64_t gfx9_eop_bug_va)
774 {
775 unsigned cp_coher_cntl = 0;
776 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
777 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
778
779 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
780 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
781 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
782 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
783
784 if (chip_class <= VI) {
785 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
786 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
787 S_0085F0_CB0_DEST_BASE_ENA(1) |
788 S_0085F0_CB1_DEST_BASE_ENA(1) |
789 S_0085F0_CB2_DEST_BASE_ENA(1) |
790 S_0085F0_CB3_DEST_BASE_ENA(1) |
791 S_0085F0_CB4_DEST_BASE_ENA(1) |
792 S_0085F0_CB5_DEST_BASE_ENA(1) |
793 S_0085F0_CB6_DEST_BASE_ENA(1) |
794 S_0085F0_CB7_DEST_BASE_ENA(1);
795
796 /* Necessary for DCC */
797 if (chip_class >= VI) {
798 si_cs_emit_write_event_eop(cs,
799 chip_class,
800 is_mec,
801 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
802 0,
803 EOP_DATA_SEL_DISCARD,
804 0, 0, 0,
805 gfx9_eop_bug_va);
806 }
807 }
808 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
809 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
810 S_0085F0_DB_DEST_BASE_ENA(1);
811 }
812 }
813
814 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
815 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
816 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
817 }
818
819 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
820 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
821 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
822 }
823
824 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
825 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
826 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
827 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
828 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
829 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
830 }
831
832 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
833 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
834 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
835 }
836
837 if (chip_class >= GFX9 && flush_cb_db) {
838 unsigned cb_db_event, tc_flags;
839
840 /* Set the CB/DB flush event. */
841 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
842
843 /* These are the only allowed combinations. If you need to
844 * do multiple operations at once, do them separately.
845 * All operations that invalidate L2 also seem to invalidate
846 * metadata. Volatile (VOL) and WC flushes are not listed here.
847 *
848 * TC | TC_WB = writeback & invalidate L2 & L1
849 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
850 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
851 * TC | TC_NC = invalidate L2 for MTYPE == NC
852 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
853 * TCL1 = invalidate L1
854 */
855 tc_flags = EVENT_TC_ACTION_ENA |
856 EVENT_TC_MD_ACTION_ENA;
857
858 /* Ideally flush TC together with CB/DB. */
859 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
860 /* Writeback and invalidate everything in L2 & L1. */
861 tc_flags = EVENT_TC_ACTION_ENA |
862 EVENT_TC_WB_ACTION_ENA;
863
864
865 /* Clear the flags. */
866 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
867 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
868 RADV_CMD_FLAG_INV_VMEM_L1);
869 }
870 assert(flush_cnt);
871 uint32_t old_fence = (*flush_cnt)++;
872
873 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
874 EOP_DATA_SEL_VALUE_32BIT,
875 flush_va, old_fence, *flush_cnt,
876 gfx9_eop_bug_va);
877 si_emit_wait_fence(cs, flush_va, *flush_cnt, 0xffffffff);
878 }
879
880 /* VGT state sync */
881 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
882 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
883 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
884 }
885
886 /* Make sure ME is idle (it executes most packets) before continuing.
887 * This prevents read-after-write hazards between PFP and ME.
888 */
889 if ((cp_coher_cntl ||
890 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
891 RADV_CMD_FLAG_INV_VMEM_L1 |
892 RADV_CMD_FLAG_INV_GLOBAL_L2 |
893 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
894 !is_mec) {
895 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
896 radeon_emit(cs, 0);
897 }
898
899 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
900 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
901 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
902 cp_coher_cntl |
903 S_0085F0_TC_ACTION_ENA(1) |
904 S_0085F0_TCL1_ACTION_ENA(1) |
905 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
906 cp_coher_cntl = 0;
907 } else {
908 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
909 /* WB = write-back
910 * NC = apply to non-coherent MTYPEs
911 * (i.e. MTYPE <= 1, which is what we use everywhere)
912 *
913 * WB doesn't work without NC.
914 */
915 si_emit_acquire_mem(cs, is_mec,
916 chip_class >= GFX9,
917 cp_coher_cntl |
918 S_0301F0_TC_WB_ACTION_ENA(1) |
919 S_0301F0_TC_NC_ACTION_ENA(1));
920 cp_coher_cntl = 0;
921 }
922 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
923 si_emit_acquire_mem(cs, is_mec,
924 chip_class >= GFX9,
925 cp_coher_cntl |
926 S_0085F0_TCL1_ACTION_ENA(1));
927 cp_coher_cntl = 0;
928 }
929 }
930
931 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
932 * Therefore, it should be last. Done in PFP.
933 */
934 if (cp_coher_cntl)
935 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
936
937 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
938 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
939 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
940 EVENT_INDEX(0));
941 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
942 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
943 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
944 EVENT_INDEX(0));
945 }
946 }
947
948 void
949 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
950 {
951 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
952
953 if (is_compute)
954 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
955 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
956 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
957 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
958 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
959 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
960 RADV_CMD_FLAG_VGT_FLUSH |
961 RADV_CMD_FLAG_START_PIPELINE_STATS |
962 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
963
964 if (!cmd_buffer->state.flush_bits)
965 return;
966
967 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
968 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
969
970 uint32_t *ptr = NULL;
971 uint64_t va = 0;
972 if (chip_class == GFX9) {
973 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
974 ptr = &cmd_buffer->gfx9_fence_idx;
975 }
976 si_cs_emit_cache_flush(cmd_buffer->cs,
977 cmd_buffer->device->physical_device->rad_info.chip_class,
978 ptr, va,
979 radv_cmd_buffer_uses_mec(cmd_buffer),
980 cmd_buffer->state.flush_bits,
981 cmd_buffer->gfx9_eop_bug_va);
982
983
984 if (unlikely(cmd_buffer->device->trace_bo))
985 radv_cmd_buffer_trace_emit(cmd_buffer);
986
987 cmd_buffer->state.flush_bits = 0;
988 }
989
990 /* sets the CP predication state using a boolean stored at va */
991 void
992 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
993 bool draw_visible, uint64_t va)
994 {
995 uint32_t op = 0;
996
997 if (va) {
998 op = PRED_OP(PREDICATION_OP_BOOL64);
999
1000 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1001 * zero, all rendering commands are discarded. Otherwise, they
1002 * are discarded if the value is non zero.
1003 */
1004 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1005 PREDICATION_DRAW_NOT_VISIBLE;
1006 }
1007 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1008 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1009 radeon_emit(cmd_buffer->cs, op);
1010 radeon_emit(cmd_buffer->cs, va);
1011 radeon_emit(cmd_buffer->cs, va >> 32);
1012 } else {
1013 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1014 radeon_emit(cmd_buffer->cs, va);
1015 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1016 }
1017 }
1018
1019 /* Set this if you want the 3D engine to wait until CP DMA is done.
1020 * It should be set on the last CP DMA packet. */
1021 #define CP_DMA_SYNC (1 << 0)
1022
1023 /* Set this if the source data was used as a destination in a previous CP DMA
1024 * packet. It's for preventing a read-after-write (RAW) hazard between two
1025 * CP DMA packets. */
1026 #define CP_DMA_RAW_WAIT (1 << 1)
1027 #define CP_DMA_USE_L2 (1 << 2)
1028 #define CP_DMA_CLEAR (1 << 3)
1029
1030 /* Alignment for optimal performance. */
1031 #define SI_CPDMA_ALIGNMENT 32
1032
1033 /* The max number of bytes that can be copied per packet. */
1034 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1035 {
1036 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1037 S_414_BYTE_COUNT_GFX9(~0u) :
1038 S_414_BYTE_COUNT_GFX6(~0u);
1039
1040 /* make it aligned for optimal performance */
1041 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1042 }
1043
1044 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1045 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1046 * clear value.
1047 */
1048 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1049 uint64_t dst_va, uint64_t src_va,
1050 unsigned size, unsigned flags)
1051 {
1052 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1053 uint32_t header = 0, command = 0;
1054
1055 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1056
1057 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1058 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1059 command |= S_414_BYTE_COUNT_GFX9(size);
1060 else
1061 command |= S_414_BYTE_COUNT_GFX6(size);
1062
1063 /* Sync flags. */
1064 if (flags & CP_DMA_SYNC)
1065 header |= S_411_CP_SYNC(1);
1066 else {
1067 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1068 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1069 else
1070 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1071 }
1072
1073 if (flags & CP_DMA_RAW_WAIT)
1074 command |= S_414_RAW_WAIT(1);
1075
1076 /* Src and dst flags. */
1077 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1078 !(flags & CP_DMA_CLEAR) &&
1079 src_va == dst_va)
1080 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1081 else if (flags & CP_DMA_USE_L2)
1082 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1083
1084 if (flags & CP_DMA_CLEAR)
1085 header |= S_411_SRC_SEL(V_411_DATA);
1086 else if (flags & CP_DMA_USE_L2)
1087 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1088
1089 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1090 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1091 radeon_emit(cs, header);
1092 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1093 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1094 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1095 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1096 radeon_emit(cs, command);
1097 } else {
1098 assert(!(flags & CP_DMA_USE_L2));
1099 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1100 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1101 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1102 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1103 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1104 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1105 radeon_emit(cs, command);
1106 }
1107
1108 /* CP DMA is executed in ME, but index buffers are read by PFP.
1109 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1110 * indices. If we wanted to execute CP DMA in PFP, this packet
1111 * should precede it.
1112 */
1113 if (flags & CP_DMA_SYNC) {
1114 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1115 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1116 radeon_emit(cs, 0);
1117 }
1118
1119 /* CP will see the sync flag and wait for all DMAs to complete. */
1120 cmd_buffer->state.dma_is_busy = false;
1121 }
1122
1123 if (unlikely(cmd_buffer->device->trace_bo))
1124 radv_cmd_buffer_trace_emit(cmd_buffer);
1125 }
1126
1127 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1128 unsigned size)
1129 {
1130 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1131 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1132
1133 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1134 aligned_size, CP_DMA_USE_L2);
1135 }
1136
1137 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1138 uint64_t remaining_size, unsigned *flags)
1139 {
1140
1141 /* Flush the caches for the first copy only.
1142 * Also wait for the previous CP DMA operations.
1143 */
1144 if (cmd_buffer->state.flush_bits) {
1145 si_emit_cache_flush(cmd_buffer);
1146 *flags |= CP_DMA_RAW_WAIT;
1147 }
1148
1149 /* Do the synchronization after the last dma, so that all data
1150 * is written to memory.
1151 */
1152 if (byte_count == remaining_size)
1153 *flags |= CP_DMA_SYNC;
1154 }
1155
1156 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1157 {
1158 uint64_t va;
1159 uint32_t offset;
1160 unsigned dma_flags = 0;
1161 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1162 void *ptr;
1163
1164 assert(size < SI_CPDMA_ALIGNMENT);
1165
1166 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1167
1168 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1169 va += offset;
1170
1171 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1172
1173 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1174 dma_flags);
1175 }
1176
1177 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1178 uint64_t src_va, uint64_t dest_va,
1179 uint64_t size)
1180 {
1181 uint64_t main_src_va, main_dest_va;
1182 uint64_t skipped_size = 0, realign_size = 0;
1183
1184 /* Assume that we are not going to sync after the last DMA operation. */
1185 cmd_buffer->state.dma_is_busy = true;
1186
1187 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1188 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1189 /* If the size is not aligned, we must add a dummy copy at the end
1190 * just to align the internal counter. Otherwise, the DMA engine
1191 * would slow down by an order of magnitude for following copies.
1192 */
1193 if (size % SI_CPDMA_ALIGNMENT)
1194 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1195
1196 /* If the copy begins unaligned, we must start copying from the next
1197 * aligned block and the skipped part should be copied after everything
1198 * else has been copied. Only the src alignment matters, not dst.
1199 */
1200 if (src_va % SI_CPDMA_ALIGNMENT) {
1201 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1202 /* The main part will be skipped if the size is too small. */
1203 skipped_size = MIN2(skipped_size, size);
1204 size -= skipped_size;
1205 }
1206 }
1207 main_src_va = src_va + skipped_size;
1208 main_dest_va = dest_va + skipped_size;
1209
1210 while (size) {
1211 unsigned dma_flags = 0;
1212 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1213
1214 si_cp_dma_prepare(cmd_buffer, byte_count,
1215 size + skipped_size + realign_size,
1216 &dma_flags);
1217
1218 dma_flags &= ~CP_DMA_SYNC;
1219
1220 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1221 byte_count, dma_flags);
1222
1223 size -= byte_count;
1224 main_src_va += byte_count;
1225 main_dest_va += byte_count;
1226 }
1227
1228 if (skipped_size) {
1229 unsigned dma_flags = 0;
1230
1231 si_cp_dma_prepare(cmd_buffer, skipped_size,
1232 size + skipped_size + realign_size,
1233 &dma_flags);
1234
1235 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1236 skipped_size, dma_flags);
1237 }
1238 if (realign_size)
1239 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1240 }
1241
1242 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1243 uint64_t size, unsigned value)
1244 {
1245
1246 if (!size)
1247 return;
1248
1249 assert(va % 4 == 0 && size % 4 == 0);
1250
1251 /* Assume that we are not going to sync after the last DMA operation. */
1252 cmd_buffer->state.dma_is_busy = true;
1253
1254 while (size) {
1255 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1256 unsigned dma_flags = CP_DMA_CLEAR;
1257
1258 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1259
1260 /* Emit the clear packet. */
1261 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1262 dma_flags);
1263
1264 size -= byte_count;
1265 va += byte_count;
1266 }
1267 }
1268
1269 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1270 {
1271 if (cmd_buffer->device->physical_device->rad_info.chip_class < CIK)
1272 return;
1273
1274 if (!cmd_buffer->state.dma_is_busy)
1275 return;
1276
1277 /* Issue a dummy DMA that copies zero bytes.
1278 *
1279 * The DMA engine will see that there's no work to do and skip this
1280 * DMA request, however, the CP will see the sync flag and still wait
1281 * for all DMAs to complete.
1282 */
1283 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1284
1285 cmd_buffer->state.dma_is_busy = false;
1286 }
1287
1288 /* For MSAA sample positions. */
1289 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1290 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1291 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1292 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1293 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1294
1295
1296 /* 2xMSAA
1297 * There are two locations (4, 4), (-4, -4). */
1298 const uint32_t eg_sample_locs_2x[4] = {
1299 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1300 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1301 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1302 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1303 };
1304 const unsigned eg_max_dist_2x = 4;
1305 /* 4xMSAA
1306 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1307 const uint32_t eg_sample_locs_4x[4] = {
1308 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1309 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1310 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1311 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1312 };
1313 const unsigned eg_max_dist_4x = 6;
1314
1315 /* Cayman 8xMSAA */
1316 static const uint32_t cm_sample_locs_8x[] = {
1317 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1318 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1319 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1320 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1321 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1322 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1323 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1324 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1325 };
1326 static const unsigned cm_max_dist_8x = 8;
1327 /* Cayman 16xMSAA */
1328 static const uint32_t cm_sample_locs_16x[] = {
1329 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1330 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1331 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1332 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1333 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1334 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1335 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1336 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1337 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1338 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1339 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1340 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1341 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1342 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1343 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1344 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1345 };
1346 static const unsigned cm_max_dist_16x = 8;
1347
1348 unsigned radv_cayman_get_maxdist(int log_samples)
1349 {
1350 unsigned max_dist[] = {
1351 0,
1352 eg_max_dist_2x,
1353 eg_max_dist_4x,
1354 cm_max_dist_8x,
1355 cm_max_dist_16x
1356 };
1357 return max_dist[log_samples];
1358 }
1359
1360 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples)
1361 {
1362 switch (nr_samples) {
1363 default:
1364 case 1:
1365 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1366 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1367 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1368 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1369 break;
1370 case 2:
1371 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1372 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1373 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1374 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1375 break;
1376 case 4:
1377 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1378 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1379 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1380 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1381 break;
1382 case 8:
1383 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1384 radeon_emit(cs, cm_sample_locs_8x[0]);
1385 radeon_emit(cs, cm_sample_locs_8x[4]);
1386 radeon_emit(cs, 0);
1387 radeon_emit(cs, 0);
1388 radeon_emit(cs, cm_sample_locs_8x[1]);
1389 radeon_emit(cs, cm_sample_locs_8x[5]);
1390 radeon_emit(cs, 0);
1391 radeon_emit(cs, 0);
1392 radeon_emit(cs, cm_sample_locs_8x[2]);
1393 radeon_emit(cs, cm_sample_locs_8x[6]);
1394 radeon_emit(cs, 0);
1395 radeon_emit(cs, 0);
1396 radeon_emit(cs, cm_sample_locs_8x[3]);
1397 radeon_emit(cs, cm_sample_locs_8x[7]);
1398 break;
1399 case 16:
1400 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1401 radeon_emit(cs, cm_sample_locs_16x[0]);
1402 radeon_emit(cs, cm_sample_locs_16x[4]);
1403 radeon_emit(cs, cm_sample_locs_16x[8]);
1404 radeon_emit(cs, cm_sample_locs_16x[12]);
1405 radeon_emit(cs, cm_sample_locs_16x[1]);
1406 radeon_emit(cs, cm_sample_locs_16x[5]);
1407 radeon_emit(cs, cm_sample_locs_16x[9]);
1408 radeon_emit(cs, cm_sample_locs_16x[13]);
1409 radeon_emit(cs, cm_sample_locs_16x[2]);
1410 radeon_emit(cs, cm_sample_locs_16x[6]);
1411 radeon_emit(cs, cm_sample_locs_16x[10]);
1412 radeon_emit(cs, cm_sample_locs_16x[14]);
1413 radeon_emit(cs, cm_sample_locs_16x[3]);
1414 radeon_emit(cs, cm_sample_locs_16x[7]);
1415 radeon_emit(cs, cm_sample_locs_16x[11]);
1416 radeon_emit(cs, cm_sample_locs_16x[15]);
1417 break;
1418 }
1419 }
1420
1421 static void radv_cayman_get_sample_position(struct radv_device *device,
1422 unsigned sample_count,
1423 unsigned sample_index, float *out_value)
1424 {
1425 int offset, index;
1426 struct {
1427 int idx:4;
1428 } val;
1429 switch (sample_count) {
1430 case 1:
1431 default:
1432 out_value[0] = out_value[1] = 0.5;
1433 break;
1434 case 2:
1435 offset = 4 * (sample_index * 2);
1436 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1437 out_value[0] = (float)(val.idx + 8) / 16.0f;
1438 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1439 out_value[1] = (float)(val.idx + 8) / 16.0f;
1440 break;
1441 case 4:
1442 offset = 4 * (sample_index * 2);
1443 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1444 out_value[0] = (float)(val.idx + 8) / 16.0f;
1445 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1446 out_value[1] = (float)(val.idx + 8) / 16.0f;
1447 break;
1448 case 8:
1449 offset = 4 * (sample_index % 4 * 2);
1450 index = (sample_index / 4) * 4;
1451 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1452 out_value[0] = (float)(val.idx + 8) / 16.0f;
1453 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1454 out_value[1] = (float)(val.idx + 8) / 16.0f;
1455 break;
1456 case 16:
1457 offset = 4 * (sample_index % 4 * 2);
1458 index = (sample_index / 4) * 4;
1459 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1460 out_value[0] = (float)(val.idx + 8) / 16.0f;
1461 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1462 out_value[1] = (float)(val.idx + 8) / 16.0f;
1463 break;
1464 }
1465 }
1466
1467 void radv_device_init_msaa(struct radv_device *device)
1468 {
1469 int i;
1470 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1471
1472 for (i = 0; i < 2; i++)
1473 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1474 for (i = 0; i < 4; i++)
1475 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1476 for (i = 0; i < 8; i++)
1477 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1478 for (i = 0; i < 16; i++)
1479 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1480 }