2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
6 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 /* command buffer handling for AMD GCN */
30 #include "radv_private.h"
31 #include "radv_shader.h"
34 #include "radv_util.h"
37 si_write_harvested_raster_configs(struct radv_physical_device
*physical_device
,
38 struct radeon_cmdbuf
*cs
,
39 unsigned raster_config
,
40 unsigned raster_config_1
)
42 unsigned num_se
= MAX2(physical_device
->rad_info
.max_se
, 1);
43 unsigned raster_config_se
[4];
46 ac_get_harvested_configs(&physical_device
->rad_info
,
51 for (se
= 0; se
< num_se
; se
++) {
52 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
53 if (physical_device
->rad_info
.chip_class
< GFX7
)
54 radeon_set_config_reg(cs
, R_00802C_GRBM_GFX_INDEX
,
55 S_00802C_SE_INDEX(se
) |
56 S_00802C_SH_BROADCAST_WRITES(1) |
57 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
60 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
61 S_030800_INSTANCE_BROADCAST_WRITES(1));
62 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
65 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
66 if (physical_device
->rad_info
.chip_class
< GFX7
)
67 radeon_set_config_reg(cs
, R_00802C_GRBM_GFX_INDEX
,
68 S_00802C_SE_BROADCAST_WRITES(1) |
69 S_00802C_SH_BROADCAST_WRITES(1) |
70 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
73 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
74 S_030800_INSTANCE_BROADCAST_WRITES(1));
76 if (physical_device
->rad_info
.chip_class
>= GFX7
)
77 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
81 si_emit_compute(struct radv_physical_device
*physical_device
,
82 struct radeon_cmdbuf
*cs
)
84 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
89 radeon_set_sh_reg_seq(cs
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
, 2);
90 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
91 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
92 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
95 if (physical_device
->rad_info
.chip_class
>= GFX7
) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs
,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
99 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
105 if (physical_device
->rad_info
.chip_class
>= GFX10
)
106 radeon_set_sh_reg(cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, 0);
108 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
109 * and is now per pipe, so it should be handled in the
110 * kernel if we want to use something other than the default value,
111 * which is now 0x22f.
113 if (physical_device
->rad_info
.chip_class
<= GFX6
) {
114 /* XXX: This should be:
115 * (number of compute units) * 4 * (waves per simd) - 1 */
117 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
118 0x190 /* Default value */);
122 /* 12.4 fixed-point */
123 static unsigned radv_pack_float_12p4(float x
)
126 x
>= 4096 ? 0xffff : x
* 16;
130 si_set_raster_config(struct radv_physical_device
*physical_device
,
131 struct radeon_cmdbuf
*cs
)
133 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
134 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
135 unsigned raster_config
, raster_config_1
;
137 ac_get_raster_config(&physical_device
->rad_info
,
139 &raster_config_1
, NULL
);
141 /* Always use the default config when all backends are enabled
142 * (or when we failed to determine the enabled backends).
144 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
145 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
,
147 if (physical_device
->rad_info
.chip_class
>= GFX7
)
148 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
,
151 si_write_harvested_raster_configs(physical_device
, cs
,
158 si_emit_graphics(struct radv_device
*device
,
159 struct radeon_cmdbuf
*cs
)
161 struct radv_physical_device
*physical_device
= device
->physical_device
;
163 bool has_clear_state
= physical_device
->rad_info
.has_clear_state
;
166 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
167 radeon_emit(cs
, CC0_UPDATE_LOAD_ENABLES(1));
168 radeon_emit(cs
, CC1_UPDATE_SHADOW_ENABLES(1));
170 if (has_clear_state
) {
171 radeon_emit(cs
, PKT3(PKT3_CLEAR_STATE
, 0, 0));
175 if (physical_device
->rad_info
.chip_class
<= GFX8
)
176 si_set_raster_config(physical_device
, cs
);
178 radeon_set_context_reg(cs
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
179 if (!has_clear_state
)
180 radeon_set_context_reg(cs
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
182 /* FIXME calculate these values somehow ??? */
183 if (physical_device
->rad_info
.chip_class
<= GFX8
) {
184 radeon_set_context_reg(cs
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
185 radeon_set_context_reg(cs
, R_028A58_VGT_ES_PER_GS
, 0x40);
188 if (!has_clear_state
) {
189 radeon_set_context_reg(cs
, R_028A5C_VGT_GS_PER_VS
, 0x2);
190 radeon_set_context_reg(cs
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
191 radeon_set_context_reg(cs
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
194 if (physical_device
->rad_info
.chip_class
<= GFX9
)
195 radeon_set_context_reg(cs
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
196 if (!has_clear_state
)
197 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
198 if (physical_device
->rad_info
.chip_class
< GFX7
)
199 radeon_set_config_reg(cs
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
200 S_008A14_CLIP_VTX_REORDER_ENA(1));
202 if (!has_clear_state
)
203 radeon_set_context_reg(cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
205 /* CLEAR_STATE doesn't clear these correctly on certain generations.
206 * I don't know why. Deduced by trial and error.
208 if (physical_device
->rad_info
.chip_class
<= GFX7
|| !has_clear_state
) {
209 radeon_set_context_reg(cs
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
210 radeon_set_context_reg(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
,
211 S_028204_WINDOW_OFFSET_DISABLE(1));
212 radeon_set_context_reg(cs
, R_028240_PA_SC_GENERIC_SCISSOR_TL
,
213 S_028240_WINDOW_OFFSET_DISABLE(1));
214 radeon_set_context_reg(cs
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
215 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
216 radeon_set_context_reg(cs
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
217 radeon_set_context_reg(cs
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
218 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
221 if (!has_clear_state
) {
222 for (i
= 0; i
< 16; i
++) {
223 radeon_set_context_reg(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+ i
*8, 0);
224 radeon_set_context_reg(cs
, R_0282D4_PA_SC_VPORT_ZMAX_0
+ i
*8, fui(1.0));
228 if (!has_clear_state
) {
229 radeon_set_context_reg(cs
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
230 radeon_set_context_reg(cs
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
231 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
232 radeon_set_context_reg(cs
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
233 radeon_set_context_reg(cs
, R_028820_PA_CL_NANINF_CNTL
, 0);
234 radeon_set_context_reg(cs
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
235 radeon_set_context_reg(cs
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
236 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
239 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
,
240 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
241 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
243 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
244 radeon_set_context_reg(cs
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
245 radeon_set_uconfig_reg(cs
, R_030964_GE_MAX_VTX_INDX
, ~0);
246 radeon_set_uconfig_reg(cs
, R_030924_GE_MIN_VTX_INDX
, 0);
247 radeon_set_uconfig_reg(cs
, R_030928_GE_INDX_OFFSET
, 0);
248 radeon_set_uconfig_reg(cs
, R_03097C_GE_STEREO_CNTL
, 0);
249 radeon_set_uconfig_reg(cs
, R_030988_GE_USER_VGPR_EN
, 0);
250 } else if (physical_device
->rad_info
.chip_class
== GFX9
) {
251 radeon_set_uconfig_reg(cs
, R_030920_VGT_MAX_VTX_INDX
, ~0);
252 radeon_set_uconfig_reg(cs
, R_030924_VGT_MIN_VTX_INDX
, 0);
253 radeon_set_uconfig_reg(cs
, R_030928_VGT_INDX_OFFSET
, 0);
255 /* These registers, when written, also overwrite the
256 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
257 * them. It would be an issue if there was another UMD
260 radeon_set_context_reg(cs
, R_028400_VGT_MAX_VTX_INDX
, ~0);
261 radeon_set_context_reg(cs
, R_028404_VGT_MIN_VTX_INDX
, 0);
262 radeon_set_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, 0);
265 if (physical_device
->rad_info
.chip_class
>= GFX7
) {
266 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
267 /* Logical CUs 16 - 31 */
268 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
,
269 3, S_00B404_CU_EN(0xffff));
270 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
,
271 3, S_00B104_CU_EN(0xffff));
272 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
,
273 3, S_00B004_CU_EN(0xffff));
276 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
277 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
278 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
280 radeon_set_sh_reg(cs
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
281 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
282 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
283 S_00B41C_WAVE_LIMIT(0x3F));
284 radeon_set_sh_reg(cs
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
285 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
286 /* If this is 0, Bonaire can hang even if GS isn't being used.
287 * Other chips are unaffected. These are suboptimal values,
288 * but we don't use on-chip GS.
290 radeon_set_context_reg(cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
291 S_028A44_ES_VERTS_PER_SUBGRP(64) |
292 S_028A44_GS_PRIMS_PER_SUBGRP(4));
295 /* Compute LATE_ALLOC_VS.LIMIT. */
296 unsigned num_cu_per_sh
= physical_device
->rad_info
.num_good_cu_per_sh
;
297 unsigned late_alloc_wave64
= 0; /* The limit is per SH. */
298 unsigned late_alloc_wave64_gs
= 0;
299 unsigned cu_mask_vs
= 0xffff;
300 unsigned cu_mask_gs
= 0xffff;
302 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
303 /* For Wave32, the hw will launch twice the number of late
304 * alloc waves, so 1 == 2x wave32.
306 if (!physical_device
->rad_info
.use_late_alloc
) {
307 late_alloc_wave64
= 0;
308 } else if (num_cu_per_sh
<= 6) {
309 late_alloc_wave64
= num_cu_per_sh
- 2;
311 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
313 /* CU2 & CU3 disabled because of the dual CU design */
315 cu_mask_gs
= 0xfff3; /* NGG only */
318 late_alloc_wave64_gs
= late_alloc_wave64
;
320 /* Don't use late alloc for NGG on Navi14 due to a hw
321 * bug. If NGG is never used, enable all CUs.
323 if (!physical_device
->use_ngg
||
324 physical_device
->rad_info
.family
== CHIP_NAVI14
) {
325 late_alloc_wave64_gs
= 0;
329 if (!physical_device
->rad_info
.use_late_alloc
) {
330 late_alloc_wave64
= 0;
331 } else if (num_cu_per_sh
<= 4) {
332 /* Too few available compute units per SH.
333 * Disallowing VS to run on one CU could hurt
334 * us more than late VS allocation would help.
336 * 2 is the highest safe number that allows us
337 * to keep all CUs enabled.
339 late_alloc_wave64
= 2;
341 /* This is a good initial value, allowing 1
342 * late_alloc wave per SIMD on num_cu - 2.
344 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
347 if (late_alloc_wave64
> 2)
348 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
351 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
352 3, S_00B118_CU_EN(cu_mask_vs
) |
353 S_00B118_WAVE_LIMIT(0x3F));
354 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
355 S_00B11C_LIMIT(late_alloc_wave64
));
357 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
358 3, S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
360 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
361 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
362 3, S_00B204_CU_EN(0xffff) |
363 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64_gs
));
366 radeon_set_sh_reg_idx(physical_device
, cs
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
367 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
370 if (physical_device
->rad_info
.chip_class
>= GFX10
) {
371 /* Break up a pixel wave if it contains deallocs for more than
372 * half the parameter cache.
374 * To avoid a deadlock where pixel waves aren't launched
375 * because they're waiting for more pixels while the frontend
376 * is stuck waiting for PC space, the maximum allowed value is
377 * the size of the PC minus the largest possible allocation for
378 * a single primitive shader subgroup.
380 radeon_set_context_reg(cs
, R_028C50_PA_SC_NGG_MODE_CNTL
,
381 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
382 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
384 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
385 unsigned meta_write_policy
, meta_read_policy
;
387 /* TODO: investigate whether LRU improves performance on other chips too */
388 if (physical_device
->rad_info
.num_render_backends
<= 4) {
389 meta_write_policy
= V_02807C_CACHE_LRU_WR
; /* cache writes */
390 meta_read_policy
= V_02807C_CACHE_LRU_RD
; /* cache reads */
392 meta_write_policy
= V_02807C_CACHE_STREAM_WR
; /* write combine */
393 meta_read_policy
= V_02807C_CACHE_NOA_RD
; /* don't cache reads */
396 radeon_set_context_reg(cs
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
397 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
398 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
399 S_02807C_HTILE_WR_POLICY(meta_write_policy
) |
400 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
401 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
402 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
403 S_02807C_HTILE_RD_POLICY(meta_read_policy
));
405 radeon_set_context_reg(cs
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
406 S_028410_CMASK_WR_POLICY(meta_write_policy
) |
407 S_028410_FMASK_WR_POLICY(meta_write_policy
) |
408 S_028410_DCC_WR_POLICY(meta_write_policy
) |
409 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
410 S_028410_CMASK_RD_POLICY(meta_read_policy
) |
411 S_028410_FMASK_RD_POLICY(meta_read_policy
) |
412 S_028410_DCC_RD_POLICY(meta_read_policy
) |
413 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
414 radeon_set_context_reg(cs
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
416 radeon_set_sh_reg(cs
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
417 S_00B0C0_SOFT_GROUPING_EN(1) |
418 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
419 radeon_set_sh_reg(cs
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
421 if (physical_device
->rad_info
.chip_class
== GFX10
) {
422 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
423 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
424 radeon_emit(cs
, EVENT_TYPE(V_028A90_SQ_NON_EVENT
) | EVENT_INDEX(0));
427 /* TODO: For culling, replace 128 with 256. */
428 radeon_set_uconfig_reg(cs
, R_030980_GE_PC_ALLOC
,
429 S_030980_OVERSUB_EN(physical_device
->rad_info
.use_late_alloc
) |
430 S_030980_NUM_PC_LINES(128 * physical_device
->rad_info
.max_se
- 1));
433 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
434 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
435 S_028B50_ACCUM_ISOLINE(40) |
436 S_028B50_ACCUM_TRI(30) |
437 S_028B50_ACCUM_QUAD(24) |
438 S_028B50_DONUT_SPLIT(24) |
439 S_028B50_TRAP_SPLIT(6));
440 } else if (physical_device
->rad_info
.chip_class
>= GFX8
) {
441 uint32_t vgt_tess_distribution
;
443 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) |
444 S_028B50_ACCUM_TRI(11) |
445 S_028B50_ACCUM_QUAD(11) |
446 S_028B50_DONUT_SPLIT(16);
448 if (physical_device
->rad_info
.family
== CHIP_FIJI
||
449 physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
450 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
452 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
453 vgt_tess_distribution
);
454 } else if (!has_clear_state
) {
455 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
456 radeon_set_context_reg(cs
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
459 if (device
->border_color_data
.bo
) {
460 uint64_t border_color_va
= radv_buffer_get_va(device
->border_color_data
.bo
);
462 radeon_set_context_reg(cs
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
463 if (physical_device
->rad_info
.chip_class
>= GFX7
) {
464 radeon_set_context_reg(cs
, R_028084_TA_BC_BASE_ADDR_HI
,
465 S_028084_ADDRESS(border_color_va
>> 40));
469 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
470 radeon_set_context_reg(cs
, R_028C48_PA_SC_BINNER_CNTL_1
,
471 S_028C48_MAX_ALLOC_COUNT(physical_device
->rad_info
.pbb_max_alloc_count
- 1) |
472 S_028C48_MAX_PRIM_PER_BATCH(1023));
473 radeon_set_context_reg(cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
474 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
475 radeon_set_uconfig_reg(cs
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
478 unsigned tmp
= (unsigned)(1.0 * 8.0);
479 radeon_set_context_reg_seq(cs
, R_028A00_PA_SU_POINT_SIZE
, 1);
480 radeon_emit(cs
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
481 radeon_set_context_reg_seq(cs
, R_028A04_PA_SU_POINT_MINMAX
, 1);
482 radeon_emit(cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
483 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
485 if (!has_clear_state
) {
486 radeon_set_context_reg(cs
, R_028004_DB_COUNT_CONTROL
,
487 S_028004_ZPASS_INCREMENT_DISABLE(1));
490 /* Enable the Polaris small primitive filter control.
491 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
492 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
493 * and AMDVLK doesn't have a workaround as well.
495 if (physical_device
->rad_info
.family
>= CHIP_POLARIS10
) {
496 unsigned small_prim_filter_cntl
=
497 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
498 /* Workaround for a hw line bug. */
499 S_028830_LINE_FILTER_DISABLE(physical_device
->rad_info
.family
<= CHIP_POLARIS12
);
501 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
502 small_prim_filter_cntl
);
505 si_emit_compute(physical_device
, cs
);
509 cik_create_gfx_config(struct radv_device
*device
)
511 struct radeon_cmdbuf
*cs
= device
->ws
->cs_create(device
->ws
, RING_GFX
);
515 si_emit_graphics(device
, cs
);
517 while (cs
->cdw
& 7) {
518 if (device
->physical_device
->rad_info
.gfx_ib_pad_with_type2
)
519 radeon_emit(cs
, 0x80000000);
521 radeon_emit(cs
, 0xffff1000);
524 device
->gfx_init
= device
->ws
->buffer_create(device
->ws
,
527 RADEON_FLAG_CPU_ACCESS
|
528 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
529 RADEON_FLAG_READ_ONLY
,
530 RADV_BO_PRIORITY_CS
);
531 if (!device
->gfx_init
)
534 void *map
= device
->ws
->buffer_map(device
->gfx_init
);
536 device
->ws
->buffer_destroy(device
->gfx_init
);
537 device
->gfx_init
= NULL
;
540 memcpy(map
, cs
->buf
, cs
->cdw
* 4);
542 device
->ws
->buffer_unmap(device
->gfx_init
);
543 device
->gfx_init_size_dw
= cs
->cdw
;
545 device
->ws
->cs_destroy(cs
);
549 get_viewport_xform(const VkViewport
*viewport
,
550 float scale
[3], float translate
[3])
552 float x
= viewport
->x
;
553 float y
= viewport
->y
;
554 float half_width
= 0.5f
* viewport
->width
;
555 float half_height
= 0.5f
* viewport
->height
;
556 double n
= viewport
->minDepth
;
557 double f
= viewport
->maxDepth
;
559 scale
[0] = half_width
;
560 translate
[0] = half_width
+ x
;
561 scale
[1] = half_height
;
562 translate
[1] = half_height
+ y
;
569 si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
570 int count
, const VkViewport
*viewports
)
575 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
576 first_vp
* 4 * 6, count
* 6);
578 for (i
= 0; i
< count
; i
++) {
579 float scale
[3], translate
[3];
582 get_viewport_xform(&viewports
[i
], scale
, translate
);
583 radeon_emit(cs
, fui(scale
[0]));
584 radeon_emit(cs
, fui(translate
[0]));
585 radeon_emit(cs
, fui(scale
[1]));
586 radeon_emit(cs
, fui(translate
[1]));
587 radeon_emit(cs
, fui(scale
[2]));
588 radeon_emit(cs
, fui(translate
[2]));
591 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
592 first_vp
* 4 * 2, count
* 2);
593 for (i
= 0; i
< count
; i
++) {
594 float zmin
= MIN2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
595 float zmax
= MAX2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
596 radeon_emit(cs
, fui(zmin
));
597 radeon_emit(cs
, fui(zmax
));
601 static VkRect2D
si_scissor_from_viewport(const VkViewport
*viewport
)
603 float scale
[3], translate
[3];
606 get_viewport_xform(viewport
, scale
, translate
);
608 rect
.offset
.x
= translate
[0] - fabsf(scale
[0]);
609 rect
.offset
.y
= translate
[1] - fabsf(scale
[1]);
610 rect
.extent
.width
= ceilf(translate
[0] + fabsf(scale
[0])) - rect
.offset
.x
;
611 rect
.extent
.height
= ceilf(translate
[1] + fabsf(scale
[1])) - rect
.offset
.y
;
616 static VkRect2D
si_intersect_scissor(const VkRect2D
*a
, const VkRect2D
*b
) {
618 ret
.offset
.x
= MAX2(a
->offset
.x
, b
->offset
.x
);
619 ret
.offset
.y
= MAX2(a
->offset
.y
, b
->offset
.y
);
620 ret
.extent
.width
= MIN2(a
->offset
.x
+ a
->extent
.width
,
621 b
->offset
.x
+ b
->extent
.width
) - ret
.offset
.x
;
622 ret
.extent
.height
= MIN2(a
->offset
.y
+ a
->extent
.height
,
623 b
->offset
.y
+ b
->extent
.height
) - ret
.offset
.y
;
628 si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
629 int count
, const VkRect2D
*scissors
,
630 const VkViewport
*viewports
, bool can_use_guardband
)
633 float scale
[3], translate
[3], guardband_x
= INFINITY
, guardband_y
= INFINITY
;
634 const float max_range
= 32767.0f
;
638 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ first
* 4 * 2, count
* 2);
639 for (i
= 0; i
< count
; i
++) {
640 VkRect2D viewport_scissor
= si_scissor_from_viewport(viewports
+ i
);
641 VkRect2D scissor
= si_intersect_scissor(&scissors
[i
], &viewport_scissor
);
643 get_viewport_xform(viewports
+ i
, scale
, translate
);
644 scale
[0] = fabsf(scale
[0]);
645 scale
[1] = fabsf(scale
[1]);
652 guardband_x
= MIN2(guardband_x
, (max_range
- fabsf(translate
[0])) / scale
[0]);
653 guardband_y
= MIN2(guardband_y
, (max_range
- fabsf(translate
[1])) / scale
[1]);
655 radeon_emit(cs
, S_028250_TL_X(scissor
.offset
.x
) |
656 S_028250_TL_Y(scissor
.offset
.y
) |
657 S_028250_WINDOW_OFFSET_DISABLE(1));
658 radeon_emit(cs
, S_028254_BR_X(scissor
.offset
.x
+ scissor
.extent
.width
) |
659 S_028254_BR_Y(scissor
.offset
.y
+ scissor
.extent
.height
));
661 if (!can_use_guardband
) {
666 radeon_set_context_reg_seq(cs
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
667 radeon_emit(cs
, fui(guardband_y
));
668 radeon_emit(cs
, fui(1.0));
669 radeon_emit(cs
, fui(guardband_x
));
670 radeon_emit(cs
, fui(1.0));
673 static inline unsigned
674 radv_prims_for_vertices(struct radv_prim_vertex_count
*info
, unsigned num
)
685 return 1 + ((num
- info
->min
) / info
->incr
);
689 si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
690 bool instanced_draw
, bool indirect_draw
,
691 bool count_from_stream_output
,
692 uint32_t draw_vertex_count
)
694 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
695 enum radeon_family family
= cmd_buffer
->device
->physical_device
->rad_info
.family
;
696 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
697 const unsigned max_primgroup_in_wave
= 2;
698 /* SWITCH_ON_EOP(0) is always preferable. */
699 bool wd_switch_on_eop
= false;
700 bool ia_switch_on_eop
= false;
701 bool ia_switch_on_eoi
= false;
702 bool partial_vs_wave
= false;
703 bool partial_es_wave
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.partial_es_wave
;
704 bool multi_instances_smaller_than_primgroup
;
706 multi_instances_smaller_than_primgroup
= indirect_draw
;
707 if (!multi_instances_smaller_than_primgroup
&& instanced_draw
) {
708 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
709 if (num_prims
< cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.primgroup_size
)
710 multi_instances_smaller_than_primgroup
= true;
713 ia_switch_on_eoi
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.ia_switch_on_eoi
;
714 partial_vs_wave
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.partial_vs_wave
;
716 if (chip_class
>= GFX7
) {
717 wd_switch_on_eop
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.wd_switch_on_eop
;
719 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
720 * We don't know that for indirect drawing, so treat it as
721 * always problematic. */
722 if (family
== CHIP_HAWAII
&&
723 (instanced_draw
|| indirect_draw
))
724 wd_switch_on_eop
= true;
726 /* Performance recommendation for 4 SE Gfx7-8 parts if
727 * instances are smaller than a primgroup.
728 * Assume indirect draws always use small instances.
729 * This is needed for good VS wave utilization.
731 if (chip_class
<= GFX8
&&
733 multi_instances_smaller_than_primgroup
)
734 wd_switch_on_eop
= true;
736 /* Required on GFX7 and later. */
737 if (info
->max_se
> 2 && !wd_switch_on_eop
)
738 ia_switch_on_eoi
= true;
740 /* Required by Hawaii and, for some special cases, by GFX8. */
741 if (ia_switch_on_eoi
&&
742 (family
== CHIP_HAWAII
||
743 (chip_class
== GFX8
&&
744 /* max primgroup in wave is always 2 - leave this for documentation */
745 (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
) || max_primgroup_in_wave
!= 2))))
746 partial_vs_wave
= true;
748 /* Instancing bug on Bonaire. */
749 if (family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
750 (instanced_draw
|| indirect_draw
))
751 partial_vs_wave
= true;
753 /* Hardware requirement when drawing primitives from a stream
756 if (count_from_stream_output
)
757 wd_switch_on_eop
= true;
759 /* If the WD switch is false, the IA switch must be false too. */
760 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
762 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
763 if (chip_class
<= GFX8
&& ia_switch_on_eoi
)
764 partial_es_wave
= true;
766 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
)) {
767 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
768 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
769 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
771 if (family
== CHIP_HAWAII
&& ia_switch_on_eoi
) {
772 bool set_vgt_flush
= indirect_draw
;
773 if (!set_vgt_flush
&& instanced_draw
) {
774 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
776 set_vgt_flush
= true;
779 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
783 return cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.base
|
784 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
785 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
786 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
787 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
788 S_028AA8_WD_SWITCH_ON_EOP(chip_class
>= GFX7
? wd_switch_on_eop
: 0);
792 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
793 enum chip_class chip_class
,
795 unsigned event
, unsigned event_flags
,
796 unsigned dst_sel
, unsigned data_sel
,
799 uint64_t gfx9_eop_bug_va
)
801 unsigned op
= EVENT_TYPE(event
) |
802 EVENT_INDEX(event
== V_028A90_CS_DONE
||
803 event
== V_028A90_PS_DONE
? 6 : 5) |
805 unsigned is_gfx8_mec
= is_mec
&& chip_class
< GFX9
;
806 unsigned sel
= EOP_DST_SEL(dst_sel
) |
807 EOP_DATA_SEL(data_sel
);
809 /* Wait for write confirmation before writing data, but don't send
811 if (data_sel
!= EOP_DATA_SEL_DISCARD
)
812 sel
|= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
);
814 if (chip_class
>= GFX9
|| is_gfx8_mec
) {
815 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
816 * counters) must immediately precede every timestamp event to
817 * prevent a GPU hang on GFX9.
819 if (chip_class
== GFX9
&& !is_mec
) {
820 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
821 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
822 radeon_emit(cs
, gfx9_eop_bug_va
);
823 radeon_emit(cs
, gfx9_eop_bug_va
>> 32);
826 radeon_emit(cs
, PKT3(PKT3_RELEASE_MEM
, is_gfx8_mec
? 5 : 6, false));
828 radeon_emit(cs
, sel
);
829 radeon_emit(cs
, va
); /* address lo */
830 radeon_emit(cs
, va
>> 32); /* address hi */
831 radeon_emit(cs
, new_fence
); /* immediate data lo */
832 radeon_emit(cs
, 0); /* immediate data hi */
834 radeon_emit(cs
, 0); /* unused */
836 if (chip_class
== GFX7
||
837 chip_class
== GFX8
) {
838 /* Two EOP events are required to make all engines go idle
839 * (and optional cache flushes executed) before the timestamp
842 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, false));
845 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
846 radeon_emit(cs
, 0); /* immediate data */
847 radeon_emit(cs
, 0); /* unused */
850 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, false));
853 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
854 radeon_emit(cs
, new_fence
); /* immediate data */
855 radeon_emit(cs
, 0); /* unused */
860 radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
861 uint32_t ref
, uint32_t mask
)
863 assert(op
== WAIT_REG_MEM_EQUAL
||
864 op
== WAIT_REG_MEM_NOT_EQUAL
||
865 op
== WAIT_REG_MEM_GREATER_OR_EQUAL
);
867 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, false));
868 radeon_emit(cs
, op
| WAIT_REG_MEM_MEM_SPACE(1));
870 radeon_emit(cs
, va
>> 32);
871 radeon_emit(cs
, ref
); /* reference value */
872 radeon_emit(cs
, mask
); /* mask */
873 radeon_emit(cs
, 4); /* poll interval */
877 si_emit_acquire_mem(struct radeon_cmdbuf
*cs
,
880 unsigned cp_coher_cntl
)
882 if (is_mec
|| is_gfx9
) {
883 uint32_t hi_val
= is_gfx9
? 0xffffff : 0xff;
884 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, false) |
885 PKT3_SHADER_TYPE_S(is_mec
));
886 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
887 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
888 radeon_emit(cs
, hi_val
); /* CP_COHER_SIZE_HI */
889 radeon_emit(cs
, 0); /* CP_COHER_BASE */
890 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
891 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
893 /* ACQUIRE_MEM is only required on a compute ring. */
894 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, false));
895 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
896 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
897 radeon_emit(cs
, 0); /* CP_COHER_BASE */
898 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
903 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
904 enum chip_class chip_class
,
908 enum radv_cmd_flush_bits flush_bits
,
909 uint64_t gfx9_eop_bug_va
)
911 uint32_t gcr_cntl
= 0;
912 unsigned cb_db_event
= 0;
914 /* We don't need these. */
915 assert(!(flush_bits
& (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
)));
917 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
918 gcr_cntl
|= S_586_GLI_INV(V_586_GLI_ALL
);
919 if (flush_bits
& RADV_CMD_FLAG_INV_SCACHE
) {
920 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
921 * to FORWARD when both L1 and L2 are written out (WB or INV).
923 gcr_cntl
|= S_586_GL1_INV(1) | S_586_GLK_INV(1);
925 if (flush_bits
& RADV_CMD_FLAG_INV_VCACHE
)
926 gcr_cntl
|= S_586_GL1_INV(1) | S_586_GLV_INV(1);
927 if (flush_bits
& RADV_CMD_FLAG_INV_L2
) {
928 /* Writeback and invalidate everything in L2. */
929 gcr_cntl
|= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
930 S_586_GLM_INV(1) | S_586_GLM_WB(1);
931 } else if (flush_bits
& RADV_CMD_FLAG_WB_L2
) {
932 /* Writeback but do not invalidate.
933 * GLM doesn't support WB alone. If WB is set, INV must be set too.
935 gcr_cntl
|= S_586_GL2_WB(1) |
936 S_586_GLM_WB(1) | S_586_GLM_INV(1);
939 /* TODO: Implement this new flag for GFX9+.
940 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
941 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
944 if (flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
| RADV_CMD_FLAG_FLUSH_AND_INV_DB
)) {
945 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
946 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
947 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
948 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
949 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) |
953 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
954 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
955 /* Flush HTILE. Will wait for idle later. */
956 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
957 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) |
961 /* First flush CB/DB, then L1/L2. */
962 gcr_cntl
|= S_586_SEQ(V_586_SEQ_FORWARD
);
964 if ((flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
| RADV_CMD_FLAG_FLUSH_AND_INV_DB
)) ==
965 (RADV_CMD_FLAG_FLUSH_AND_INV_CB
| RADV_CMD_FLAG_FLUSH_AND_INV_DB
)) {
966 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
967 } else if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
968 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
969 } else if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
970 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
975 /* Wait for graphics shaders to go idle if requested. */
976 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
977 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
978 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
979 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
980 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
981 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
985 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
986 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
987 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
991 /* CB/DB flush and invalidate (or possibly just a wait for a
992 * meta flush) via RELEASE_MEM.
994 * Combine this with other cache flushes when possible; this
995 * requires affected shaders to be idle, so do it after the
996 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
999 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1000 unsigned glm_wb
= G_586_GLM_WB(gcr_cntl
);
1001 unsigned glm_inv
= G_586_GLM_INV(gcr_cntl
);
1002 unsigned glv_inv
= G_586_GLV_INV(gcr_cntl
);
1003 unsigned gl1_inv
= G_586_GL1_INV(gcr_cntl
);
1004 assert(G_586_GL2_US(gcr_cntl
) == 0);
1005 assert(G_586_GL2_RANGE(gcr_cntl
) == 0);
1006 assert(G_586_GL2_DISCARD(gcr_cntl
) == 0);
1007 unsigned gl2_inv
= G_586_GL2_INV(gcr_cntl
);
1008 unsigned gl2_wb
= G_586_GL2_WB(gcr_cntl
);
1009 unsigned gcr_seq
= G_586_SEQ(gcr_cntl
);
1011 gcr_cntl
&= C_586_GLM_WB
&
1016 C_586_GL2_WB
; /* keep SEQ */
1021 si_cs_emit_write_event_eop(cs
, chip_class
, false, cb_db_event
,
1022 S_490_GLM_WB(glm_wb
) |
1023 S_490_GLM_INV(glm_inv
) |
1024 S_490_GLV_INV(glv_inv
) |
1025 S_490_GL1_INV(gl1_inv
) |
1026 S_490_GL2_INV(gl2_inv
) |
1027 S_490_GL2_WB(gl2_wb
) |
1030 EOP_DATA_SEL_VALUE_32BIT
,
1031 flush_va
, *flush_cnt
,
1034 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, flush_va
,
1035 *flush_cnt
, 0xffffffff);
1038 /* VGT state sync */
1039 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
1040 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1041 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1044 /* Ignore fields that only modify the behavior of other fields. */
1045 if (gcr_cntl
& C_586_GL1_RANGE
& C_586_GL2_RANGE
& C_586_SEQ
) {
1046 /* Flush caches and wait for the caches to assert idle.
1047 * The cache flush is executed in the ME, but the PFP waits
1050 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 6, 0));
1051 radeon_emit(cs
, 0); /* CP_COHER_CNTL */
1052 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
1053 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
1054 radeon_emit(cs
, 0); /* CP_COHER_BASE */
1055 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
1056 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
1057 radeon_emit(cs
, gcr_cntl
); /* GCR_CNTL */
1058 } else if ((cb_db_event
||
1059 (flush_bits
& (RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
1060 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1061 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)))
1063 /* We need to ensure that PFP waits as well. */
1064 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1068 if (flush_bits
& RADV_CMD_FLAG_START_PIPELINE_STATS
) {
1069 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1070 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1072 } else if (flush_bits
& RADV_CMD_FLAG_STOP_PIPELINE_STATS
) {
1073 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1074 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1080 si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1081 enum chip_class chip_class
,
1082 uint32_t *flush_cnt
,
1085 enum radv_cmd_flush_bits flush_bits
,
1086 uint64_t gfx9_eop_bug_va
)
1088 unsigned cp_coher_cntl
= 0;
1089 uint32_t flush_cb_db
= flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1090 RADV_CMD_FLAG_FLUSH_AND_INV_DB
);
1092 if (chip_class
>= GFX10
) {
1093 /* GFX10 cache flush handling is quite different. */
1094 gfx10_cs_emit_cache_flush(cs
, chip_class
, flush_cnt
, flush_va
,
1095 is_mec
, flush_bits
, gfx9_eop_bug_va
);
1099 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
1100 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1101 if (flush_bits
& RADV_CMD_FLAG_INV_SCACHE
)
1102 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1104 if (chip_class
<= GFX8
) {
1105 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
1106 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
1107 S_0085F0_CB0_DEST_BASE_ENA(1) |
1108 S_0085F0_CB1_DEST_BASE_ENA(1) |
1109 S_0085F0_CB2_DEST_BASE_ENA(1) |
1110 S_0085F0_CB3_DEST_BASE_ENA(1) |
1111 S_0085F0_CB4_DEST_BASE_ENA(1) |
1112 S_0085F0_CB5_DEST_BASE_ENA(1) |
1113 S_0085F0_CB6_DEST_BASE_ENA(1) |
1114 S_0085F0_CB7_DEST_BASE_ENA(1);
1116 /* Necessary for DCC */
1117 if (chip_class
>= GFX8
) {
1118 si_cs_emit_write_event_eop(cs
,
1121 V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
1124 EOP_DATA_SEL_DISCARD
,
1129 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
1130 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
1131 S_0085F0_DB_DEST_BASE_ENA(1);
1135 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) {
1136 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1137 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
1140 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) {
1141 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1142 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
1145 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
1146 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1147 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1148 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
1149 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1150 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1153 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
1154 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1155 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1158 if (chip_class
== GFX9
&& flush_cb_db
) {
1159 unsigned cb_db_event
, tc_flags
;
1161 /* Set the CB/DB flush event. */
1162 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
1164 /* These are the only allowed combinations. If you need to
1165 * do multiple operations at once, do them separately.
1166 * All operations that invalidate L2 also seem to invalidate
1167 * metadata. Volatile (VOL) and WC flushes are not listed here.
1169 * TC | TC_WB = writeback & invalidate L2 & L1
1170 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1171 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1172 * TC | TC_NC = invalidate L2 for MTYPE == NC
1173 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1174 * TCL1 = invalidate L1
1176 tc_flags
= EVENT_TC_ACTION_ENA
|
1177 EVENT_TC_MD_ACTION_ENA
;
1179 /* Ideally flush TC together with CB/DB. */
1180 if (flush_bits
& RADV_CMD_FLAG_INV_L2
) {
1181 /* Writeback and invalidate everything in L2 & L1. */
1182 tc_flags
= EVENT_TC_ACTION_ENA
|
1183 EVENT_TC_WB_ACTION_ENA
;
1186 /* Clear the flags. */
1187 flush_bits
&= ~(RADV_CMD_FLAG_INV_L2
|
1188 RADV_CMD_FLAG_WB_L2
|
1189 RADV_CMD_FLAG_INV_VCACHE
);
1194 si_cs_emit_write_event_eop(cs
, chip_class
, false, cb_db_event
, tc_flags
,
1196 EOP_DATA_SEL_VALUE_32BIT
,
1197 flush_va
, *flush_cnt
,
1199 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, flush_va
,
1200 *flush_cnt
, 0xffffffff);
1203 /* VGT state sync */
1204 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
1205 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1206 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1209 /* VGT streamout state sync */
1210 if (flush_bits
& RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
) {
1211 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1212 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
1215 /* Make sure ME is idle (it executes most packets) before continuing.
1216 * This prevents read-after-write hazards between PFP and ME.
1218 if ((cp_coher_cntl
||
1219 (flush_bits
& (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
1220 RADV_CMD_FLAG_INV_VCACHE
|
1221 RADV_CMD_FLAG_INV_L2
|
1222 RADV_CMD_FLAG_WB_L2
))) &&
1224 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1228 if ((flush_bits
& RADV_CMD_FLAG_INV_L2
) ||
1229 (chip_class
<= GFX7
&& (flush_bits
& RADV_CMD_FLAG_WB_L2
))) {
1230 si_emit_acquire_mem(cs
, is_mec
, chip_class
== GFX9
,
1232 S_0085F0_TC_ACTION_ENA(1) |
1233 S_0085F0_TCL1_ACTION_ENA(1) |
1234 S_0301F0_TC_WB_ACTION_ENA(chip_class
>= GFX8
));
1237 if(flush_bits
& RADV_CMD_FLAG_WB_L2
) {
1239 * NC = apply to non-coherent MTYPEs
1240 * (i.e. MTYPE <= 1, which is what we use everywhere)
1242 * WB doesn't work without NC.
1244 si_emit_acquire_mem(cs
, is_mec
,
1247 S_0301F0_TC_WB_ACTION_ENA(1) |
1248 S_0301F0_TC_NC_ACTION_ENA(1));
1251 if (flush_bits
& RADV_CMD_FLAG_INV_VCACHE
) {
1252 si_emit_acquire_mem(cs
, is_mec
,
1255 S_0085F0_TCL1_ACTION_ENA(1));
1260 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1261 * Therefore, it should be last. Done in PFP.
1264 si_emit_acquire_mem(cs
, is_mec
, chip_class
== GFX9
, cp_coher_cntl
);
1266 if (flush_bits
& RADV_CMD_FLAG_START_PIPELINE_STATS
) {
1267 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1268 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1270 } else if (flush_bits
& RADV_CMD_FLAG_STOP_PIPELINE_STATS
) {
1271 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1272 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1278 si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
)
1280 bool is_compute
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
1283 cmd_buffer
->state
.flush_bits
&= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1284 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1285 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1286 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1287 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1288 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
1289 RADV_CMD_FLAG_VGT_FLUSH
|
1290 RADV_CMD_FLAG_START_PIPELINE_STATS
|
1291 RADV_CMD_FLAG_STOP_PIPELINE_STATS
);
1293 if (!cmd_buffer
->state
.flush_bits
)
1296 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 128);
1298 si_cs_emit_cache_flush(cmd_buffer
->cs
,
1299 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
1300 &cmd_buffer
->gfx9_fence_idx
,
1301 cmd_buffer
->gfx9_fence_va
,
1302 radv_cmd_buffer_uses_mec(cmd_buffer
),
1303 cmd_buffer
->state
.flush_bits
,
1304 cmd_buffer
->gfx9_eop_bug_va
);
1307 if (unlikely(cmd_buffer
->device
->trace_bo
))
1308 radv_cmd_buffer_trace_emit(cmd_buffer
);
1310 /* Clear the caches that have been flushed to avoid syncing too much
1311 * when there is some pending active queries.
1313 cmd_buffer
->active_query_flush_bits
&= ~cmd_buffer
->state
.flush_bits
;
1315 cmd_buffer
->state
.flush_bits
= 0;
1317 /* If the driver used a compute shader for resetting a query pool, it
1318 * should be finished at this point.
1320 cmd_buffer
->pending_reset_query
= false;
1323 /* sets the CP predication state using a boolean stored at va */
1325 si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1326 bool draw_visible
, uint64_t va
)
1331 op
= PRED_OP(PREDICATION_OP_BOOL64
);
1333 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1334 * zero, all rendering commands are discarded. Otherwise, they
1335 * are discarded if the value is non zero.
1337 op
|= draw_visible
? PREDICATION_DRAW_VISIBLE
:
1338 PREDICATION_DRAW_NOT_VISIBLE
;
1340 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1341 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 2, 0));
1342 radeon_emit(cmd_buffer
->cs
, op
);
1343 radeon_emit(cmd_buffer
->cs
, va
);
1344 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1346 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 1, 0));
1347 radeon_emit(cmd_buffer
->cs
, va
);
1348 radeon_emit(cmd_buffer
->cs
, op
| ((va
>> 32) & 0xFF));
1352 /* Set this if you want the 3D engine to wait until CP DMA is done.
1353 * It should be set on the last CP DMA packet. */
1354 #define CP_DMA_SYNC (1 << 0)
1356 /* Set this if the source data was used as a destination in a previous CP DMA
1357 * packet. It's for preventing a read-after-write (RAW) hazard between two
1358 * CP DMA packets. */
1359 #define CP_DMA_RAW_WAIT (1 << 1)
1360 #define CP_DMA_USE_L2 (1 << 2)
1361 #define CP_DMA_CLEAR (1 << 3)
1363 /* Alignment for optimal performance. */
1364 #define SI_CPDMA_ALIGNMENT 32
1366 /* The max number of bytes that can be copied per packet. */
1367 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer
*cmd_buffer
)
1369 unsigned max
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
?
1370 S_414_BYTE_COUNT_GFX9(~0u) :
1371 S_414_BYTE_COUNT_GFX6(~0u);
1373 /* make it aligned for optimal performance */
1374 return max
& ~(SI_CPDMA_ALIGNMENT
- 1);
1377 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1378 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1381 static void si_emit_cp_dma(struct radv_cmd_buffer
*cmd_buffer
,
1382 uint64_t dst_va
, uint64_t src_va
,
1383 unsigned size
, unsigned flags
)
1385 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1386 uint32_t header
= 0, command
= 0;
1388 assert(size
<= cp_dma_max_byte_count(cmd_buffer
));
1390 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 9);
1391 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1392 command
|= S_414_BYTE_COUNT_GFX9(size
);
1394 command
|= S_414_BYTE_COUNT_GFX6(size
);
1397 if (flags
& CP_DMA_SYNC
)
1398 header
|= S_411_CP_SYNC(1);
1400 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1401 command
|= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1403 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1406 if (flags
& CP_DMA_RAW_WAIT
)
1407 command
|= S_414_RAW_WAIT(1);
1409 /* Src and dst flags. */
1410 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1411 !(flags
& CP_DMA_CLEAR
) &&
1413 header
|= S_411_DST_SEL(V_411_NOWHERE
); /* prefetch only */
1414 else if (flags
& CP_DMA_USE_L2
)
1415 header
|= S_411_DST_SEL(V_411_DST_ADDR_TC_L2
);
1417 if (flags
& CP_DMA_CLEAR
)
1418 header
|= S_411_SRC_SEL(V_411_DATA
);
1419 else if (flags
& CP_DMA_USE_L2
)
1420 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
);
1422 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1423 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, cmd_buffer
->state
.predicating
));
1424 radeon_emit(cs
, header
);
1425 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1426 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
1427 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1428 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
1429 radeon_emit(cs
, command
);
1431 assert(!(flags
& CP_DMA_USE_L2
));
1432 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
1433 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, cmd_buffer
->state
.predicating
));
1434 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1435 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
1436 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1437 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1438 radeon_emit(cs
, command
);
1441 /* CP DMA is executed in ME, but index buffers are read by PFP.
1442 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1443 * indices. If we wanted to execute CP DMA in PFP, this packet
1444 * should precede it.
1446 if (flags
& CP_DMA_SYNC
) {
1447 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
1448 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1452 /* CP will see the sync flag and wait for all DMAs to complete. */
1453 cmd_buffer
->state
.dma_is_busy
= false;
1456 if (unlikely(cmd_buffer
->device
->trace_bo
))
1457 radv_cmd_buffer_trace_emit(cmd_buffer
);
1460 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1463 uint64_t aligned_va
= va
& ~(SI_CPDMA_ALIGNMENT
- 1);
1464 uint64_t aligned_size
= ((va
+ size
+ SI_CPDMA_ALIGNMENT
-1) & ~(SI_CPDMA_ALIGNMENT
- 1)) - aligned_va
;
1466 si_emit_cp_dma(cmd_buffer
, aligned_va
, aligned_va
,
1467 aligned_size
, CP_DMA_USE_L2
);
1470 static void si_cp_dma_prepare(struct radv_cmd_buffer
*cmd_buffer
, uint64_t byte_count
,
1471 uint64_t remaining_size
, unsigned *flags
)
1474 /* Flush the caches for the first copy only.
1475 * Also wait for the previous CP DMA operations.
1477 if (cmd_buffer
->state
.flush_bits
) {
1478 si_emit_cache_flush(cmd_buffer
);
1479 *flags
|= CP_DMA_RAW_WAIT
;
1482 /* Do the synchronization after the last dma, so that all data
1483 * is written to memory.
1485 if (byte_count
== remaining_size
)
1486 *flags
|= CP_DMA_SYNC
;
1489 static void si_cp_dma_realign_engine(struct radv_cmd_buffer
*cmd_buffer
, unsigned size
)
1493 unsigned dma_flags
= 0;
1494 unsigned buf_size
= SI_CPDMA_ALIGNMENT
* 2;
1497 assert(size
< SI_CPDMA_ALIGNMENT
);
1499 radv_cmd_buffer_upload_alloc(cmd_buffer
, buf_size
, SI_CPDMA_ALIGNMENT
, &offset
, &ptr
);
1501 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1504 si_cp_dma_prepare(cmd_buffer
, size
, size
, &dma_flags
);
1506 si_emit_cp_dma(cmd_buffer
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
,
1510 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1511 uint64_t src_va
, uint64_t dest_va
,
1514 uint64_t main_src_va
, main_dest_va
;
1515 uint64_t skipped_size
= 0, realign_size
= 0;
1517 /* Assume that we are not going to sync after the last DMA operation. */
1518 cmd_buffer
->state
.dma_is_busy
= true;
1520 if (cmd_buffer
->device
->physical_device
->rad_info
.family
<= CHIP_CARRIZO
||
1521 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
) {
1522 /* If the size is not aligned, we must add a dummy copy at the end
1523 * just to align the internal counter. Otherwise, the DMA engine
1524 * would slow down by an order of magnitude for following copies.
1526 if (size
% SI_CPDMA_ALIGNMENT
)
1527 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
1529 /* If the copy begins unaligned, we must start copying from the next
1530 * aligned block and the skipped part should be copied after everything
1531 * else has been copied. Only the src alignment matters, not dst.
1533 if (src_va
% SI_CPDMA_ALIGNMENT
) {
1534 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_va
% SI_CPDMA_ALIGNMENT
);
1535 /* The main part will be skipped if the size is too small. */
1536 skipped_size
= MIN2(skipped_size
, size
);
1537 size
-= skipped_size
;
1540 main_src_va
= src_va
+ skipped_size
;
1541 main_dest_va
= dest_va
+ skipped_size
;
1544 unsigned dma_flags
= 0;
1545 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1547 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1548 /* DMA operations via L2 are coherent and faster.
1549 * TODO: GFX7-GFX9 should also support this but it
1550 * requires tests/benchmarks.
1552 dma_flags
|= CP_DMA_USE_L2
;
1555 si_cp_dma_prepare(cmd_buffer
, byte_count
,
1556 size
+ skipped_size
+ realign_size
,
1559 dma_flags
&= ~CP_DMA_SYNC
;
1561 si_emit_cp_dma(cmd_buffer
, main_dest_va
, main_src_va
,
1562 byte_count
, dma_flags
);
1565 main_src_va
+= byte_count
;
1566 main_dest_va
+= byte_count
;
1570 unsigned dma_flags
= 0;
1572 si_cp_dma_prepare(cmd_buffer
, skipped_size
,
1573 size
+ skipped_size
+ realign_size
,
1576 si_emit_cp_dma(cmd_buffer
, dest_va
, src_va
,
1577 skipped_size
, dma_flags
);
1580 si_cp_dma_realign_engine(cmd_buffer
, realign_size
);
1583 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1584 uint64_t size
, unsigned value
)
1590 assert(va
% 4 == 0 && size
% 4 == 0);
1592 /* Assume that we are not going to sync after the last DMA operation. */
1593 cmd_buffer
->state
.dma_is_busy
= true;
1596 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1597 unsigned dma_flags
= CP_DMA_CLEAR
;
1599 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1600 /* DMA operations via L2 are coherent and faster.
1601 * TODO: GFX7-GFX9 should also support this but it
1602 * requires tests/benchmarks.
1604 dma_flags
|= CP_DMA_USE_L2
;
1607 si_cp_dma_prepare(cmd_buffer
, byte_count
, size
, &dma_flags
);
1609 /* Emit the clear packet. */
1610 si_emit_cp_dma(cmd_buffer
, va
, value
, byte_count
,
1618 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
)
1620 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
< GFX7
)
1623 if (!cmd_buffer
->state
.dma_is_busy
)
1626 /* Issue a dummy DMA that copies zero bytes.
1628 * The DMA engine will see that there's no work to do and skip this
1629 * DMA request, however, the CP will see the sync flag and still wait
1630 * for all DMAs to complete.
1632 si_emit_cp_dma(cmd_buffer
, 0, 0, 0, CP_DMA_SYNC
);
1634 cmd_buffer
->state
.dma_is_busy
= false;
1637 /* For MSAA sample positions. */
1638 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1639 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1640 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1641 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1642 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1644 /* For obtaining location coordinates from registers */
1645 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1646 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1647 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1648 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1651 static const uint32_t sample_locs_1x
=
1652 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1653 static const unsigned max_dist_1x
= 0;
1654 static const uint64_t centroid_priority_1x
= 0x0000000000000000ull
;
1657 static const uint32_t sample_locs_2x
=
1658 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1659 static const unsigned max_dist_2x
= 4;
1660 static const uint64_t centroid_priority_2x
= 0x1010101010101010ull
;
1663 static const uint32_t sample_locs_4x
=
1664 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1665 static const unsigned max_dist_4x
= 6;
1666 static const uint64_t centroid_priority_4x
= 0x3210321032103210ull
;
1669 static const uint32_t sample_locs_8x
[] = {
1670 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1671 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1672 /* The following are unused by hardware, but we emit them to IBs
1673 * instead of multiple SET_CONTEXT_REG packets. */
1677 static const unsigned max_dist_8x
= 7;
1678 static const uint64_t centroid_priority_8x
= 0x7654321076543210ull
;
1680 unsigned radv_get_default_max_sample_dist(int log_samples
)
1682 unsigned max_dist
[] = {
1688 return max_dist
[log_samples
];
1691 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
)
1693 switch (nr_samples
) {
1696 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1697 radeon_emit(cs
, (uint32_t)centroid_priority_1x
);
1698 radeon_emit(cs
, centroid_priority_1x
>> 32);
1699 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_1x
);
1700 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_1x
);
1701 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_1x
);
1702 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_1x
);
1705 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1706 radeon_emit(cs
, (uint32_t)centroid_priority_2x
);
1707 radeon_emit(cs
, centroid_priority_2x
>> 32);
1708 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
);
1709 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
);
1710 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
);
1711 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
);
1714 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1715 radeon_emit(cs
, (uint32_t)centroid_priority_4x
);
1716 radeon_emit(cs
, centroid_priority_4x
>> 32);
1717 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
);
1718 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
);
1719 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
);
1720 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
);
1723 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1724 radeon_emit(cs
, (uint32_t)centroid_priority_8x
);
1725 radeon_emit(cs
, centroid_priority_8x
>> 32);
1726 radeon_set_context_reg_seq(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
1727 radeon_emit_array(cs
, sample_locs_8x
, 4);
1728 radeon_emit_array(cs
, sample_locs_8x
, 4);
1729 radeon_emit_array(cs
, sample_locs_8x
, 4);
1730 radeon_emit_array(cs
, sample_locs_8x
, 2);
1735 static void radv_get_sample_position(struct radv_device
*device
,
1736 unsigned sample_count
,
1737 unsigned sample_index
, float *out_value
)
1739 const uint32_t *sample_locs
;
1741 switch (sample_count
) {
1744 sample_locs
= &sample_locs_1x
;
1747 sample_locs
= &sample_locs_2x
;
1750 sample_locs
= &sample_locs_4x
;
1753 sample_locs
= sample_locs_8x
;
1757 out_value
[0] = (GET_SX(sample_locs
, sample_index
) + 8) / 16.0f
;
1758 out_value
[1] = (GET_SY(sample_locs
, sample_index
) + 8) / 16.0f
;
1761 void radv_device_init_msaa(struct radv_device
*device
)
1765 radv_get_sample_position(device
, 1, 0, device
->sample_locations_1x
[0]);
1767 for (i
= 0; i
< 2; i
++)
1768 radv_get_sample_position(device
, 2, i
, device
->sample_locations_2x
[i
]);
1769 for (i
= 0; i
< 4; i
++)
1770 radv_get_sample_position(device
, 4, i
, device
->sample_locations_4x
[i
]);
1771 for (i
= 0; i
< 8; i
++)
1772 radv_get_sample_position(device
, 8, i
, device
->sample_locations_8x
[i
]);