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radv: Fix off by one for S_028C48_MAX_ALLOC_COUNT.
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
92 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
95
96 if (physical_device->rad_info.chip_class >= GFX7) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
100 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
101 S_00B858_SH1_CU_EN(0xffff));
102 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
103 S_00B858_SH1_CU_EN(0xffff));
104 }
105
106 if (physical_device->rad_info.chip_class >= GFX10)
107 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
108
109 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
110 * and is now per pipe, so it should be handled in the
111 * kernel if we want to use something other than the default value,
112 * which is now 0x22f.
113 */
114 if (physical_device->rad_info.chip_class <= GFX6) {
115 /* XXX: This should be:
116 * (number of compute units) * 4 * (waves per simd) - 1 */
117
118 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
119 0x190 /* Default value */);
120 }
121 }
122
123 /* 12.4 fixed-point */
124 static unsigned radv_pack_float_12p4(float x)
125 {
126 return x <= 0 ? 0 :
127 x >= 4096 ? 0xffff : x * 16;
128 }
129
130 static void
131 si_set_raster_config(struct radv_physical_device *physical_device,
132 struct radeon_cmdbuf *cs)
133 {
134 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
135 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
136 unsigned raster_config, raster_config_1;
137
138 ac_get_raster_config(&physical_device->rad_info,
139 &raster_config,
140 &raster_config_1, NULL);
141
142 /* Always use the default config when all backends are enabled
143 * (or when we failed to determine the enabled backends).
144 */
145 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
146 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
147 raster_config);
148 if (physical_device->rad_info.chip_class >= GFX7)
149 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
150 raster_config_1);
151 } else {
152 si_write_harvested_raster_configs(physical_device, cs,
153 raster_config,
154 raster_config_1);
155 }
156 }
157
158 void
159 si_emit_graphics(struct radv_physical_device *physical_device,
160 struct radeon_cmdbuf *cs)
161 {
162 int i;
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (physical_device->has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!physical_device->has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!physical_device->has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
193 if (!physical_device->has_clear_state)
194 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
195 if (physical_device->rad_info.chip_class < GFX7)
196 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
197 S_008A14_CLIP_VTX_REORDER_ENA(1));
198
199 if (!physical_device->has_clear_state)
200 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
201
202 /* CLEAR_STATE doesn't clear these correctly on certain generations.
203 * I don't know why. Deduced by trial and error.
204 */
205 if (physical_device->rad_info.chip_class <= GFX7 || !physical_device->has_clear_state) {
206 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
207 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
208 S_028204_WINDOW_OFFSET_DISABLE(1));
209 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
210 S_028240_WINDOW_OFFSET_DISABLE(1));
211 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
212 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
213 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
214 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
215 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
216 }
217
218 if (!physical_device->has_clear_state) {
219 for (i = 0; i < 16; i++) {
220 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
221 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
222 }
223 }
224
225 if (!physical_device->has_clear_state) {
226 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
227 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
228 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
229 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
230 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
231 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
232 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
233 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
234 }
235
236 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
237 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
238 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
239
240 if (physical_device->rad_info.chip_class >= GFX10) {
241 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
242 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
243 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
244 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
245 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
246 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
247 } else if (physical_device->rad_info.chip_class == GFX9) {
248 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
249 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
250 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
251 } else {
252 /* These registers, when written, also overwrite the
253 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
254 * them. It would be an issue if there was another UMD
255 * changing them.
256 */
257 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
258 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
259 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
260 }
261
262 if (physical_device->rad_info.chip_class >= GFX7) {
263 if (physical_device->rad_info.chip_class >= GFX10) {
264 /* Logical CUs 16 - 31 */
265 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
266 3, S_00B404_CU_EN(0xffff));
267 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
268 3, S_00B104_CU_EN(0xffff));
269 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
270 3, S_00B004_CU_EN(0xffff));
271 }
272
273 if (physical_device->rad_info.chip_class >= GFX9) {
274 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
275 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
276 } else {
277 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
278 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
279 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
280 S_00B41C_WAVE_LIMIT(0x3F));
281 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
282 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
283 /* If this is 0, Bonaire can hang even if GS isn't being used.
284 * Other chips are unaffected. These are suboptimal values,
285 * but we don't use on-chip GS.
286 */
287 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
288 S_028A44_ES_VERTS_PER_SUBGRP(64) |
289 S_028A44_GS_PRIMS_PER_SUBGRP(4));
290 }
291
292 /* Compute LATE_ALLOC_VS.LIMIT. */
293 unsigned num_cu_per_sh = physical_device->rad_info.num_good_cu_per_sh;
294 unsigned late_alloc_limit; /* The limit is per SH. */
295
296 if (physical_device->rad_info.family == CHIP_KABINI) {
297 late_alloc_limit = 0; /* Potential hang on Kabini. */
298 } else if (num_cu_per_sh <= 4) {
299 /* Too few available compute units per SH. Disallowing
300 * VS to run on one CU could hurt us more than late VS
301 * allocation would help.
302 *
303 * 2 is the highest safe number that allows us to keep
304 * all CUs enabled.
305 */
306 late_alloc_limit = 2;
307 } else {
308 /* This is a good initial value, allowing 1 late_alloc
309 * wave per SIMD on num_cu - 2.
310 */
311 late_alloc_limit = (num_cu_per_sh - 2) * 4;
312 }
313
314 unsigned late_alloc_limit_gs = late_alloc_limit;
315 unsigned cu_mask_vs = 0xffff;
316 unsigned cu_mask_gs = 0xffff;
317
318 if (late_alloc_limit > 2) {
319 if (physical_device->rad_info.chip_class >= GFX10) {
320 /* CU2 & CU3 disabled because of the dual CU design */
321 cu_mask_vs = 0xfff3;
322 cu_mask_gs = 0xfff3; /* NGG only */
323 } else {
324 cu_mask_vs = 0xfffe; /* 1 CU disabled */
325 }
326 }
327
328 /* Don't use late alloc for NGG on Navi14 due to a hw bug. */
329 if (physical_device->rad_info.family == CHIP_NAVI14) {
330 late_alloc_limit_gs = 0;
331 cu_mask_gs = 0xffff;
332 }
333
334 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
335 3, S_00B118_CU_EN(cu_mask_vs) |
336 S_00B118_WAVE_LIMIT(0x3F));
337 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
338 S_00B11C_LIMIT(late_alloc_limit));
339
340 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
341 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
342
343 if (physical_device->rad_info.chip_class >= GFX10) {
344 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
345 3, S_00B204_CU_EN(0xffff) |
346 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit_gs));
347 }
348
349 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
350 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
351 }
352
353 if (physical_device->rad_info.chip_class >= GFX10) {
354 /* Break up a pixel wave if it contains deallocs for more than
355 * half the parameter cache.
356 *
357 * To avoid a deadlock where pixel waves aren't launched
358 * because they're waiting for more pixels while the frontend
359 * is stuck waiting for PC space, the maximum allowed value is
360 * the size of the PC minus the largest possible allocation for
361 * a single primitive shader subgroup.
362 */
363 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
364 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
365 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
366 radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
367 physical_device->rad_info.pa_sc_tile_steering_override);
368 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
369 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
370 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
371 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
372 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
373 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
374 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
375 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
376
377 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
378 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
379 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
380 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
381 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
382 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
383 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
384 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
385 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
386 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
387
388 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
389 S_00B0C0_SOFT_GROUPING_EN(1) |
390 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
391 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
392
393 if (physical_device->rad_info.family == CHIP_NAVI10 ||
394 physical_device->rad_info.family == CHIP_NAVI12 ||
395 physical_device->rad_info.family == CHIP_NAVI14) {
396 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
397 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
398 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
399 }
400
401 /* TODO: For culling, replace 128 with 256. */
402 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
403 S_030980_OVERSUB_EN(1) |
404 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
405 }
406
407 if (physical_device->rad_info.chip_class >= GFX8) {
408 uint32_t vgt_tess_distribution;
409
410 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
411 S_028B50_ACCUM_TRI(11) |
412 S_028B50_ACCUM_QUAD(11) |
413 S_028B50_DONUT_SPLIT(16);
414
415 if (physical_device->rad_info.family == CHIP_FIJI ||
416 physical_device->rad_info.family >= CHIP_POLARIS10)
417 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
418
419 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
420 vgt_tess_distribution);
421 } else if (!physical_device->has_clear_state) {
422 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
423 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
424 }
425
426 if (physical_device->rad_info.chip_class >= GFX9) {
427 unsigned num_se = physical_device->rad_info.max_se;
428 unsigned pc_lines = 0;
429 unsigned max_alloc_count = 0;
430
431 switch (physical_device->rad_info.family) {
432 case CHIP_VEGA10:
433 case CHIP_VEGA12:
434 case CHIP_VEGA20:
435 pc_lines = 4096;
436 break;
437 case CHIP_RAVEN:
438 case CHIP_RAVEN2:
439 case CHIP_NAVI10:
440 case CHIP_NAVI12:
441 pc_lines = 1024;
442 break;
443 case CHIP_NAVI14:
444 pc_lines = 512;
445 break;
446 default:
447 assert(0);
448 }
449
450 if (physical_device->rad_info.chip_class >= GFX10) {
451 max_alloc_count = pc_lines / 3;
452 } else {
453 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
454 }
455
456 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
457 S_028C48_MAX_ALLOC_COUNT(max_alloc_count - 1) |
458 S_028C48_MAX_PRIM_PER_BATCH(1023));
459 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
460 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
461 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
462 }
463
464 unsigned tmp = (unsigned)(1.0 * 8.0);
465 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
466 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
467 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
468 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
469 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
470
471 if (!physical_device->has_clear_state) {
472 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
473 S_028004_ZPASS_INCREMENT_DISABLE(1));
474 }
475
476 /* Enable the Polaris small primitive filter control.
477 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
478 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
479 * and AMDVLK doesn't have a workaround as well.
480 */
481 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
482 unsigned small_prim_filter_cntl =
483 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
484 /* Workaround for a hw line bug. */
485 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
486
487 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
488 small_prim_filter_cntl);
489 }
490
491 si_emit_compute(physical_device, cs);
492 }
493
494 void
495 cik_create_gfx_config(struct radv_device *device)
496 {
497 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
498 if (!cs)
499 return;
500
501 si_emit_graphics(device->physical_device, cs);
502
503 while (cs->cdw & 7) {
504 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
505 radeon_emit(cs, 0x80000000);
506 else
507 radeon_emit(cs, 0xffff1000);
508 }
509
510 device->gfx_init = device->ws->buffer_create(device->ws,
511 cs->cdw * 4, 4096,
512 RADEON_DOMAIN_GTT,
513 RADEON_FLAG_CPU_ACCESS|
514 RADEON_FLAG_NO_INTERPROCESS_SHARING |
515 RADEON_FLAG_READ_ONLY,
516 RADV_BO_PRIORITY_CS);
517 if (!device->gfx_init)
518 goto fail;
519
520 void *map = device->ws->buffer_map(device->gfx_init);
521 if (!map) {
522 device->ws->buffer_destroy(device->gfx_init);
523 device->gfx_init = NULL;
524 goto fail;
525 }
526 memcpy(map, cs->buf, cs->cdw * 4);
527
528 device->ws->buffer_unmap(device->gfx_init);
529 device->gfx_init_size_dw = cs->cdw;
530 fail:
531 device->ws->cs_destroy(cs);
532 }
533
534 static void
535 get_viewport_xform(const VkViewport *viewport,
536 float scale[3], float translate[3])
537 {
538 float x = viewport->x;
539 float y = viewport->y;
540 float half_width = 0.5f * viewport->width;
541 float half_height = 0.5f * viewport->height;
542 double n = viewport->minDepth;
543 double f = viewport->maxDepth;
544
545 scale[0] = half_width;
546 translate[0] = half_width + x;
547 scale[1] = half_height;
548 translate[1] = half_height + y;
549
550 scale[2] = (f - n);
551 translate[2] = n;
552 }
553
554 void
555 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
556 int count, const VkViewport *viewports)
557 {
558 int i;
559
560 assert(count);
561 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
562 first_vp * 4 * 6, count * 6);
563
564 for (i = 0; i < count; i++) {
565 float scale[3], translate[3];
566
567
568 get_viewport_xform(&viewports[i], scale, translate);
569 radeon_emit(cs, fui(scale[0]));
570 radeon_emit(cs, fui(translate[0]));
571 radeon_emit(cs, fui(scale[1]));
572 radeon_emit(cs, fui(translate[1]));
573 radeon_emit(cs, fui(scale[2]));
574 radeon_emit(cs, fui(translate[2]));
575 }
576
577 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
578 first_vp * 4 * 2, count * 2);
579 for (i = 0; i < count; i++) {
580 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
581 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
582 radeon_emit(cs, fui(zmin));
583 radeon_emit(cs, fui(zmax));
584 }
585 }
586
587 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
588 {
589 float scale[3], translate[3];
590 VkRect2D rect;
591
592 get_viewport_xform(viewport, scale, translate);
593
594 rect.offset.x = translate[0] - fabs(scale[0]);
595 rect.offset.y = translate[1] - fabs(scale[1]);
596 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
597 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
598
599 return rect;
600 }
601
602 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
603 VkRect2D ret;
604 ret.offset.x = MAX2(a->offset.x, b->offset.x);
605 ret.offset.y = MAX2(a->offset.y, b->offset.y);
606 ret.extent.width = MIN2(a->offset.x + a->extent.width,
607 b->offset.x + b->extent.width) - ret.offset.x;
608 ret.extent.height = MIN2(a->offset.y + a->extent.height,
609 b->offset.y + b->extent.height) - ret.offset.y;
610 return ret;
611 }
612
613 void
614 si_write_scissors(struct radeon_cmdbuf *cs, int first,
615 int count, const VkRect2D *scissors,
616 const VkViewport *viewports, bool can_use_guardband)
617 {
618 int i;
619 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
620 const float max_range = 32767.0f;
621 if (!count)
622 return;
623
624 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
625 for (i = 0; i < count; i++) {
626 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
627 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
628
629 get_viewport_xform(viewports + i, scale, translate);
630 scale[0] = fabsf(scale[0]);
631 scale[1] = fabsf(scale[1]);
632
633 if (scale[0] < 0.5)
634 scale[0] = 0.5;
635 if (scale[1] < 0.5)
636 scale[1] = 0.5;
637
638 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
639 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
640
641 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
642 S_028250_TL_Y(scissor.offset.y) |
643 S_028250_WINDOW_OFFSET_DISABLE(1));
644 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
645 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
646 }
647 if (!can_use_guardband) {
648 guardband_x = 1.0;
649 guardband_y = 1.0;
650 }
651
652 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
653 radeon_emit(cs, fui(guardband_y));
654 radeon_emit(cs, fui(1.0));
655 radeon_emit(cs, fui(guardband_x));
656 radeon_emit(cs, fui(1.0));
657 }
658
659 static inline unsigned
660 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
661 {
662 if (num == 0)
663 return 0;
664
665 if (info->incr == 0)
666 return 0;
667
668 if (num < info->min)
669 return 0;
670
671 return 1 + ((num - info->min) / info->incr);
672 }
673
674 uint32_t
675 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
676 bool instanced_draw, bool indirect_draw,
677 bool count_from_stream_output,
678 uint32_t draw_vertex_count)
679 {
680 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
681 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
682 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
683 const unsigned max_primgroup_in_wave = 2;
684 /* SWITCH_ON_EOP(0) is always preferable. */
685 bool wd_switch_on_eop = false;
686 bool ia_switch_on_eop = false;
687 bool ia_switch_on_eoi = false;
688 bool partial_vs_wave = false;
689 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
690 bool multi_instances_smaller_than_primgroup;
691
692 multi_instances_smaller_than_primgroup = indirect_draw;
693 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
694 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
695 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
696 multi_instances_smaller_than_primgroup = true;
697 }
698
699 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
700 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
701
702 if (chip_class >= GFX7) {
703 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
704
705 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
706 * We don't know that for indirect drawing, so treat it as
707 * always problematic. */
708 if (family == CHIP_HAWAII &&
709 (instanced_draw || indirect_draw))
710 wd_switch_on_eop = true;
711
712 /* Performance recommendation for 4 SE Gfx7-8 parts if
713 * instances are smaller than a primgroup.
714 * Assume indirect draws always use small instances.
715 * This is needed for good VS wave utilization.
716 */
717 if (chip_class <= GFX8 &&
718 info->max_se == 4 &&
719 multi_instances_smaller_than_primgroup)
720 wd_switch_on_eop = true;
721
722 /* Required on GFX7 and later. */
723 if (info->max_se > 2 && !wd_switch_on_eop)
724 ia_switch_on_eoi = true;
725
726 /* Required by Hawaii and, for some special cases, by GFX8. */
727 if (ia_switch_on_eoi &&
728 (family == CHIP_HAWAII ||
729 (chip_class == GFX8 &&
730 /* max primgroup in wave is always 2 - leave this for documentation */
731 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
732 partial_vs_wave = true;
733
734 /* Instancing bug on Bonaire. */
735 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
736 (instanced_draw || indirect_draw))
737 partial_vs_wave = true;
738
739 /* Hardware requirement when drawing primitives from a stream
740 * output buffer.
741 */
742 if (count_from_stream_output)
743 wd_switch_on_eop = true;
744
745 /* If the WD switch is false, the IA switch must be false too. */
746 assert(wd_switch_on_eop || !ia_switch_on_eop);
747 }
748 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
749 if (chip_class <= GFX8 && ia_switch_on_eoi)
750 partial_es_wave = true;
751
752 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
753 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
754 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
755 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
756 */
757 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
758 bool set_vgt_flush = indirect_draw;
759 if (!set_vgt_flush && instanced_draw) {
760 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
761 if (num_prims <= 1)
762 set_vgt_flush = true;
763 }
764 if (set_vgt_flush)
765 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
766 }
767 }
768
769 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
770 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
771 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
772 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
773 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
774 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
775
776 }
777
778 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
779 enum chip_class chip_class,
780 bool is_mec,
781 unsigned event, unsigned event_flags,
782 unsigned dst_sel, unsigned data_sel,
783 uint64_t va,
784 uint32_t new_fence,
785 uint64_t gfx9_eop_bug_va)
786 {
787 unsigned op = EVENT_TYPE(event) |
788 EVENT_INDEX(event == V_028A90_CS_DONE ||
789 event == V_028A90_PS_DONE ? 6 : 5) |
790 event_flags;
791 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
792 unsigned sel = EOP_DST_SEL(dst_sel) |
793 EOP_DATA_SEL(data_sel);
794
795 /* Wait for write confirmation before writing data, but don't send
796 * an interrupt. */
797 if (data_sel != EOP_DATA_SEL_DISCARD)
798 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
799
800 if (chip_class >= GFX9 || is_gfx8_mec) {
801 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
802 * counters) must immediately precede every timestamp event to
803 * prevent a GPU hang on GFX9.
804 */
805 if (chip_class == GFX9 && !is_mec) {
806 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
807 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
808 radeon_emit(cs, gfx9_eop_bug_va);
809 radeon_emit(cs, gfx9_eop_bug_va >> 32);
810 }
811
812 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
813 radeon_emit(cs, op);
814 radeon_emit(cs, sel);
815 radeon_emit(cs, va); /* address lo */
816 radeon_emit(cs, va >> 32); /* address hi */
817 radeon_emit(cs, new_fence); /* immediate data lo */
818 radeon_emit(cs, 0); /* immediate data hi */
819 if (!is_gfx8_mec)
820 radeon_emit(cs, 0); /* unused */
821 } else {
822 if (chip_class == GFX7 ||
823 chip_class == GFX8) {
824 /* Two EOP events are required to make all engines go idle
825 * (and optional cache flushes executed) before the timestamp
826 * is written.
827 */
828 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
829 radeon_emit(cs, op);
830 radeon_emit(cs, va);
831 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
832 radeon_emit(cs, 0); /* immediate data */
833 radeon_emit(cs, 0); /* unused */
834 }
835
836 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
837 radeon_emit(cs, op);
838 radeon_emit(cs, va);
839 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
840 radeon_emit(cs, new_fence); /* immediate data */
841 radeon_emit(cs, 0); /* unused */
842 }
843 }
844
845 void
846 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
847 uint32_t ref, uint32_t mask)
848 {
849 assert(op == WAIT_REG_MEM_EQUAL ||
850 op == WAIT_REG_MEM_NOT_EQUAL ||
851 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
852
853 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
854 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
855 radeon_emit(cs, va);
856 radeon_emit(cs, va >> 32);
857 radeon_emit(cs, ref); /* reference value */
858 radeon_emit(cs, mask); /* mask */
859 radeon_emit(cs, 4); /* poll interval */
860 }
861
862 static void
863 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
864 bool is_mec,
865 bool is_gfx9,
866 unsigned cp_coher_cntl)
867 {
868 if (is_mec || is_gfx9) {
869 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
870 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
871 PKT3_SHADER_TYPE_S(is_mec));
872 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
873 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
874 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
875 radeon_emit(cs, 0); /* CP_COHER_BASE */
876 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
877 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
878 } else {
879 /* ACQUIRE_MEM is only required on a compute ring. */
880 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
881 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
882 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
883 radeon_emit(cs, 0); /* CP_COHER_BASE */
884 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
885 }
886 }
887
888 static void
889 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
890 enum chip_class chip_class,
891 uint32_t *flush_cnt,
892 uint64_t flush_va,
893 bool is_mec,
894 enum radv_cmd_flush_bits flush_bits,
895 uint64_t gfx9_eop_bug_va)
896 {
897 uint32_t gcr_cntl = 0;
898 unsigned cb_db_event = 0;
899
900 /* We don't need these. */
901 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
902
903 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
904 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
905 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
906 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
907 * to FORWARD when both L1 and L2 are written out (WB or INV).
908 */
909 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
910 }
911 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
912 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
913 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
914 /* Writeback and invalidate everything in L2. */
915 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
916 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
917 /* Writeback but do not invalidate. */
918 gcr_cntl |= S_586_GL2_WB(1);
919 }
920
921 /* TODO: Implement this new flag for GFX9+.
922 if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
923 gcr_cntl |= S_586_GLM_INV(1);
924 */
925
926 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
927 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
928 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
929 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
930 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
931 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
932 EVENT_INDEX(0));
933 }
934
935 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
936 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
937 /* Flush HTILE. Will wait for idle later. */
938 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
939 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
940 EVENT_INDEX(0));
941 }
942
943 /* First flush CB/DB, then L1/L2. */
944 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
945
946 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
947 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
948 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
949 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
950 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
951 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
952 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
953 } else {
954 assert(0);
955 }
956 } else {
957 /* Wait for graphics shaders to go idle if requested. */
958 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
959 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
960 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
961 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
962 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
963 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
964 }
965 }
966
967 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
968 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
969 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
970 }
971
972 if (cb_db_event) {
973 /* CB/DB flush and invalidate (or possibly just a wait for a
974 * meta flush) via RELEASE_MEM.
975 *
976 * Combine this with other cache flushes when possible; this
977 * requires affected shaders to be idle, so do it after the
978 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
979 * implied).
980 */
981 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
982 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
983 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
984 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
985 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
986 assert(G_586_GL2_US(gcr_cntl) == 0);
987 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
988 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
989 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
990 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
991 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
992
993 gcr_cntl &= C_586_GLM_WB &
994 C_586_GLM_INV &
995 C_586_GLV_INV &
996 C_586_GL1_INV &
997 C_586_GL2_INV &
998 C_586_GL2_WB; /* keep SEQ */
999
1000 assert(flush_cnt);
1001 (*flush_cnt)++;
1002
1003 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
1004 S_490_GLM_WB(glm_wb) |
1005 S_490_GLM_INV(glm_inv) |
1006 S_490_GLV_INV(glv_inv) |
1007 S_490_GL1_INV(gl1_inv) |
1008 S_490_GL2_INV(gl2_inv) |
1009 S_490_GL2_WB(gl2_wb) |
1010 S_490_SEQ(gcr_seq),
1011 EOP_DST_SEL_MEM,
1012 EOP_DATA_SEL_VALUE_32BIT,
1013 flush_va, *flush_cnt,
1014 gfx9_eop_bug_va);
1015
1016 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1017 *flush_cnt, 0xffffffff);
1018 }
1019
1020 /* VGT state sync */
1021 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1022 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1023 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1024 }
1025
1026 /* Ignore fields that only modify the behavior of other fields. */
1027 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1028 /* Flush caches and wait for the caches to assert idle.
1029 * The cache flush is executed in the ME, but the PFP waits
1030 * for completion.
1031 */
1032 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1033 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1034 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1035 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1036 radeon_emit(cs, 0); /* CP_COHER_BASE */
1037 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1038 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1039 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1040 } else if ((cb_db_event ||
1041 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1042 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1043 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1044 && !is_mec) {
1045 /* We need to ensure that PFP waits as well. */
1046 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1047 radeon_emit(cs, 0);
1048 }
1049
1050 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1051 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1052 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1053 EVENT_INDEX(0));
1054 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1055 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1056 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1057 EVENT_INDEX(0));
1058 }
1059 }
1060
1061 void
1062 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1063 enum chip_class chip_class,
1064 uint32_t *flush_cnt,
1065 uint64_t flush_va,
1066 bool is_mec,
1067 enum radv_cmd_flush_bits flush_bits,
1068 uint64_t gfx9_eop_bug_va)
1069 {
1070 unsigned cp_coher_cntl = 0;
1071 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1072 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1073
1074 if (chip_class >= GFX10) {
1075 /* GFX10 cache flush handling is quite different. */
1076 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1077 is_mec, flush_bits, gfx9_eop_bug_va);
1078 return;
1079 }
1080
1081 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1082 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1083 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1084 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1085
1086 if (chip_class <= GFX8) {
1087 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1088 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1089 S_0085F0_CB0_DEST_BASE_ENA(1) |
1090 S_0085F0_CB1_DEST_BASE_ENA(1) |
1091 S_0085F0_CB2_DEST_BASE_ENA(1) |
1092 S_0085F0_CB3_DEST_BASE_ENA(1) |
1093 S_0085F0_CB4_DEST_BASE_ENA(1) |
1094 S_0085F0_CB5_DEST_BASE_ENA(1) |
1095 S_0085F0_CB6_DEST_BASE_ENA(1) |
1096 S_0085F0_CB7_DEST_BASE_ENA(1);
1097
1098 /* Necessary for DCC */
1099 if (chip_class >= GFX8) {
1100 si_cs_emit_write_event_eop(cs,
1101 chip_class,
1102 is_mec,
1103 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1104 0,
1105 EOP_DST_SEL_MEM,
1106 EOP_DATA_SEL_DISCARD,
1107 0, 0,
1108 gfx9_eop_bug_va);
1109 }
1110 }
1111 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1112 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1113 S_0085F0_DB_DEST_BASE_ENA(1);
1114 }
1115 }
1116
1117 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1118 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1119 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1120 }
1121
1122 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1123 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1124 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1125 }
1126
1127 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1128 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1129 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1130 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1131 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1132 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1133 }
1134
1135 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1136 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1137 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1138 }
1139
1140 if (chip_class == GFX9 && flush_cb_db) {
1141 unsigned cb_db_event, tc_flags;
1142
1143 /* Set the CB/DB flush event. */
1144 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1145
1146 /* These are the only allowed combinations. If you need to
1147 * do multiple operations at once, do them separately.
1148 * All operations that invalidate L2 also seem to invalidate
1149 * metadata. Volatile (VOL) and WC flushes are not listed here.
1150 *
1151 * TC | TC_WB = writeback & invalidate L2 & L1
1152 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1153 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1154 * TC | TC_NC = invalidate L2 for MTYPE == NC
1155 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1156 * TCL1 = invalidate L1
1157 */
1158 tc_flags = EVENT_TC_ACTION_ENA |
1159 EVENT_TC_MD_ACTION_ENA;
1160
1161 /* Ideally flush TC together with CB/DB. */
1162 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1163 /* Writeback and invalidate everything in L2 & L1. */
1164 tc_flags = EVENT_TC_ACTION_ENA |
1165 EVENT_TC_WB_ACTION_ENA;
1166
1167
1168 /* Clear the flags. */
1169 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1170 RADV_CMD_FLAG_WB_L2 |
1171 RADV_CMD_FLAG_INV_VCACHE);
1172 }
1173 assert(flush_cnt);
1174 (*flush_cnt)++;
1175
1176 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1177 EOP_DST_SEL_MEM,
1178 EOP_DATA_SEL_VALUE_32BIT,
1179 flush_va, *flush_cnt,
1180 gfx9_eop_bug_va);
1181 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1182 *flush_cnt, 0xffffffff);
1183 }
1184
1185 /* VGT state sync */
1186 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1187 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1188 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1189 }
1190
1191 /* VGT streamout state sync */
1192 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1193 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1194 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1195 }
1196
1197 /* Make sure ME is idle (it executes most packets) before continuing.
1198 * This prevents read-after-write hazards between PFP and ME.
1199 */
1200 if ((cp_coher_cntl ||
1201 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1202 RADV_CMD_FLAG_INV_VCACHE |
1203 RADV_CMD_FLAG_INV_L2 |
1204 RADV_CMD_FLAG_WB_L2))) &&
1205 !is_mec) {
1206 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1207 radeon_emit(cs, 0);
1208 }
1209
1210 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1211 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1212 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1213 cp_coher_cntl |
1214 S_0085F0_TC_ACTION_ENA(1) |
1215 S_0085F0_TCL1_ACTION_ENA(1) |
1216 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1217 cp_coher_cntl = 0;
1218 } else {
1219 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1220 /* WB = write-back
1221 * NC = apply to non-coherent MTYPEs
1222 * (i.e. MTYPE <= 1, which is what we use everywhere)
1223 *
1224 * WB doesn't work without NC.
1225 */
1226 si_emit_acquire_mem(cs, is_mec,
1227 chip_class == GFX9,
1228 cp_coher_cntl |
1229 S_0301F0_TC_WB_ACTION_ENA(1) |
1230 S_0301F0_TC_NC_ACTION_ENA(1));
1231 cp_coher_cntl = 0;
1232 }
1233 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1234 si_emit_acquire_mem(cs, is_mec,
1235 chip_class == GFX9,
1236 cp_coher_cntl |
1237 S_0085F0_TCL1_ACTION_ENA(1));
1238 cp_coher_cntl = 0;
1239 }
1240 }
1241
1242 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1243 * Therefore, it should be last. Done in PFP.
1244 */
1245 if (cp_coher_cntl)
1246 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1247
1248 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1249 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1250 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1251 EVENT_INDEX(0));
1252 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1253 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1254 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1255 EVENT_INDEX(0));
1256 }
1257 }
1258
1259 void
1260 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1261 {
1262 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1263
1264 if (is_compute)
1265 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1266 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1267 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1268 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1269 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1270 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1271 RADV_CMD_FLAG_VGT_FLUSH |
1272 RADV_CMD_FLAG_START_PIPELINE_STATS |
1273 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1274
1275 if (!cmd_buffer->state.flush_bits)
1276 return;
1277
1278 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1279
1280 si_cs_emit_cache_flush(cmd_buffer->cs,
1281 cmd_buffer->device->physical_device->rad_info.chip_class,
1282 &cmd_buffer->gfx9_fence_idx,
1283 cmd_buffer->gfx9_fence_va,
1284 radv_cmd_buffer_uses_mec(cmd_buffer),
1285 cmd_buffer->state.flush_bits,
1286 cmd_buffer->gfx9_eop_bug_va);
1287
1288
1289 if (unlikely(cmd_buffer->device->trace_bo))
1290 radv_cmd_buffer_trace_emit(cmd_buffer);
1291
1292 /* Clear the caches that have been flushed to avoid syncing too much
1293 * when there is some pending active queries.
1294 */
1295 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1296
1297 cmd_buffer->state.flush_bits = 0;
1298
1299 /* If the driver used a compute shader for resetting a query pool, it
1300 * should be finished at this point.
1301 */
1302 cmd_buffer->pending_reset_query = false;
1303 }
1304
1305 /* sets the CP predication state using a boolean stored at va */
1306 void
1307 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1308 bool draw_visible, uint64_t va)
1309 {
1310 uint32_t op = 0;
1311
1312 if (va) {
1313 op = PRED_OP(PREDICATION_OP_BOOL64);
1314
1315 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1316 * zero, all rendering commands are discarded. Otherwise, they
1317 * are discarded if the value is non zero.
1318 */
1319 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1320 PREDICATION_DRAW_NOT_VISIBLE;
1321 }
1322 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1323 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1324 radeon_emit(cmd_buffer->cs, op);
1325 radeon_emit(cmd_buffer->cs, va);
1326 radeon_emit(cmd_buffer->cs, va >> 32);
1327 } else {
1328 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1329 radeon_emit(cmd_buffer->cs, va);
1330 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1331 }
1332 }
1333
1334 /* Set this if you want the 3D engine to wait until CP DMA is done.
1335 * It should be set on the last CP DMA packet. */
1336 #define CP_DMA_SYNC (1 << 0)
1337
1338 /* Set this if the source data was used as a destination in a previous CP DMA
1339 * packet. It's for preventing a read-after-write (RAW) hazard between two
1340 * CP DMA packets. */
1341 #define CP_DMA_RAW_WAIT (1 << 1)
1342 #define CP_DMA_USE_L2 (1 << 2)
1343 #define CP_DMA_CLEAR (1 << 3)
1344
1345 /* Alignment for optimal performance. */
1346 #define SI_CPDMA_ALIGNMENT 32
1347
1348 /* The max number of bytes that can be copied per packet. */
1349 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1350 {
1351 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1352 S_414_BYTE_COUNT_GFX9(~0u) :
1353 S_414_BYTE_COUNT_GFX6(~0u);
1354
1355 /* make it aligned for optimal performance */
1356 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1357 }
1358
1359 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1360 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1361 * clear value.
1362 */
1363 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1364 uint64_t dst_va, uint64_t src_va,
1365 unsigned size, unsigned flags)
1366 {
1367 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1368 uint32_t header = 0, command = 0;
1369
1370 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1371
1372 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1373 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1374 command |= S_414_BYTE_COUNT_GFX9(size);
1375 else
1376 command |= S_414_BYTE_COUNT_GFX6(size);
1377
1378 /* Sync flags. */
1379 if (flags & CP_DMA_SYNC)
1380 header |= S_411_CP_SYNC(1);
1381 else {
1382 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1383 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1384 else
1385 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1386 }
1387
1388 if (flags & CP_DMA_RAW_WAIT)
1389 command |= S_414_RAW_WAIT(1);
1390
1391 /* Src and dst flags. */
1392 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1393 !(flags & CP_DMA_CLEAR) &&
1394 src_va == dst_va)
1395 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1396 else if (flags & CP_DMA_USE_L2)
1397 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1398
1399 if (flags & CP_DMA_CLEAR)
1400 header |= S_411_SRC_SEL(V_411_DATA);
1401 else if (flags & CP_DMA_USE_L2)
1402 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1403
1404 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1405 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1406 radeon_emit(cs, header);
1407 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1408 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1409 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1410 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1411 radeon_emit(cs, command);
1412 } else {
1413 assert(!(flags & CP_DMA_USE_L2));
1414 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1415 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1416 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1417 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1418 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1419 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1420 radeon_emit(cs, command);
1421 }
1422
1423 /* CP DMA is executed in ME, but index buffers are read by PFP.
1424 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1425 * indices. If we wanted to execute CP DMA in PFP, this packet
1426 * should precede it.
1427 */
1428 if (flags & CP_DMA_SYNC) {
1429 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1430 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1431 radeon_emit(cs, 0);
1432 }
1433
1434 /* CP will see the sync flag and wait for all DMAs to complete. */
1435 cmd_buffer->state.dma_is_busy = false;
1436 }
1437
1438 if (unlikely(cmd_buffer->device->trace_bo))
1439 radv_cmd_buffer_trace_emit(cmd_buffer);
1440 }
1441
1442 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1443 unsigned size)
1444 {
1445 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1446 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1447
1448 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1449 aligned_size, CP_DMA_USE_L2);
1450 }
1451
1452 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1453 uint64_t remaining_size, unsigned *flags)
1454 {
1455
1456 /* Flush the caches for the first copy only.
1457 * Also wait for the previous CP DMA operations.
1458 */
1459 if (cmd_buffer->state.flush_bits) {
1460 si_emit_cache_flush(cmd_buffer);
1461 *flags |= CP_DMA_RAW_WAIT;
1462 }
1463
1464 /* Do the synchronization after the last dma, so that all data
1465 * is written to memory.
1466 */
1467 if (byte_count == remaining_size)
1468 *flags |= CP_DMA_SYNC;
1469 }
1470
1471 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1472 {
1473 uint64_t va;
1474 uint32_t offset;
1475 unsigned dma_flags = 0;
1476 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1477 void *ptr;
1478
1479 assert(size < SI_CPDMA_ALIGNMENT);
1480
1481 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1482
1483 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1484 va += offset;
1485
1486 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1487
1488 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1489 dma_flags);
1490 }
1491
1492 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1493 uint64_t src_va, uint64_t dest_va,
1494 uint64_t size)
1495 {
1496 uint64_t main_src_va, main_dest_va;
1497 uint64_t skipped_size = 0, realign_size = 0;
1498
1499 /* Assume that we are not going to sync after the last DMA operation. */
1500 cmd_buffer->state.dma_is_busy = true;
1501
1502 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1503 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1504 /* If the size is not aligned, we must add a dummy copy at the end
1505 * just to align the internal counter. Otherwise, the DMA engine
1506 * would slow down by an order of magnitude for following copies.
1507 */
1508 if (size % SI_CPDMA_ALIGNMENT)
1509 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1510
1511 /* If the copy begins unaligned, we must start copying from the next
1512 * aligned block and the skipped part should be copied after everything
1513 * else has been copied. Only the src alignment matters, not dst.
1514 */
1515 if (src_va % SI_CPDMA_ALIGNMENT) {
1516 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1517 /* The main part will be skipped if the size is too small. */
1518 skipped_size = MIN2(skipped_size, size);
1519 size -= skipped_size;
1520 }
1521 }
1522 main_src_va = src_va + skipped_size;
1523 main_dest_va = dest_va + skipped_size;
1524
1525 while (size) {
1526 unsigned dma_flags = 0;
1527 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1528
1529 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1530 /* DMA operations via L2 are coherent and faster.
1531 * TODO: GFX7-GFX9 should also support this but it
1532 * requires tests/benchmarks.
1533 */
1534 dma_flags |= CP_DMA_USE_L2;
1535 }
1536
1537 si_cp_dma_prepare(cmd_buffer, byte_count,
1538 size + skipped_size + realign_size,
1539 &dma_flags);
1540
1541 dma_flags &= ~CP_DMA_SYNC;
1542
1543 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1544 byte_count, dma_flags);
1545
1546 size -= byte_count;
1547 main_src_va += byte_count;
1548 main_dest_va += byte_count;
1549 }
1550
1551 if (skipped_size) {
1552 unsigned dma_flags = 0;
1553
1554 si_cp_dma_prepare(cmd_buffer, skipped_size,
1555 size + skipped_size + realign_size,
1556 &dma_flags);
1557
1558 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1559 skipped_size, dma_flags);
1560 }
1561 if (realign_size)
1562 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1563 }
1564
1565 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1566 uint64_t size, unsigned value)
1567 {
1568
1569 if (!size)
1570 return;
1571
1572 assert(va % 4 == 0 && size % 4 == 0);
1573
1574 /* Assume that we are not going to sync after the last DMA operation. */
1575 cmd_buffer->state.dma_is_busy = true;
1576
1577 while (size) {
1578 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1579 unsigned dma_flags = CP_DMA_CLEAR;
1580
1581 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1582 /* DMA operations via L2 are coherent and faster.
1583 * TODO: GFX7-GFX9 should also support this but it
1584 * requires tests/benchmarks.
1585 */
1586 dma_flags |= CP_DMA_USE_L2;
1587 }
1588
1589 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1590
1591 /* Emit the clear packet. */
1592 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1593 dma_flags);
1594
1595 size -= byte_count;
1596 va += byte_count;
1597 }
1598 }
1599
1600 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1601 {
1602 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1603 return;
1604
1605 if (!cmd_buffer->state.dma_is_busy)
1606 return;
1607
1608 /* Issue a dummy DMA that copies zero bytes.
1609 *
1610 * The DMA engine will see that there's no work to do and skip this
1611 * DMA request, however, the CP will see the sync flag and still wait
1612 * for all DMAs to complete.
1613 */
1614 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1615
1616 cmd_buffer->state.dma_is_busy = false;
1617 }
1618
1619 /* For MSAA sample positions. */
1620 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1621 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1622 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1623 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1624 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1625
1626 /* For obtaining location coordinates from registers */
1627 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1628 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1629 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1630 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1631
1632 /* 1x MSAA */
1633 static const uint32_t sample_locs_1x =
1634 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1635 static const unsigned max_dist_1x = 0;
1636 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1637
1638 /* 2xMSAA */
1639 static const uint32_t sample_locs_2x =
1640 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1641 static const unsigned max_dist_2x = 4;
1642 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1643
1644 /* 4xMSAA */
1645 static const uint32_t sample_locs_4x =
1646 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1647 static const unsigned max_dist_4x = 6;
1648 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1649
1650 /* 8xMSAA */
1651 static const uint32_t sample_locs_8x[] = {
1652 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1653 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1654 /* The following are unused by hardware, but we emit them to IBs
1655 * instead of multiple SET_CONTEXT_REG packets. */
1656 0,
1657 0,
1658 };
1659 static const unsigned max_dist_8x = 7;
1660 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1661
1662 unsigned radv_get_default_max_sample_dist(int log_samples)
1663 {
1664 unsigned max_dist[] = {
1665 max_dist_1x,
1666 max_dist_2x,
1667 max_dist_4x,
1668 max_dist_8x,
1669 };
1670 return max_dist[log_samples];
1671 }
1672
1673 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1674 {
1675 switch (nr_samples) {
1676 default:
1677 case 1:
1678 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1679 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1680 radeon_emit(cs, centroid_priority_1x >> 32);
1681 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1682 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1683 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1684 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1685 break;
1686 case 2:
1687 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1688 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1689 radeon_emit(cs, centroid_priority_2x >> 32);
1690 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1691 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1692 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1693 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1694 break;
1695 case 4:
1696 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1697 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1698 radeon_emit(cs, centroid_priority_4x >> 32);
1699 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1700 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1701 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1702 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1703 break;
1704 case 8:
1705 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1706 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1707 radeon_emit(cs, centroid_priority_8x >> 32);
1708 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1709 radeon_emit_array(cs, sample_locs_8x, 4);
1710 radeon_emit_array(cs, sample_locs_8x, 4);
1711 radeon_emit_array(cs, sample_locs_8x, 4);
1712 radeon_emit_array(cs, sample_locs_8x, 2);
1713 break;
1714 }
1715 }
1716
1717 static void radv_get_sample_position(struct radv_device *device,
1718 unsigned sample_count,
1719 unsigned sample_index, float *out_value)
1720 {
1721 const uint32_t *sample_locs;
1722
1723 switch (sample_count) {
1724 case 1:
1725 default:
1726 sample_locs = &sample_locs_1x;
1727 break;
1728 case 2:
1729 sample_locs = &sample_locs_2x;
1730 break;
1731 case 4:
1732 sample_locs = &sample_locs_4x;
1733 break;
1734 case 8:
1735 sample_locs = sample_locs_8x;
1736 break;
1737 }
1738
1739 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1740 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1741 }
1742
1743 void radv_device_init_msaa(struct radv_device *device)
1744 {
1745 int i;
1746
1747 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1748
1749 for (i = 0; i < 2; i++)
1750 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1751 for (i = 0; i < 4; i++)
1752 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1753 for (i = 0; i < 8; i++)
1754 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1755 }