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radv: Add Renoir support.
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
92 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
95
96 if (physical_device->rad_info.chip_class >= GFX7) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
100 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
101 S_00B858_SH1_CU_EN(0xffff));
102 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
103 S_00B858_SH1_CU_EN(0xffff));
104 }
105
106 if (physical_device->rad_info.chip_class >= GFX10)
107 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
108
109 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
110 * and is now per pipe, so it should be handled in the
111 * kernel if we want to use something other than the default value,
112 * which is now 0x22f.
113 */
114 if (physical_device->rad_info.chip_class <= GFX6) {
115 /* XXX: This should be:
116 * (number of compute units) * 4 * (waves per simd) - 1 */
117
118 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
119 0x190 /* Default value */);
120 }
121 }
122
123 /* 12.4 fixed-point */
124 static unsigned radv_pack_float_12p4(float x)
125 {
126 return x <= 0 ? 0 :
127 x >= 4096 ? 0xffff : x * 16;
128 }
129
130 static void
131 si_set_raster_config(struct radv_physical_device *physical_device,
132 struct radeon_cmdbuf *cs)
133 {
134 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
135 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
136 unsigned raster_config, raster_config_1;
137
138 ac_get_raster_config(&physical_device->rad_info,
139 &raster_config,
140 &raster_config_1, NULL);
141
142 /* Always use the default config when all backends are enabled
143 * (or when we failed to determine the enabled backends).
144 */
145 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
146 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
147 raster_config);
148 if (physical_device->rad_info.chip_class >= GFX7)
149 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
150 raster_config_1);
151 } else {
152 si_write_harvested_raster_configs(physical_device, cs,
153 raster_config,
154 raster_config_1);
155 }
156 }
157
158 void
159 si_emit_graphics(struct radv_physical_device *physical_device,
160 struct radeon_cmdbuf *cs)
161 {
162 int i;
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (physical_device->has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!physical_device->has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!physical_device->has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
193 if (!physical_device->has_clear_state)
194 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
195 if (physical_device->rad_info.chip_class < GFX7)
196 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
197 S_008A14_CLIP_VTX_REORDER_ENA(1));
198
199 if (!physical_device->has_clear_state)
200 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
201
202 /* CLEAR_STATE doesn't clear these correctly on certain generations.
203 * I don't know why. Deduced by trial and error.
204 */
205 if (physical_device->rad_info.chip_class <= GFX7 || !physical_device->has_clear_state) {
206 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
207 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
208 S_028204_WINDOW_OFFSET_DISABLE(1));
209 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
210 S_028240_WINDOW_OFFSET_DISABLE(1));
211 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
212 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
213 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
214 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
215 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
216 }
217
218 if (!physical_device->has_clear_state) {
219 for (i = 0; i < 16; i++) {
220 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
221 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
222 }
223 }
224
225 if (!physical_device->has_clear_state) {
226 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
227 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
228 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
229 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
230 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
231 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
232 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
233 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
234 }
235
236 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
237 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
238 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
239
240 if (physical_device->rad_info.chip_class >= GFX10) {
241 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
242 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
243 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
244 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
245 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
246 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
247 } else if (physical_device->rad_info.chip_class == GFX9) {
248 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
249 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
250 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
251 } else {
252 /* These registers, when written, also overwrite the
253 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
254 * them. It would be an issue if there was another UMD
255 * changing them.
256 */
257 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
258 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
259 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
260 }
261
262 if (physical_device->rad_info.chip_class >= GFX7) {
263 if (physical_device->rad_info.chip_class >= GFX10) {
264 /* Logical CUs 16 - 31 */
265 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
266 3, S_00B404_CU_EN(0xffff));
267 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
268 3, S_00B104_CU_EN(0xffff));
269 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
270 3, S_00B004_CU_EN(0xffff));
271 }
272
273 if (physical_device->rad_info.chip_class >= GFX9) {
274 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
275 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
276 } else {
277 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
278 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
279 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
280 S_00B41C_WAVE_LIMIT(0x3F));
281 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
282 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
283 /* If this is 0, Bonaire can hang even if GS isn't being used.
284 * Other chips are unaffected. These are suboptimal values,
285 * but we don't use on-chip GS.
286 */
287 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
288 S_028A44_ES_VERTS_PER_SUBGRP(64) |
289 S_028A44_GS_PRIMS_PER_SUBGRP(4));
290 }
291
292 /* Compute LATE_ALLOC_VS.LIMIT. */
293 unsigned num_cu_per_sh = physical_device->rad_info.num_good_cu_per_sh;
294 unsigned late_alloc_limit; /* The limit is per SH. */
295
296 if (physical_device->rad_info.family == CHIP_KABINI) {
297 late_alloc_limit = 0; /* Potential hang on Kabini. */
298 } else if (num_cu_per_sh <= 4) {
299 /* Too few available compute units per SH. Disallowing
300 * VS to run on one CU could hurt us more than late VS
301 * allocation would help.
302 *
303 * 2 is the highest safe number that allows us to keep
304 * all CUs enabled.
305 */
306 late_alloc_limit = 2;
307 } else {
308 /* This is a good initial value, allowing 1 late_alloc
309 * wave per SIMD on num_cu - 2.
310 */
311 late_alloc_limit = (num_cu_per_sh - 2) * 4;
312 }
313
314 unsigned late_alloc_limit_gs = late_alloc_limit;
315 unsigned cu_mask_vs = 0xffff;
316 unsigned cu_mask_gs = 0xffff;
317
318 if (late_alloc_limit > 2) {
319 if (physical_device->rad_info.chip_class >= GFX10) {
320 /* CU2 & CU3 disabled because of the dual CU design */
321 cu_mask_vs = 0xfff3;
322 cu_mask_gs = 0xfff3; /* NGG only */
323 } else {
324 cu_mask_vs = 0xfffe; /* 1 CU disabled */
325 }
326 }
327
328 /* Don't use late alloc for NGG on Navi14 due to a hw bug. */
329 if (physical_device->rad_info.family == CHIP_NAVI14) {
330 late_alloc_limit_gs = 0;
331 cu_mask_gs = 0xffff;
332 }
333
334 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
335 3, S_00B118_CU_EN(cu_mask_vs) |
336 S_00B118_WAVE_LIMIT(0x3F));
337 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
338 S_00B11C_LIMIT(late_alloc_limit));
339
340 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
341 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
342
343 if (physical_device->rad_info.chip_class >= GFX10) {
344 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
345 3, S_00B204_CU_EN(0xffff) |
346 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit_gs));
347 }
348
349 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
350 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
351 }
352
353 if (physical_device->rad_info.chip_class >= GFX10) {
354 /* Break up a pixel wave if it contains deallocs for more than
355 * half the parameter cache.
356 *
357 * To avoid a deadlock where pixel waves aren't launched
358 * because they're waiting for more pixels while the frontend
359 * is stuck waiting for PC space, the maximum allowed value is
360 * the size of the PC minus the largest possible allocation for
361 * a single primitive shader subgroup.
362 */
363 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
364 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
365 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
366 radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
367 physical_device->rad_info.pa_sc_tile_steering_override);
368 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
369 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
370 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
371 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
372 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
373 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
374 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
375 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
376
377 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
378 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
379 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
380 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
381 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
382 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
383 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
384 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
385 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
386 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
387
388 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
389 S_00B0C0_SOFT_GROUPING_EN(1) |
390 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
391 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
392
393 if (physical_device->rad_info.family == CHIP_NAVI10 ||
394 physical_device->rad_info.family == CHIP_NAVI12 ||
395 physical_device->rad_info.family == CHIP_NAVI14) {
396 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
397 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
398 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
399 }
400
401 /* TODO: For culling, replace 128 with 256. */
402 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
403 S_030980_OVERSUB_EN(1) |
404 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
405 }
406
407 if (physical_device->rad_info.chip_class >= GFX8) {
408 uint32_t vgt_tess_distribution;
409
410 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
411 S_028B50_ACCUM_TRI(11) |
412 S_028B50_ACCUM_QUAD(11) |
413 S_028B50_DONUT_SPLIT(16);
414
415 if (physical_device->rad_info.family == CHIP_FIJI ||
416 physical_device->rad_info.family >= CHIP_POLARIS10)
417 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
418
419 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
420 vgt_tess_distribution);
421 } else if (!physical_device->has_clear_state) {
422 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
423 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
424 }
425
426 if (physical_device->rad_info.chip_class >= GFX9) {
427 unsigned num_se = physical_device->rad_info.max_se;
428 unsigned pc_lines = 0;
429 unsigned max_alloc_count = 0;
430
431 switch (physical_device->rad_info.family) {
432 case CHIP_VEGA10:
433 case CHIP_VEGA12:
434 case CHIP_VEGA20:
435 pc_lines = 4096;
436 break;
437 case CHIP_RAVEN:
438 case CHIP_RAVEN2:
439 case CHIP_RENOIR:
440 case CHIP_NAVI10:
441 case CHIP_NAVI12:
442 pc_lines = 1024;
443 break;
444 case CHIP_NAVI14:
445 pc_lines = 512;
446 break;
447 default:
448 assert(0);
449 }
450
451 if (physical_device->rad_info.chip_class >= GFX10) {
452 max_alloc_count = pc_lines / 3;
453 } else {
454 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
455 }
456
457 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
458 S_028C48_MAX_ALLOC_COUNT(max_alloc_count - 1) |
459 S_028C48_MAX_PRIM_PER_BATCH(1023));
460 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
461 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
462 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
463 }
464
465 unsigned tmp = (unsigned)(1.0 * 8.0);
466 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
467 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
468 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
469 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
470 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
471
472 if (!physical_device->has_clear_state) {
473 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
474 S_028004_ZPASS_INCREMENT_DISABLE(1));
475 }
476
477 /* Enable the Polaris small primitive filter control.
478 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
479 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
480 * and AMDVLK doesn't have a workaround as well.
481 */
482 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
483 unsigned small_prim_filter_cntl =
484 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
485 /* Workaround for a hw line bug. */
486 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
487
488 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
489 small_prim_filter_cntl);
490 }
491
492 si_emit_compute(physical_device, cs);
493 }
494
495 void
496 cik_create_gfx_config(struct radv_device *device)
497 {
498 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
499 if (!cs)
500 return;
501
502 si_emit_graphics(device->physical_device, cs);
503
504 while (cs->cdw & 7) {
505 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
506 radeon_emit(cs, 0x80000000);
507 else
508 radeon_emit(cs, 0xffff1000);
509 }
510
511 device->gfx_init = device->ws->buffer_create(device->ws,
512 cs->cdw * 4, 4096,
513 RADEON_DOMAIN_GTT,
514 RADEON_FLAG_CPU_ACCESS|
515 RADEON_FLAG_NO_INTERPROCESS_SHARING |
516 RADEON_FLAG_READ_ONLY,
517 RADV_BO_PRIORITY_CS);
518 if (!device->gfx_init)
519 goto fail;
520
521 void *map = device->ws->buffer_map(device->gfx_init);
522 if (!map) {
523 device->ws->buffer_destroy(device->gfx_init);
524 device->gfx_init = NULL;
525 goto fail;
526 }
527 memcpy(map, cs->buf, cs->cdw * 4);
528
529 device->ws->buffer_unmap(device->gfx_init);
530 device->gfx_init_size_dw = cs->cdw;
531 fail:
532 device->ws->cs_destroy(cs);
533 }
534
535 static void
536 get_viewport_xform(const VkViewport *viewport,
537 float scale[3], float translate[3])
538 {
539 float x = viewport->x;
540 float y = viewport->y;
541 float half_width = 0.5f * viewport->width;
542 float half_height = 0.5f * viewport->height;
543 double n = viewport->minDepth;
544 double f = viewport->maxDepth;
545
546 scale[0] = half_width;
547 translate[0] = half_width + x;
548 scale[1] = half_height;
549 translate[1] = half_height + y;
550
551 scale[2] = (f - n);
552 translate[2] = n;
553 }
554
555 void
556 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
557 int count, const VkViewport *viewports)
558 {
559 int i;
560
561 assert(count);
562 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
563 first_vp * 4 * 6, count * 6);
564
565 for (i = 0; i < count; i++) {
566 float scale[3], translate[3];
567
568
569 get_viewport_xform(&viewports[i], scale, translate);
570 radeon_emit(cs, fui(scale[0]));
571 radeon_emit(cs, fui(translate[0]));
572 radeon_emit(cs, fui(scale[1]));
573 radeon_emit(cs, fui(translate[1]));
574 radeon_emit(cs, fui(scale[2]));
575 radeon_emit(cs, fui(translate[2]));
576 }
577
578 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
579 first_vp * 4 * 2, count * 2);
580 for (i = 0; i < count; i++) {
581 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
582 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
583 radeon_emit(cs, fui(zmin));
584 radeon_emit(cs, fui(zmax));
585 }
586 }
587
588 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
589 {
590 float scale[3], translate[3];
591 VkRect2D rect;
592
593 get_viewport_xform(viewport, scale, translate);
594
595 rect.offset.x = translate[0] - fabs(scale[0]);
596 rect.offset.y = translate[1] - fabs(scale[1]);
597 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
598 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
599
600 return rect;
601 }
602
603 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
604 VkRect2D ret;
605 ret.offset.x = MAX2(a->offset.x, b->offset.x);
606 ret.offset.y = MAX2(a->offset.y, b->offset.y);
607 ret.extent.width = MIN2(a->offset.x + a->extent.width,
608 b->offset.x + b->extent.width) - ret.offset.x;
609 ret.extent.height = MIN2(a->offset.y + a->extent.height,
610 b->offset.y + b->extent.height) - ret.offset.y;
611 return ret;
612 }
613
614 void
615 si_write_scissors(struct radeon_cmdbuf *cs, int first,
616 int count, const VkRect2D *scissors,
617 const VkViewport *viewports, bool can_use_guardband)
618 {
619 int i;
620 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
621 const float max_range = 32767.0f;
622 if (!count)
623 return;
624
625 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
626 for (i = 0; i < count; i++) {
627 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
628 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
629
630 get_viewport_xform(viewports + i, scale, translate);
631 scale[0] = fabsf(scale[0]);
632 scale[1] = fabsf(scale[1]);
633
634 if (scale[0] < 0.5)
635 scale[0] = 0.5;
636 if (scale[1] < 0.5)
637 scale[1] = 0.5;
638
639 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
640 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
641
642 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
643 S_028250_TL_Y(scissor.offset.y) |
644 S_028250_WINDOW_OFFSET_DISABLE(1));
645 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
646 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
647 }
648 if (!can_use_guardband) {
649 guardband_x = 1.0;
650 guardband_y = 1.0;
651 }
652
653 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
654 radeon_emit(cs, fui(guardband_y));
655 radeon_emit(cs, fui(1.0));
656 radeon_emit(cs, fui(guardband_x));
657 radeon_emit(cs, fui(1.0));
658 }
659
660 static inline unsigned
661 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
662 {
663 if (num == 0)
664 return 0;
665
666 if (info->incr == 0)
667 return 0;
668
669 if (num < info->min)
670 return 0;
671
672 return 1 + ((num - info->min) / info->incr);
673 }
674
675 uint32_t
676 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
677 bool instanced_draw, bool indirect_draw,
678 bool count_from_stream_output,
679 uint32_t draw_vertex_count)
680 {
681 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
682 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
683 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
684 const unsigned max_primgroup_in_wave = 2;
685 /* SWITCH_ON_EOP(0) is always preferable. */
686 bool wd_switch_on_eop = false;
687 bool ia_switch_on_eop = false;
688 bool ia_switch_on_eoi = false;
689 bool partial_vs_wave = false;
690 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
691 bool multi_instances_smaller_than_primgroup;
692
693 multi_instances_smaller_than_primgroup = indirect_draw;
694 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
695 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
696 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
697 multi_instances_smaller_than_primgroup = true;
698 }
699
700 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
701 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
702
703 if (chip_class >= GFX7) {
704 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
705
706 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
707 * We don't know that for indirect drawing, so treat it as
708 * always problematic. */
709 if (family == CHIP_HAWAII &&
710 (instanced_draw || indirect_draw))
711 wd_switch_on_eop = true;
712
713 /* Performance recommendation for 4 SE Gfx7-8 parts if
714 * instances are smaller than a primgroup.
715 * Assume indirect draws always use small instances.
716 * This is needed for good VS wave utilization.
717 */
718 if (chip_class <= GFX8 &&
719 info->max_se == 4 &&
720 multi_instances_smaller_than_primgroup)
721 wd_switch_on_eop = true;
722
723 /* Required on GFX7 and later. */
724 if (info->max_se > 2 && !wd_switch_on_eop)
725 ia_switch_on_eoi = true;
726
727 /* Required by Hawaii and, for some special cases, by GFX8. */
728 if (ia_switch_on_eoi &&
729 (family == CHIP_HAWAII ||
730 (chip_class == GFX8 &&
731 /* max primgroup in wave is always 2 - leave this for documentation */
732 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
733 partial_vs_wave = true;
734
735 /* Instancing bug on Bonaire. */
736 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
737 (instanced_draw || indirect_draw))
738 partial_vs_wave = true;
739
740 /* Hardware requirement when drawing primitives from a stream
741 * output buffer.
742 */
743 if (count_from_stream_output)
744 wd_switch_on_eop = true;
745
746 /* If the WD switch is false, the IA switch must be false too. */
747 assert(wd_switch_on_eop || !ia_switch_on_eop);
748 }
749 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
750 if (chip_class <= GFX8 && ia_switch_on_eoi)
751 partial_es_wave = true;
752
753 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
754 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
755 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
756 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
757 */
758 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
759 bool set_vgt_flush = indirect_draw;
760 if (!set_vgt_flush && instanced_draw) {
761 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
762 if (num_prims <= 1)
763 set_vgt_flush = true;
764 }
765 if (set_vgt_flush)
766 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
767 }
768 }
769
770 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
771 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
772 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
773 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
774 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
775 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
776
777 }
778
779 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
780 enum chip_class chip_class,
781 bool is_mec,
782 unsigned event, unsigned event_flags,
783 unsigned dst_sel, unsigned data_sel,
784 uint64_t va,
785 uint32_t new_fence,
786 uint64_t gfx9_eop_bug_va)
787 {
788 unsigned op = EVENT_TYPE(event) |
789 EVENT_INDEX(event == V_028A90_CS_DONE ||
790 event == V_028A90_PS_DONE ? 6 : 5) |
791 event_flags;
792 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
793 unsigned sel = EOP_DST_SEL(dst_sel) |
794 EOP_DATA_SEL(data_sel);
795
796 /* Wait for write confirmation before writing data, but don't send
797 * an interrupt. */
798 if (data_sel != EOP_DATA_SEL_DISCARD)
799 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
800
801 if (chip_class >= GFX9 || is_gfx8_mec) {
802 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
803 * counters) must immediately precede every timestamp event to
804 * prevent a GPU hang on GFX9.
805 */
806 if (chip_class == GFX9 && !is_mec) {
807 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
808 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
809 radeon_emit(cs, gfx9_eop_bug_va);
810 radeon_emit(cs, gfx9_eop_bug_va >> 32);
811 }
812
813 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
814 radeon_emit(cs, op);
815 radeon_emit(cs, sel);
816 radeon_emit(cs, va); /* address lo */
817 radeon_emit(cs, va >> 32); /* address hi */
818 radeon_emit(cs, new_fence); /* immediate data lo */
819 radeon_emit(cs, 0); /* immediate data hi */
820 if (!is_gfx8_mec)
821 radeon_emit(cs, 0); /* unused */
822 } else {
823 if (chip_class == GFX7 ||
824 chip_class == GFX8) {
825 /* Two EOP events are required to make all engines go idle
826 * (and optional cache flushes executed) before the timestamp
827 * is written.
828 */
829 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
830 radeon_emit(cs, op);
831 radeon_emit(cs, va);
832 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
833 radeon_emit(cs, 0); /* immediate data */
834 radeon_emit(cs, 0); /* unused */
835 }
836
837 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
838 radeon_emit(cs, op);
839 radeon_emit(cs, va);
840 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
841 radeon_emit(cs, new_fence); /* immediate data */
842 radeon_emit(cs, 0); /* unused */
843 }
844 }
845
846 void
847 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
848 uint32_t ref, uint32_t mask)
849 {
850 assert(op == WAIT_REG_MEM_EQUAL ||
851 op == WAIT_REG_MEM_NOT_EQUAL ||
852 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
853
854 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
855 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
856 radeon_emit(cs, va);
857 radeon_emit(cs, va >> 32);
858 radeon_emit(cs, ref); /* reference value */
859 radeon_emit(cs, mask); /* mask */
860 radeon_emit(cs, 4); /* poll interval */
861 }
862
863 static void
864 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
865 bool is_mec,
866 bool is_gfx9,
867 unsigned cp_coher_cntl)
868 {
869 if (is_mec || is_gfx9) {
870 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
871 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
872 PKT3_SHADER_TYPE_S(is_mec));
873 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
874 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
875 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
876 radeon_emit(cs, 0); /* CP_COHER_BASE */
877 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
878 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
879 } else {
880 /* ACQUIRE_MEM is only required on a compute ring. */
881 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
882 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
883 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
884 radeon_emit(cs, 0); /* CP_COHER_BASE */
885 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
886 }
887 }
888
889 static void
890 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
891 enum chip_class chip_class,
892 uint32_t *flush_cnt,
893 uint64_t flush_va,
894 bool is_mec,
895 enum radv_cmd_flush_bits flush_bits,
896 uint64_t gfx9_eop_bug_va)
897 {
898 uint32_t gcr_cntl = 0;
899 unsigned cb_db_event = 0;
900
901 /* We don't need these. */
902 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
903
904 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
905 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
906 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
907 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
908 * to FORWARD when both L1 and L2 are written out (WB or INV).
909 */
910 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
911 }
912 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
913 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
914 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
915 /* Writeback and invalidate everything in L2. */
916 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
917 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
918 /* Writeback but do not invalidate. */
919 gcr_cntl |= S_586_GL2_WB(1);
920 }
921
922 /* TODO: Implement this new flag for GFX9+.
923 if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
924 gcr_cntl |= S_586_GLM_INV(1);
925 */
926
927 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
928 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
929 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
930 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
931 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
932 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
933 EVENT_INDEX(0));
934 }
935
936 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
937 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
938 /* Flush HTILE. Will wait for idle later. */
939 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
940 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
941 EVENT_INDEX(0));
942 }
943
944 /* First flush CB/DB, then L1/L2. */
945 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
946
947 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
948 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
949 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
950 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
951 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
952 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
953 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
954 } else {
955 assert(0);
956 }
957 } else {
958 /* Wait for graphics shaders to go idle if requested. */
959 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
960 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
961 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
962 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
963 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
964 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
965 }
966 }
967
968 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
969 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
970 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
971 }
972
973 if (cb_db_event) {
974 /* CB/DB flush and invalidate (or possibly just a wait for a
975 * meta flush) via RELEASE_MEM.
976 *
977 * Combine this with other cache flushes when possible; this
978 * requires affected shaders to be idle, so do it after the
979 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
980 * implied).
981 */
982 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
983 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
984 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
985 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
986 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
987 assert(G_586_GL2_US(gcr_cntl) == 0);
988 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
989 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
990 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
991 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
992 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
993
994 gcr_cntl &= C_586_GLM_WB &
995 C_586_GLM_INV &
996 C_586_GLV_INV &
997 C_586_GL1_INV &
998 C_586_GL2_INV &
999 C_586_GL2_WB; /* keep SEQ */
1000
1001 assert(flush_cnt);
1002 (*flush_cnt)++;
1003
1004 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
1005 S_490_GLM_WB(glm_wb) |
1006 S_490_GLM_INV(glm_inv) |
1007 S_490_GLV_INV(glv_inv) |
1008 S_490_GL1_INV(gl1_inv) |
1009 S_490_GL2_INV(gl2_inv) |
1010 S_490_GL2_WB(gl2_wb) |
1011 S_490_SEQ(gcr_seq),
1012 EOP_DST_SEL_MEM,
1013 EOP_DATA_SEL_VALUE_32BIT,
1014 flush_va, *flush_cnt,
1015 gfx9_eop_bug_va);
1016
1017 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1018 *flush_cnt, 0xffffffff);
1019 }
1020
1021 /* VGT state sync */
1022 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1023 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1024 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1025 }
1026
1027 /* Ignore fields that only modify the behavior of other fields. */
1028 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1029 /* Flush caches and wait for the caches to assert idle.
1030 * The cache flush is executed in the ME, but the PFP waits
1031 * for completion.
1032 */
1033 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1034 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1035 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1036 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1037 radeon_emit(cs, 0); /* CP_COHER_BASE */
1038 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1039 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1040 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1041 } else if ((cb_db_event ||
1042 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1043 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1044 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1045 && !is_mec) {
1046 /* We need to ensure that PFP waits as well. */
1047 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1048 radeon_emit(cs, 0);
1049 }
1050
1051 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1052 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1053 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1054 EVENT_INDEX(0));
1055 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1056 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1057 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1058 EVENT_INDEX(0));
1059 }
1060 }
1061
1062 void
1063 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1064 enum chip_class chip_class,
1065 uint32_t *flush_cnt,
1066 uint64_t flush_va,
1067 bool is_mec,
1068 enum radv_cmd_flush_bits flush_bits,
1069 uint64_t gfx9_eop_bug_va)
1070 {
1071 unsigned cp_coher_cntl = 0;
1072 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1073 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1074
1075 if (chip_class >= GFX10) {
1076 /* GFX10 cache flush handling is quite different. */
1077 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1078 is_mec, flush_bits, gfx9_eop_bug_va);
1079 return;
1080 }
1081
1082 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1083 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1084 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1085 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1086
1087 if (chip_class <= GFX8) {
1088 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1089 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1090 S_0085F0_CB0_DEST_BASE_ENA(1) |
1091 S_0085F0_CB1_DEST_BASE_ENA(1) |
1092 S_0085F0_CB2_DEST_BASE_ENA(1) |
1093 S_0085F0_CB3_DEST_BASE_ENA(1) |
1094 S_0085F0_CB4_DEST_BASE_ENA(1) |
1095 S_0085F0_CB5_DEST_BASE_ENA(1) |
1096 S_0085F0_CB6_DEST_BASE_ENA(1) |
1097 S_0085F0_CB7_DEST_BASE_ENA(1);
1098
1099 /* Necessary for DCC */
1100 if (chip_class >= GFX8) {
1101 si_cs_emit_write_event_eop(cs,
1102 chip_class,
1103 is_mec,
1104 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1105 0,
1106 EOP_DST_SEL_MEM,
1107 EOP_DATA_SEL_DISCARD,
1108 0, 0,
1109 gfx9_eop_bug_va);
1110 }
1111 }
1112 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1113 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1114 S_0085F0_DB_DEST_BASE_ENA(1);
1115 }
1116 }
1117
1118 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1119 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1120 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1121 }
1122
1123 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1124 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1125 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1126 }
1127
1128 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1129 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1130 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1131 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1132 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1133 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1134 }
1135
1136 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1137 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1138 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1139 }
1140
1141 if (chip_class == GFX9 && flush_cb_db) {
1142 unsigned cb_db_event, tc_flags;
1143
1144 /* Set the CB/DB flush event. */
1145 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1146
1147 /* These are the only allowed combinations. If you need to
1148 * do multiple operations at once, do them separately.
1149 * All operations that invalidate L2 also seem to invalidate
1150 * metadata. Volatile (VOL) and WC flushes are not listed here.
1151 *
1152 * TC | TC_WB = writeback & invalidate L2 & L1
1153 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1154 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1155 * TC | TC_NC = invalidate L2 for MTYPE == NC
1156 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1157 * TCL1 = invalidate L1
1158 */
1159 tc_flags = EVENT_TC_ACTION_ENA |
1160 EVENT_TC_MD_ACTION_ENA;
1161
1162 /* Ideally flush TC together with CB/DB. */
1163 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1164 /* Writeback and invalidate everything in L2 & L1. */
1165 tc_flags = EVENT_TC_ACTION_ENA |
1166 EVENT_TC_WB_ACTION_ENA;
1167
1168
1169 /* Clear the flags. */
1170 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1171 RADV_CMD_FLAG_WB_L2 |
1172 RADV_CMD_FLAG_INV_VCACHE);
1173 }
1174 assert(flush_cnt);
1175 (*flush_cnt)++;
1176
1177 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1178 EOP_DST_SEL_MEM,
1179 EOP_DATA_SEL_VALUE_32BIT,
1180 flush_va, *flush_cnt,
1181 gfx9_eop_bug_va);
1182 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1183 *flush_cnt, 0xffffffff);
1184 }
1185
1186 /* VGT state sync */
1187 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1188 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1189 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1190 }
1191
1192 /* VGT streamout state sync */
1193 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1194 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1195 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1196 }
1197
1198 /* Make sure ME is idle (it executes most packets) before continuing.
1199 * This prevents read-after-write hazards between PFP and ME.
1200 */
1201 if ((cp_coher_cntl ||
1202 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1203 RADV_CMD_FLAG_INV_VCACHE |
1204 RADV_CMD_FLAG_INV_L2 |
1205 RADV_CMD_FLAG_WB_L2))) &&
1206 !is_mec) {
1207 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1208 radeon_emit(cs, 0);
1209 }
1210
1211 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1212 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1213 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1214 cp_coher_cntl |
1215 S_0085F0_TC_ACTION_ENA(1) |
1216 S_0085F0_TCL1_ACTION_ENA(1) |
1217 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1218 cp_coher_cntl = 0;
1219 } else {
1220 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1221 /* WB = write-back
1222 * NC = apply to non-coherent MTYPEs
1223 * (i.e. MTYPE <= 1, which is what we use everywhere)
1224 *
1225 * WB doesn't work without NC.
1226 */
1227 si_emit_acquire_mem(cs, is_mec,
1228 chip_class == GFX9,
1229 cp_coher_cntl |
1230 S_0301F0_TC_WB_ACTION_ENA(1) |
1231 S_0301F0_TC_NC_ACTION_ENA(1));
1232 cp_coher_cntl = 0;
1233 }
1234 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1235 si_emit_acquire_mem(cs, is_mec,
1236 chip_class == GFX9,
1237 cp_coher_cntl |
1238 S_0085F0_TCL1_ACTION_ENA(1));
1239 cp_coher_cntl = 0;
1240 }
1241 }
1242
1243 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1244 * Therefore, it should be last. Done in PFP.
1245 */
1246 if (cp_coher_cntl)
1247 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1248
1249 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1250 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1251 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1252 EVENT_INDEX(0));
1253 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1254 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1255 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1256 EVENT_INDEX(0));
1257 }
1258 }
1259
1260 void
1261 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1262 {
1263 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1264
1265 if (is_compute)
1266 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1267 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1268 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1269 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1270 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1271 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1272 RADV_CMD_FLAG_VGT_FLUSH |
1273 RADV_CMD_FLAG_START_PIPELINE_STATS |
1274 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1275
1276 if (!cmd_buffer->state.flush_bits)
1277 return;
1278
1279 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1280
1281 si_cs_emit_cache_flush(cmd_buffer->cs,
1282 cmd_buffer->device->physical_device->rad_info.chip_class,
1283 &cmd_buffer->gfx9_fence_idx,
1284 cmd_buffer->gfx9_fence_va,
1285 radv_cmd_buffer_uses_mec(cmd_buffer),
1286 cmd_buffer->state.flush_bits,
1287 cmd_buffer->gfx9_eop_bug_va);
1288
1289
1290 if (unlikely(cmd_buffer->device->trace_bo))
1291 radv_cmd_buffer_trace_emit(cmd_buffer);
1292
1293 /* Clear the caches that have been flushed to avoid syncing too much
1294 * when there is some pending active queries.
1295 */
1296 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1297
1298 cmd_buffer->state.flush_bits = 0;
1299
1300 /* If the driver used a compute shader for resetting a query pool, it
1301 * should be finished at this point.
1302 */
1303 cmd_buffer->pending_reset_query = false;
1304 }
1305
1306 /* sets the CP predication state using a boolean stored at va */
1307 void
1308 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1309 bool draw_visible, uint64_t va)
1310 {
1311 uint32_t op = 0;
1312
1313 if (va) {
1314 op = PRED_OP(PREDICATION_OP_BOOL64);
1315
1316 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1317 * zero, all rendering commands are discarded. Otherwise, they
1318 * are discarded if the value is non zero.
1319 */
1320 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1321 PREDICATION_DRAW_NOT_VISIBLE;
1322 }
1323 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1324 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1325 radeon_emit(cmd_buffer->cs, op);
1326 radeon_emit(cmd_buffer->cs, va);
1327 radeon_emit(cmd_buffer->cs, va >> 32);
1328 } else {
1329 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1330 radeon_emit(cmd_buffer->cs, va);
1331 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1332 }
1333 }
1334
1335 /* Set this if you want the 3D engine to wait until CP DMA is done.
1336 * It should be set on the last CP DMA packet. */
1337 #define CP_DMA_SYNC (1 << 0)
1338
1339 /* Set this if the source data was used as a destination in a previous CP DMA
1340 * packet. It's for preventing a read-after-write (RAW) hazard between two
1341 * CP DMA packets. */
1342 #define CP_DMA_RAW_WAIT (1 << 1)
1343 #define CP_DMA_USE_L2 (1 << 2)
1344 #define CP_DMA_CLEAR (1 << 3)
1345
1346 /* Alignment for optimal performance. */
1347 #define SI_CPDMA_ALIGNMENT 32
1348
1349 /* The max number of bytes that can be copied per packet. */
1350 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1351 {
1352 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1353 S_414_BYTE_COUNT_GFX9(~0u) :
1354 S_414_BYTE_COUNT_GFX6(~0u);
1355
1356 /* make it aligned for optimal performance */
1357 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1358 }
1359
1360 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1361 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1362 * clear value.
1363 */
1364 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1365 uint64_t dst_va, uint64_t src_va,
1366 unsigned size, unsigned flags)
1367 {
1368 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1369 uint32_t header = 0, command = 0;
1370
1371 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1372
1373 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1374 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1375 command |= S_414_BYTE_COUNT_GFX9(size);
1376 else
1377 command |= S_414_BYTE_COUNT_GFX6(size);
1378
1379 /* Sync flags. */
1380 if (flags & CP_DMA_SYNC)
1381 header |= S_411_CP_SYNC(1);
1382 else {
1383 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1384 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1385 else
1386 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1387 }
1388
1389 if (flags & CP_DMA_RAW_WAIT)
1390 command |= S_414_RAW_WAIT(1);
1391
1392 /* Src and dst flags. */
1393 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1394 !(flags & CP_DMA_CLEAR) &&
1395 src_va == dst_va)
1396 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1397 else if (flags & CP_DMA_USE_L2)
1398 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1399
1400 if (flags & CP_DMA_CLEAR)
1401 header |= S_411_SRC_SEL(V_411_DATA);
1402 else if (flags & CP_DMA_USE_L2)
1403 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1404
1405 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1406 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1407 radeon_emit(cs, header);
1408 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1409 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1410 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1411 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1412 radeon_emit(cs, command);
1413 } else {
1414 assert(!(flags & CP_DMA_USE_L2));
1415 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1416 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1417 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1418 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1419 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1420 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1421 radeon_emit(cs, command);
1422 }
1423
1424 /* CP DMA is executed in ME, but index buffers are read by PFP.
1425 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1426 * indices. If we wanted to execute CP DMA in PFP, this packet
1427 * should precede it.
1428 */
1429 if (flags & CP_DMA_SYNC) {
1430 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1431 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1432 radeon_emit(cs, 0);
1433 }
1434
1435 /* CP will see the sync flag and wait for all DMAs to complete. */
1436 cmd_buffer->state.dma_is_busy = false;
1437 }
1438
1439 if (unlikely(cmd_buffer->device->trace_bo))
1440 radv_cmd_buffer_trace_emit(cmd_buffer);
1441 }
1442
1443 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1444 unsigned size)
1445 {
1446 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1447 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1448
1449 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1450 aligned_size, CP_DMA_USE_L2);
1451 }
1452
1453 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1454 uint64_t remaining_size, unsigned *flags)
1455 {
1456
1457 /* Flush the caches for the first copy only.
1458 * Also wait for the previous CP DMA operations.
1459 */
1460 if (cmd_buffer->state.flush_bits) {
1461 si_emit_cache_flush(cmd_buffer);
1462 *flags |= CP_DMA_RAW_WAIT;
1463 }
1464
1465 /* Do the synchronization after the last dma, so that all data
1466 * is written to memory.
1467 */
1468 if (byte_count == remaining_size)
1469 *flags |= CP_DMA_SYNC;
1470 }
1471
1472 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1473 {
1474 uint64_t va;
1475 uint32_t offset;
1476 unsigned dma_flags = 0;
1477 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1478 void *ptr;
1479
1480 assert(size < SI_CPDMA_ALIGNMENT);
1481
1482 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1483
1484 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1485 va += offset;
1486
1487 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1488
1489 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1490 dma_flags);
1491 }
1492
1493 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1494 uint64_t src_va, uint64_t dest_va,
1495 uint64_t size)
1496 {
1497 uint64_t main_src_va, main_dest_va;
1498 uint64_t skipped_size = 0, realign_size = 0;
1499
1500 /* Assume that we are not going to sync after the last DMA operation. */
1501 cmd_buffer->state.dma_is_busy = true;
1502
1503 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1504 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1505 /* If the size is not aligned, we must add a dummy copy at the end
1506 * just to align the internal counter. Otherwise, the DMA engine
1507 * would slow down by an order of magnitude for following copies.
1508 */
1509 if (size % SI_CPDMA_ALIGNMENT)
1510 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1511
1512 /* If the copy begins unaligned, we must start copying from the next
1513 * aligned block and the skipped part should be copied after everything
1514 * else has been copied. Only the src alignment matters, not dst.
1515 */
1516 if (src_va % SI_CPDMA_ALIGNMENT) {
1517 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1518 /* The main part will be skipped if the size is too small. */
1519 skipped_size = MIN2(skipped_size, size);
1520 size -= skipped_size;
1521 }
1522 }
1523 main_src_va = src_va + skipped_size;
1524 main_dest_va = dest_va + skipped_size;
1525
1526 while (size) {
1527 unsigned dma_flags = 0;
1528 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1529
1530 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1531 /* DMA operations via L2 are coherent and faster.
1532 * TODO: GFX7-GFX9 should also support this but it
1533 * requires tests/benchmarks.
1534 */
1535 dma_flags |= CP_DMA_USE_L2;
1536 }
1537
1538 si_cp_dma_prepare(cmd_buffer, byte_count,
1539 size + skipped_size + realign_size,
1540 &dma_flags);
1541
1542 dma_flags &= ~CP_DMA_SYNC;
1543
1544 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1545 byte_count, dma_flags);
1546
1547 size -= byte_count;
1548 main_src_va += byte_count;
1549 main_dest_va += byte_count;
1550 }
1551
1552 if (skipped_size) {
1553 unsigned dma_flags = 0;
1554
1555 si_cp_dma_prepare(cmd_buffer, skipped_size,
1556 size + skipped_size + realign_size,
1557 &dma_flags);
1558
1559 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1560 skipped_size, dma_flags);
1561 }
1562 if (realign_size)
1563 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1564 }
1565
1566 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1567 uint64_t size, unsigned value)
1568 {
1569
1570 if (!size)
1571 return;
1572
1573 assert(va % 4 == 0 && size % 4 == 0);
1574
1575 /* Assume that we are not going to sync after the last DMA operation. */
1576 cmd_buffer->state.dma_is_busy = true;
1577
1578 while (size) {
1579 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1580 unsigned dma_flags = CP_DMA_CLEAR;
1581
1582 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1583 /* DMA operations via L2 are coherent and faster.
1584 * TODO: GFX7-GFX9 should also support this but it
1585 * requires tests/benchmarks.
1586 */
1587 dma_flags |= CP_DMA_USE_L2;
1588 }
1589
1590 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1591
1592 /* Emit the clear packet. */
1593 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1594 dma_flags);
1595
1596 size -= byte_count;
1597 va += byte_count;
1598 }
1599 }
1600
1601 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1602 {
1603 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1604 return;
1605
1606 if (!cmd_buffer->state.dma_is_busy)
1607 return;
1608
1609 /* Issue a dummy DMA that copies zero bytes.
1610 *
1611 * The DMA engine will see that there's no work to do and skip this
1612 * DMA request, however, the CP will see the sync flag and still wait
1613 * for all DMAs to complete.
1614 */
1615 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1616
1617 cmd_buffer->state.dma_is_busy = false;
1618 }
1619
1620 /* For MSAA sample positions. */
1621 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1622 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1623 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1624 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1625 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1626
1627 /* For obtaining location coordinates from registers */
1628 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1629 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1630 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1631 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1632
1633 /* 1x MSAA */
1634 static const uint32_t sample_locs_1x =
1635 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1636 static const unsigned max_dist_1x = 0;
1637 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1638
1639 /* 2xMSAA */
1640 static const uint32_t sample_locs_2x =
1641 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1642 static const unsigned max_dist_2x = 4;
1643 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1644
1645 /* 4xMSAA */
1646 static const uint32_t sample_locs_4x =
1647 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1648 static const unsigned max_dist_4x = 6;
1649 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1650
1651 /* 8xMSAA */
1652 static const uint32_t sample_locs_8x[] = {
1653 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1654 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1655 /* The following are unused by hardware, but we emit them to IBs
1656 * instead of multiple SET_CONTEXT_REG packets. */
1657 0,
1658 0,
1659 };
1660 static const unsigned max_dist_8x = 7;
1661 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1662
1663 unsigned radv_get_default_max_sample_dist(int log_samples)
1664 {
1665 unsigned max_dist[] = {
1666 max_dist_1x,
1667 max_dist_2x,
1668 max_dist_4x,
1669 max_dist_8x,
1670 };
1671 return max_dist[log_samples];
1672 }
1673
1674 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1675 {
1676 switch (nr_samples) {
1677 default:
1678 case 1:
1679 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1680 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1681 radeon_emit(cs, centroid_priority_1x >> 32);
1682 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1683 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1684 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1685 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1686 break;
1687 case 2:
1688 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1689 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1690 radeon_emit(cs, centroid_priority_2x >> 32);
1691 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1692 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1693 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1694 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1695 break;
1696 case 4:
1697 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1698 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1699 radeon_emit(cs, centroid_priority_4x >> 32);
1700 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1701 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1702 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1703 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1704 break;
1705 case 8:
1706 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1707 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1708 radeon_emit(cs, centroid_priority_8x >> 32);
1709 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1710 radeon_emit_array(cs, sample_locs_8x, 4);
1711 radeon_emit_array(cs, sample_locs_8x, 4);
1712 radeon_emit_array(cs, sample_locs_8x, 4);
1713 radeon_emit_array(cs, sample_locs_8x, 2);
1714 break;
1715 }
1716 }
1717
1718 static void radv_get_sample_position(struct radv_device *device,
1719 unsigned sample_count,
1720 unsigned sample_index, float *out_value)
1721 {
1722 const uint32_t *sample_locs;
1723
1724 switch (sample_count) {
1725 case 1:
1726 default:
1727 sample_locs = &sample_locs_1x;
1728 break;
1729 case 2:
1730 sample_locs = &sample_locs_2x;
1731 break;
1732 case 4:
1733 sample_locs = &sample_locs_4x;
1734 break;
1735 case 8:
1736 sample_locs = sample_locs_8x;
1737 break;
1738 }
1739
1740 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1741 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1742 }
1743
1744 void radv_device_init_msaa(struct radv_device *device)
1745 {
1746 int i;
1747
1748 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1749
1750 for (i = 0; i < 2; i++)
1751 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1752 for (i = 0; i < 4; i++)
1753 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1754 for (i = 0; i < 8; i++)
1755 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1756 }