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radv/gfx10: set PA_SC_TILE_STEERING_OVERRIDE
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
106 * and is now per pipe, so it should be handled in the
107 * kernel if we want to use something other than the default value,
108 * which is now 0x22f.
109 */
110 if (physical_device->rad_info.chip_class <= GFX6) {
111 /* XXX: This should be:
112 * (number of compute units) * 4 * (waves per simd) - 1 */
113
114 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
115 0x190 /* Default value */);
116 }
117 }
118
119 /* 12.4 fixed-point */
120 static unsigned radv_pack_float_12p4(float x)
121 {
122 return x <= 0 ? 0 :
123 x >= 4096 ? 0xffff : x * 16;
124 }
125
126 static void
127 si_set_raster_config(struct radv_physical_device *physical_device,
128 struct radeon_cmdbuf *cs)
129 {
130 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
131 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
132 unsigned raster_config, raster_config_1;
133
134 ac_get_raster_config(&physical_device->rad_info,
135 &raster_config,
136 &raster_config_1, NULL);
137
138 /* Always use the default config when all backends are enabled
139 * (or when we failed to determine the enabled backends).
140 */
141 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
142 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
143 raster_config);
144 if (physical_device->rad_info.chip_class >= GFX7)
145 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
146 raster_config_1);
147 } else {
148 si_write_harvested_raster_configs(physical_device, cs,
149 raster_config,
150 raster_config_1);
151 }
152 }
153
154 void
155 si_emit_graphics(struct radv_physical_device *physical_device,
156 struct radeon_cmdbuf *cs)
157 {
158 int i;
159
160 /* Only GFX6 can disable CLEAR_STATE for now. */
161 assert(physical_device->has_clear_state ||
162 physical_device->rad_info.chip_class == GFX6);
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (physical_device->has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!physical_device->has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!physical_device->has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
193 if (!physical_device->has_clear_state)
194 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
195 if (physical_device->rad_info.chip_class < GFX7)
196 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
197 S_008A14_CLIP_VTX_REORDER_ENA(1));
198
199 if (!physical_device->has_clear_state)
200 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
201
202 /* CLEAR_STATE doesn't clear these correctly on certain generations.
203 * I don't know why. Deduced by trial and error.
204 */
205 if (physical_device->rad_info.chip_class <= GFX7) {
206 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
207 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
208 S_028204_WINDOW_OFFSET_DISABLE(1));
209 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
210 S_028240_WINDOW_OFFSET_DISABLE(1));
211 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
212 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
213 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
214 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
215 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
216 }
217
218 if (!physical_device->has_clear_state) {
219 for (i = 0; i < 16; i++) {
220 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
221 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
222 }
223 }
224
225 if (!physical_device->has_clear_state) {
226 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
227 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
228 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
229 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
230 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
231 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
232 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
233 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
234 }
235
236 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
237 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
238 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
239
240 if (physical_device->rad_info.chip_class >= GFX9) {
241 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
242 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
243 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
244 } else {
245 /* These registers, when written, also overwrite the
246 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
247 * them. It would be an issue if there was another UMD
248 * changing them.
249 */
250 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
251 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
252 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
253 }
254
255 if (physical_device->rad_info.chip_class >= GFX7) {
256 if (physical_device->rad_info.chip_class >= GFX9) {
257 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
258 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
259 } else {
260 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
261 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
262 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
263 S_00B41C_WAVE_LIMIT(0x3F));
264 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
265 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
266 /* If this is 0, Bonaire can hang even if GS isn't being used.
267 * Other chips are unaffected. These are suboptimal values,
268 * but we don't use on-chip GS.
269 */
270 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
271 S_028A44_ES_VERTS_PER_SUBGRP(64) |
272 S_028A44_GS_PRIMS_PER_SUBGRP(4));
273 }
274 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
275 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
276
277 if (physical_device->rad_info.num_good_cu_per_sh <= 4) {
278 /* Too few available compute units per SH. Disallowing
279 * VS to run on CU0 could hurt us more than late VS
280 * allocation would help.
281 *
282 * LATE_ALLOC_VS = 2 is the highest safe number.
283 */
284 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
285 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
286 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
287 } else {
288 /* Set LATE_ALLOC_VS == 31. It should be less than
289 * the number of scratch waves. Limitations:
290 * - VS can't execute on CU0.
291 * - If HS writes outputs to LDS, LS can't execute on CU0.
292 */
293 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
294 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
295 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
296 }
297
298 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
299 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
300 }
301
302 if (physical_device->rad_info.chip_class >= GFX10) {
303 radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
304 physical_device->rad_info.pa_sc_tile_steering_override);
305 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
306 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
307 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
308 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
309 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
310 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
311 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
312 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
313
314 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
315 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
316 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
317 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
318 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
319 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
320 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
321 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
322 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
323 }
324
325 if (physical_device->rad_info.chip_class >= GFX8) {
326 uint32_t vgt_tess_distribution;
327
328 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
329 S_028B50_ACCUM_TRI(11) |
330 S_028B50_ACCUM_QUAD(11) |
331 S_028B50_DONUT_SPLIT(16);
332
333 if (physical_device->rad_info.family == CHIP_FIJI ||
334 physical_device->rad_info.family >= CHIP_POLARIS10)
335 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
336
337 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
338 vgt_tess_distribution);
339 } else if (!physical_device->has_clear_state) {
340 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
341 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
342 }
343
344 if (physical_device->rad_info.chip_class >= GFX9) {
345 unsigned num_se = physical_device->rad_info.max_se;
346 unsigned pc_lines = 0;
347 unsigned max_alloc_count = 0;
348
349 switch (physical_device->rad_info.family) {
350 case CHIP_VEGA10:
351 case CHIP_VEGA12:
352 case CHIP_VEGA20:
353 pc_lines = 4096;
354 break;
355 case CHIP_RAVEN:
356 case CHIP_RAVEN2:
357 case CHIP_NAVI10:
358 case CHIP_NAVI12:
359 pc_lines = 1024;
360 break;
361 case CHIP_NAVI14:
362 pc_lines = 512;
363 break;
364 default:
365 assert(0);
366 }
367
368 if (physical_device->rad_info.chip_class >= GFX10) {
369 max_alloc_count = pc_lines / 3;
370 } else {
371 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
372 }
373
374 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
375 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
376 S_028C48_MAX_PRIM_PER_BATCH(1023));
377 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
378 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
379 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
380 }
381
382 unsigned tmp = (unsigned)(1.0 * 8.0);
383 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
384 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
385 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
386 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
387 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
388
389 if (!physical_device->has_clear_state) {
390 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
391 S_028004_ZPASS_INCREMENT_DISABLE(1));
392 }
393
394 /* Enable the Polaris small primitive filter control.
395 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
396 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
397 * and AMDVLK doesn't have a workaround as well.
398 */
399 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
400 unsigned small_prim_filter_cntl =
401 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
402 /* Workaround for a hw line bug. */
403 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
404
405 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
406 small_prim_filter_cntl);
407 }
408
409 si_emit_compute(physical_device, cs);
410 }
411
412 void
413 cik_create_gfx_config(struct radv_device *device)
414 {
415 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
416 if (!cs)
417 return;
418
419 si_emit_graphics(device->physical_device, cs);
420
421 while (cs->cdw & 7) {
422 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
423 radeon_emit(cs, 0x80000000);
424 else
425 radeon_emit(cs, 0xffff1000);
426 }
427
428 device->gfx_init = device->ws->buffer_create(device->ws,
429 cs->cdw * 4, 4096,
430 RADEON_DOMAIN_GTT,
431 RADEON_FLAG_CPU_ACCESS|
432 RADEON_FLAG_NO_INTERPROCESS_SHARING |
433 RADEON_FLAG_READ_ONLY,
434 RADV_BO_PRIORITY_CS);
435 if (!device->gfx_init)
436 goto fail;
437
438 void *map = device->ws->buffer_map(device->gfx_init);
439 if (!map) {
440 device->ws->buffer_destroy(device->gfx_init);
441 device->gfx_init = NULL;
442 goto fail;
443 }
444 memcpy(map, cs->buf, cs->cdw * 4);
445
446 device->ws->buffer_unmap(device->gfx_init);
447 device->gfx_init_size_dw = cs->cdw;
448 fail:
449 device->ws->cs_destroy(cs);
450 }
451
452 static void
453 get_viewport_xform(const VkViewport *viewport,
454 float scale[3], float translate[3])
455 {
456 float x = viewport->x;
457 float y = viewport->y;
458 float half_width = 0.5f * viewport->width;
459 float half_height = 0.5f * viewport->height;
460 double n = viewport->minDepth;
461 double f = viewport->maxDepth;
462
463 scale[0] = half_width;
464 translate[0] = half_width + x;
465 scale[1] = half_height;
466 translate[1] = half_height + y;
467
468 scale[2] = (f - n);
469 translate[2] = n;
470 }
471
472 void
473 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
474 int count, const VkViewport *viewports)
475 {
476 int i;
477
478 assert(count);
479 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
480 first_vp * 4 * 6, count * 6);
481
482 for (i = 0; i < count; i++) {
483 float scale[3], translate[3];
484
485
486 get_viewport_xform(&viewports[i], scale, translate);
487 radeon_emit(cs, fui(scale[0]));
488 radeon_emit(cs, fui(translate[0]));
489 radeon_emit(cs, fui(scale[1]));
490 radeon_emit(cs, fui(translate[1]));
491 radeon_emit(cs, fui(scale[2]));
492 radeon_emit(cs, fui(translate[2]));
493 }
494
495 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
496 first_vp * 4 * 2, count * 2);
497 for (i = 0; i < count; i++) {
498 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
499 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
500 radeon_emit(cs, fui(zmin));
501 radeon_emit(cs, fui(zmax));
502 }
503 }
504
505 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
506 {
507 float scale[3], translate[3];
508 VkRect2D rect;
509
510 get_viewport_xform(viewport, scale, translate);
511
512 rect.offset.x = translate[0] - fabs(scale[0]);
513 rect.offset.y = translate[1] - fabs(scale[1]);
514 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
515 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
516
517 return rect;
518 }
519
520 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
521 VkRect2D ret;
522 ret.offset.x = MAX2(a->offset.x, b->offset.x);
523 ret.offset.y = MAX2(a->offset.y, b->offset.y);
524 ret.extent.width = MIN2(a->offset.x + a->extent.width,
525 b->offset.x + b->extent.width) - ret.offset.x;
526 ret.extent.height = MIN2(a->offset.y + a->extent.height,
527 b->offset.y + b->extent.height) - ret.offset.y;
528 return ret;
529 }
530
531 void
532 si_write_scissors(struct radeon_cmdbuf *cs, int first,
533 int count, const VkRect2D *scissors,
534 const VkViewport *viewports, bool can_use_guardband)
535 {
536 int i;
537 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
538 const float max_range = 32767.0f;
539 if (!count)
540 return;
541
542 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
543 for (i = 0; i < count; i++) {
544 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
545 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
546
547 get_viewport_xform(viewports + i, scale, translate);
548 scale[0] = fabsf(scale[0]);
549 scale[1] = fabsf(scale[1]);
550
551 if (scale[0] < 0.5)
552 scale[0] = 0.5;
553 if (scale[1] < 0.5)
554 scale[1] = 0.5;
555
556 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
557 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
558
559 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
560 S_028250_TL_Y(scissor.offset.y) |
561 S_028250_WINDOW_OFFSET_DISABLE(1));
562 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
563 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
564 }
565 if (!can_use_guardband) {
566 guardband_x = 1.0;
567 guardband_y = 1.0;
568 }
569
570 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
571 radeon_emit(cs, fui(guardband_y));
572 radeon_emit(cs, fui(1.0));
573 radeon_emit(cs, fui(guardband_x));
574 radeon_emit(cs, fui(1.0));
575 }
576
577 static inline unsigned
578 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
579 {
580 if (num == 0)
581 return 0;
582
583 if (info->incr == 0)
584 return 0;
585
586 if (num < info->min)
587 return 0;
588
589 return 1 + ((num - info->min) / info->incr);
590 }
591
592 uint32_t
593 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
594 bool instanced_draw, bool indirect_draw,
595 bool count_from_stream_output,
596 uint32_t draw_vertex_count)
597 {
598 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
599 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
600 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
601 const unsigned max_primgroup_in_wave = 2;
602 /* SWITCH_ON_EOP(0) is always preferable. */
603 bool wd_switch_on_eop = false;
604 bool ia_switch_on_eop = false;
605 bool ia_switch_on_eoi = false;
606 bool partial_vs_wave = false;
607 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
608 bool multi_instances_smaller_than_primgroup;
609
610 multi_instances_smaller_than_primgroup = indirect_draw;
611 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
612 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
613 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
614 multi_instances_smaller_than_primgroup = true;
615 }
616
617 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
618 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
619
620 if (chip_class >= GFX7) {
621 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
622
623 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
624 * We don't know that for indirect drawing, so treat it as
625 * always problematic. */
626 if (family == CHIP_HAWAII &&
627 (instanced_draw || indirect_draw))
628 wd_switch_on_eop = true;
629
630 /* Performance recommendation for 4 SE Gfx7-8 parts if
631 * instances are smaller than a primgroup.
632 * Assume indirect draws always use small instances.
633 * This is needed for good VS wave utilization.
634 */
635 if (chip_class <= GFX8 &&
636 info->max_se == 4 &&
637 multi_instances_smaller_than_primgroup)
638 wd_switch_on_eop = true;
639
640 /* Required on GFX7 and later. */
641 if (info->max_se > 2 && !wd_switch_on_eop)
642 ia_switch_on_eoi = true;
643
644 /* Required by Hawaii and, for some special cases, by GFX8. */
645 if (ia_switch_on_eoi &&
646 (family == CHIP_HAWAII ||
647 (chip_class == GFX8 &&
648 /* max primgroup in wave is always 2 - leave this for documentation */
649 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
650 partial_vs_wave = true;
651
652 /* Instancing bug on Bonaire. */
653 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
654 (instanced_draw || indirect_draw))
655 partial_vs_wave = true;
656
657 /* Hardware requirement when drawing primitives from a stream
658 * output buffer.
659 */
660 if (count_from_stream_output)
661 wd_switch_on_eop = true;
662
663 /* If the WD switch is false, the IA switch must be false too. */
664 assert(wd_switch_on_eop || !ia_switch_on_eop);
665 }
666 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
667 if (chip_class <= GFX8 && ia_switch_on_eoi)
668 partial_es_wave = true;
669
670 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
671 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
672 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
673 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
674 */
675 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
676 bool set_vgt_flush = indirect_draw;
677 if (!set_vgt_flush && instanced_draw) {
678 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
679 if (num_prims <= 1)
680 set_vgt_flush = true;
681 }
682 if (set_vgt_flush)
683 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
684 }
685 }
686
687 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
688 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
689 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
690 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
691 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
692 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
693
694 }
695
696 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
697 enum chip_class chip_class,
698 bool is_mec,
699 unsigned event, unsigned event_flags,
700 unsigned data_sel,
701 uint64_t va,
702 uint32_t new_fence,
703 uint64_t gfx9_eop_bug_va)
704 {
705 unsigned op = EVENT_TYPE(event) |
706 EVENT_INDEX(5) |
707 event_flags;
708 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
709 unsigned sel = EOP_DATA_SEL(data_sel);
710
711 /* Wait for write confirmation before writing data, but don't send
712 * an interrupt. */
713 if (data_sel != EOP_DATA_SEL_DISCARD)
714 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
715
716 if (chip_class >= GFX9 || is_gfx8_mec) {
717 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
718 * counters) must immediately precede every timestamp event to
719 * prevent a GPU hang on GFX9.
720 */
721 if (chip_class == GFX9 && !is_mec) {
722 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
723 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
724 radeon_emit(cs, gfx9_eop_bug_va);
725 radeon_emit(cs, gfx9_eop_bug_va >> 32);
726 }
727
728 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
729 radeon_emit(cs, op);
730 radeon_emit(cs, sel);
731 radeon_emit(cs, va); /* address lo */
732 radeon_emit(cs, va >> 32); /* address hi */
733 radeon_emit(cs, new_fence); /* immediate data lo */
734 radeon_emit(cs, 0); /* immediate data hi */
735 if (!is_gfx8_mec)
736 radeon_emit(cs, 0); /* unused */
737 } else {
738 if (chip_class == GFX7 ||
739 chip_class == GFX8) {
740 /* Two EOP events are required to make all engines go idle
741 * (and optional cache flushes executed) before the timestamp
742 * is written.
743 */
744 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
745 radeon_emit(cs, op);
746 radeon_emit(cs, va);
747 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
748 radeon_emit(cs, 0); /* immediate data */
749 radeon_emit(cs, 0); /* unused */
750 }
751
752 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
753 radeon_emit(cs, op);
754 radeon_emit(cs, va);
755 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
756 radeon_emit(cs, new_fence); /* immediate data */
757 radeon_emit(cs, 0); /* unused */
758 }
759 }
760
761 void
762 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
763 uint32_t ref, uint32_t mask)
764 {
765 assert(op == WAIT_REG_MEM_EQUAL ||
766 op == WAIT_REG_MEM_NOT_EQUAL ||
767 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
768
769 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
770 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
771 radeon_emit(cs, va);
772 radeon_emit(cs, va >> 32);
773 radeon_emit(cs, ref); /* reference value */
774 radeon_emit(cs, mask); /* mask */
775 radeon_emit(cs, 4); /* poll interval */
776 }
777
778 static void
779 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
780 bool is_mec,
781 bool is_gfx9,
782 unsigned cp_coher_cntl)
783 {
784 if (is_mec || is_gfx9) {
785 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
786 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
787 PKT3_SHADER_TYPE_S(is_mec));
788 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
789 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
790 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
791 radeon_emit(cs, 0); /* CP_COHER_BASE */
792 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
793 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
794 } else {
795 /* ACQUIRE_MEM is only required on a compute ring. */
796 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
797 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
798 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
799 radeon_emit(cs, 0); /* CP_COHER_BASE */
800 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
801 }
802 }
803
804 void
805 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
806 enum chip_class chip_class,
807 uint32_t *flush_cnt,
808 uint64_t flush_va,
809 bool is_mec,
810 enum radv_cmd_flush_bits flush_bits,
811 uint64_t gfx9_eop_bug_va)
812 {
813 unsigned cp_coher_cntl = 0;
814 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
815 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
816
817 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
818 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
819 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
820 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
821
822 if (chip_class <= GFX8) {
823 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
824 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
825 S_0085F0_CB0_DEST_BASE_ENA(1) |
826 S_0085F0_CB1_DEST_BASE_ENA(1) |
827 S_0085F0_CB2_DEST_BASE_ENA(1) |
828 S_0085F0_CB3_DEST_BASE_ENA(1) |
829 S_0085F0_CB4_DEST_BASE_ENA(1) |
830 S_0085F0_CB5_DEST_BASE_ENA(1) |
831 S_0085F0_CB6_DEST_BASE_ENA(1) |
832 S_0085F0_CB7_DEST_BASE_ENA(1);
833
834 /* Necessary for DCC */
835 if (chip_class >= GFX8) {
836 si_cs_emit_write_event_eop(cs,
837 chip_class,
838 is_mec,
839 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
840 0,
841 EOP_DATA_SEL_DISCARD,
842 0, 0,
843 gfx9_eop_bug_va);
844 }
845 }
846 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
847 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
848 S_0085F0_DB_DEST_BASE_ENA(1);
849 }
850 }
851
852 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
853 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
854 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
855 }
856
857 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
858 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
859 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
860 }
861
862 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
863 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
864 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
865 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
866 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
867 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
868 }
869
870 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
871 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
872 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
873 }
874
875 if (chip_class >= GFX9 && flush_cb_db) {
876 unsigned cb_db_event, tc_flags;
877
878 /* Set the CB/DB flush event. */
879 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
880
881 /* These are the only allowed combinations. If you need to
882 * do multiple operations at once, do them separately.
883 * All operations that invalidate L2 also seem to invalidate
884 * metadata. Volatile (VOL) and WC flushes are not listed here.
885 *
886 * TC | TC_WB = writeback & invalidate L2 & L1
887 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
888 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
889 * TC | TC_NC = invalidate L2 for MTYPE == NC
890 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
891 * TCL1 = invalidate L1
892 */
893 tc_flags = EVENT_TC_ACTION_ENA |
894 EVENT_TC_MD_ACTION_ENA;
895
896 /* Ideally flush TC together with CB/DB. */
897 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
898 /* Writeback and invalidate everything in L2 & L1. */
899 tc_flags = EVENT_TC_ACTION_ENA |
900 EVENT_TC_WB_ACTION_ENA;
901
902
903 /* Clear the flags. */
904 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
905 RADV_CMD_FLAG_WB_L2 |
906 RADV_CMD_FLAG_INV_VCACHE);
907 }
908 assert(flush_cnt);
909 (*flush_cnt)++;
910
911 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
912 EOP_DATA_SEL_VALUE_32BIT,
913 flush_va, *flush_cnt,
914 gfx9_eop_bug_va);
915 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
916 *flush_cnt, 0xffffffff);
917 }
918
919 /* VGT state sync */
920 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
921 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
922 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
923 }
924
925 /* VGT streamout state sync */
926 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
927 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
928 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
929 }
930
931 /* Make sure ME is idle (it executes most packets) before continuing.
932 * This prevents read-after-write hazards between PFP and ME.
933 */
934 if ((cp_coher_cntl ||
935 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
936 RADV_CMD_FLAG_INV_VCACHE |
937 RADV_CMD_FLAG_INV_L2 |
938 RADV_CMD_FLAG_WB_L2))) &&
939 !is_mec) {
940 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
941 radeon_emit(cs, 0);
942 }
943
944 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
945 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
946 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
947 cp_coher_cntl |
948 S_0085F0_TC_ACTION_ENA(1) |
949 S_0085F0_TCL1_ACTION_ENA(1) |
950 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
951 cp_coher_cntl = 0;
952 } else {
953 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
954 /* WB = write-back
955 * NC = apply to non-coherent MTYPEs
956 * (i.e. MTYPE <= 1, which is what we use everywhere)
957 *
958 * WB doesn't work without NC.
959 */
960 si_emit_acquire_mem(cs, is_mec,
961 chip_class >= GFX9,
962 cp_coher_cntl |
963 S_0301F0_TC_WB_ACTION_ENA(1) |
964 S_0301F0_TC_NC_ACTION_ENA(1));
965 cp_coher_cntl = 0;
966 }
967 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
968 si_emit_acquire_mem(cs, is_mec,
969 chip_class >= GFX9,
970 cp_coher_cntl |
971 S_0085F0_TCL1_ACTION_ENA(1));
972 cp_coher_cntl = 0;
973 }
974 }
975
976 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
977 * Therefore, it should be last. Done in PFP.
978 */
979 if (cp_coher_cntl)
980 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
981
982 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
983 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
984 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
985 EVENT_INDEX(0));
986 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
987 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
988 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
989 EVENT_INDEX(0));
990 }
991 }
992
993 void
994 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
995 {
996 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
997
998 if (is_compute)
999 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1000 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1001 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1002 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1003 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1004 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1005 RADV_CMD_FLAG_VGT_FLUSH |
1006 RADV_CMD_FLAG_START_PIPELINE_STATS |
1007 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1008
1009 if (!cmd_buffer->state.flush_bits)
1010 return;
1011
1012 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1013
1014 si_cs_emit_cache_flush(cmd_buffer->cs,
1015 cmd_buffer->device->physical_device->rad_info.chip_class,
1016 &cmd_buffer->gfx9_fence_idx,
1017 cmd_buffer->gfx9_fence_va,
1018 radv_cmd_buffer_uses_mec(cmd_buffer),
1019 cmd_buffer->state.flush_bits,
1020 cmd_buffer->gfx9_eop_bug_va);
1021
1022
1023 if (unlikely(cmd_buffer->device->trace_bo))
1024 radv_cmd_buffer_trace_emit(cmd_buffer);
1025
1026 /* Clear the caches that have been flushed to avoid syncing too much
1027 * when there is some pending active queries.
1028 */
1029 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1030
1031 cmd_buffer->state.flush_bits = 0;
1032
1033 /* If the driver used a compute shader for resetting a query pool, it
1034 * should be finished at this point.
1035 */
1036 cmd_buffer->pending_reset_query = false;
1037 }
1038
1039 /* sets the CP predication state using a boolean stored at va */
1040 void
1041 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1042 bool draw_visible, uint64_t va)
1043 {
1044 uint32_t op = 0;
1045
1046 if (va) {
1047 op = PRED_OP(PREDICATION_OP_BOOL64);
1048
1049 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1050 * zero, all rendering commands are discarded. Otherwise, they
1051 * are discarded if the value is non zero.
1052 */
1053 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1054 PREDICATION_DRAW_NOT_VISIBLE;
1055 }
1056 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1057 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1058 radeon_emit(cmd_buffer->cs, op);
1059 radeon_emit(cmd_buffer->cs, va);
1060 radeon_emit(cmd_buffer->cs, va >> 32);
1061 } else {
1062 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1063 radeon_emit(cmd_buffer->cs, va);
1064 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1065 }
1066 }
1067
1068 /* Set this if you want the 3D engine to wait until CP DMA is done.
1069 * It should be set on the last CP DMA packet. */
1070 #define CP_DMA_SYNC (1 << 0)
1071
1072 /* Set this if the source data was used as a destination in a previous CP DMA
1073 * packet. It's for preventing a read-after-write (RAW) hazard between two
1074 * CP DMA packets. */
1075 #define CP_DMA_RAW_WAIT (1 << 1)
1076 #define CP_DMA_USE_L2 (1 << 2)
1077 #define CP_DMA_CLEAR (1 << 3)
1078
1079 /* Alignment for optimal performance. */
1080 #define SI_CPDMA_ALIGNMENT 32
1081
1082 /* The max number of bytes that can be copied per packet. */
1083 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1084 {
1085 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1086 S_414_BYTE_COUNT_GFX9(~0u) :
1087 S_414_BYTE_COUNT_GFX6(~0u);
1088
1089 /* make it aligned for optimal performance */
1090 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1091 }
1092
1093 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1094 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1095 * clear value.
1096 */
1097 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1098 uint64_t dst_va, uint64_t src_va,
1099 unsigned size, unsigned flags)
1100 {
1101 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1102 uint32_t header = 0, command = 0;
1103
1104 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1105
1106 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1107 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1108 command |= S_414_BYTE_COUNT_GFX9(size);
1109 else
1110 command |= S_414_BYTE_COUNT_GFX6(size);
1111
1112 /* Sync flags. */
1113 if (flags & CP_DMA_SYNC)
1114 header |= S_411_CP_SYNC(1);
1115 else {
1116 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1117 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1118 else
1119 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1120 }
1121
1122 if (flags & CP_DMA_RAW_WAIT)
1123 command |= S_414_RAW_WAIT(1);
1124
1125 /* Src and dst flags. */
1126 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1127 !(flags & CP_DMA_CLEAR) &&
1128 src_va == dst_va)
1129 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1130 else if (flags & CP_DMA_USE_L2)
1131 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1132
1133 if (flags & CP_DMA_CLEAR)
1134 header |= S_411_SRC_SEL(V_411_DATA);
1135 else if (flags & CP_DMA_USE_L2)
1136 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1137
1138 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1139 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1140 radeon_emit(cs, header);
1141 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1142 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1143 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1144 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1145 radeon_emit(cs, command);
1146 } else {
1147 assert(!(flags & CP_DMA_USE_L2));
1148 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1149 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1150 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1151 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1152 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1153 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1154 radeon_emit(cs, command);
1155 }
1156
1157 /* CP DMA is executed in ME, but index buffers are read by PFP.
1158 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1159 * indices. If we wanted to execute CP DMA in PFP, this packet
1160 * should precede it.
1161 */
1162 if (flags & CP_DMA_SYNC) {
1163 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1164 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1165 radeon_emit(cs, 0);
1166 }
1167
1168 /* CP will see the sync flag and wait for all DMAs to complete. */
1169 cmd_buffer->state.dma_is_busy = false;
1170 }
1171
1172 if (unlikely(cmd_buffer->device->trace_bo))
1173 radv_cmd_buffer_trace_emit(cmd_buffer);
1174 }
1175
1176 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1177 unsigned size)
1178 {
1179 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1180 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1181
1182 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1183 aligned_size, CP_DMA_USE_L2);
1184 }
1185
1186 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1187 uint64_t remaining_size, unsigned *flags)
1188 {
1189
1190 /* Flush the caches for the first copy only.
1191 * Also wait for the previous CP DMA operations.
1192 */
1193 if (cmd_buffer->state.flush_bits) {
1194 si_emit_cache_flush(cmd_buffer);
1195 *flags |= CP_DMA_RAW_WAIT;
1196 }
1197
1198 /* Do the synchronization after the last dma, so that all data
1199 * is written to memory.
1200 */
1201 if (byte_count == remaining_size)
1202 *flags |= CP_DMA_SYNC;
1203 }
1204
1205 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1206 {
1207 uint64_t va;
1208 uint32_t offset;
1209 unsigned dma_flags = 0;
1210 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1211 void *ptr;
1212
1213 assert(size < SI_CPDMA_ALIGNMENT);
1214
1215 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1216
1217 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1218 va += offset;
1219
1220 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1221
1222 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1223 dma_flags);
1224 }
1225
1226 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1227 uint64_t src_va, uint64_t dest_va,
1228 uint64_t size)
1229 {
1230 uint64_t main_src_va, main_dest_va;
1231 uint64_t skipped_size = 0, realign_size = 0;
1232
1233 /* Assume that we are not going to sync after the last DMA operation. */
1234 cmd_buffer->state.dma_is_busy = true;
1235
1236 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1237 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1238 /* If the size is not aligned, we must add a dummy copy at the end
1239 * just to align the internal counter. Otherwise, the DMA engine
1240 * would slow down by an order of magnitude for following copies.
1241 */
1242 if (size % SI_CPDMA_ALIGNMENT)
1243 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1244
1245 /* If the copy begins unaligned, we must start copying from the next
1246 * aligned block and the skipped part should be copied after everything
1247 * else has been copied. Only the src alignment matters, not dst.
1248 */
1249 if (src_va % SI_CPDMA_ALIGNMENT) {
1250 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1251 /* The main part will be skipped if the size is too small. */
1252 skipped_size = MIN2(skipped_size, size);
1253 size -= skipped_size;
1254 }
1255 }
1256 main_src_va = src_va + skipped_size;
1257 main_dest_va = dest_va + skipped_size;
1258
1259 while (size) {
1260 unsigned dma_flags = 0;
1261 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1262
1263 si_cp_dma_prepare(cmd_buffer, byte_count,
1264 size + skipped_size + realign_size,
1265 &dma_flags);
1266
1267 dma_flags &= ~CP_DMA_SYNC;
1268
1269 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1270 byte_count, dma_flags);
1271
1272 size -= byte_count;
1273 main_src_va += byte_count;
1274 main_dest_va += byte_count;
1275 }
1276
1277 if (skipped_size) {
1278 unsigned dma_flags = 0;
1279
1280 si_cp_dma_prepare(cmd_buffer, skipped_size,
1281 size + skipped_size + realign_size,
1282 &dma_flags);
1283
1284 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1285 skipped_size, dma_flags);
1286 }
1287 if (realign_size)
1288 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1289 }
1290
1291 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1292 uint64_t size, unsigned value)
1293 {
1294
1295 if (!size)
1296 return;
1297
1298 assert(va % 4 == 0 && size % 4 == 0);
1299
1300 /* Assume that we are not going to sync after the last DMA operation. */
1301 cmd_buffer->state.dma_is_busy = true;
1302
1303 while (size) {
1304 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1305 unsigned dma_flags = CP_DMA_CLEAR;
1306
1307 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1308
1309 /* Emit the clear packet. */
1310 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1311 dma_flags);
1312
1313 size -= byte_count;
1314 va += byte_count;
1315 }
1316 }
1317
1318 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1319 {
1320 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1321 return;
1322
1323 if (!cmd_buffer->state.dma_is_busy)
1324 return;
1325
1326 /* Issue a dummy DMA that copies zero bytes.
1327 *
1328 * The DMA engine will see that there's no work to do and skip this
1329 * DMA request, however, the CP will see the sync flag and still wait
1330 * for all DMAs to complete.
1331 */
1332 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1333
1334 cmd_buffer->state.dma_is_busy = false;
1335 }
1336
1337 /* For MSAA sample positions. */
1338 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1339 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1340 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1341 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1342 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1343
1344 /* For obtaining location coordinates from registers */
1345 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1346 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1347 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1348 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1349
1350 /* 1x MSAA */
1351 static const uint32_t sample_locs_1x =
1352 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1353 static const unsigned max_dist_1x = 0;
1354 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1355
1356 /* 2xMSAA */
1357 static const uint32_t sample_locs_2x =
1358 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1359 static const unsigned max_dist_2x = 4;
1360 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1361
1362 /* 4xMSAA */
1363 static const uint32_t sample_locs_4x =
1364 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1365 static const unsigned max_dist_4x = 6;
1366 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1367
1368 /* 8xMSAA */
1369 static const uint32_t sample_locs_8x[] = {
1370 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1371 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1372 /* The following are unused by hardware, but we emit them to IBs
1373 * instead of multiple SET_CONTEXT_REG packets. */
1374 0,
1375 0,
1376 };
1377 static const unsigned max_dist_8x = 7;
1378 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1379
1380 unsigned radv_get_default_max_sample_dist(int log_samples)
1381 {
1382 unsigned max_dist[] = {
1383 max_dist_1x,
1384 max_dist_2x,
1385 max_dist_4x,
1386 max_dist_8x,
1387 };
1388 return max_dist[log_samples];
1389 }
1390
1391 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1392 {
1393 switch (nr_samples) {
1394 default:
1395 case 1:
1396 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1397 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1398 radeon_emit(cs, centroid_priority_1x >> 32);
1399 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1400 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1401 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1402 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1403 break;
1404 case 2:
1405 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1406 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1407 radeon_emit(cs, centroid_priority_2x >> 32);
1408 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1409 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1410 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1411 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1412 break;
1413 case 4:
1414 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1415 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1416 radeon_emit(cs, centroid_priority_4x >> 32);
1417 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1418 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1419 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1420 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1421 break;
1422 case 8:
1423 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1424 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1425 radeon_emit(cs, centroid_priority_8x >> 32);
1426 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1427 radeon_emit_array(cs, sample_locs_8x, 4);
1428 radeon_emit_array(cs, sample_locs_8x, 4);
1429 radeon_emit_array(cs, sample_locs_8x, 4);
1430 radeon_emit_array(cs, sample_locs_8x, 2);
1431 break;
1432 }
1433 }
1434
1435 static void radv_get_sample_position(struct radv_device *device,
1436 unsigned sample_count,
1437 unsigned sample_index, float *out_value)
1438 {
1439 const uint32_t *sample_locs;
1440
1441 switch (sample_count) {
1442 case 1:
1443 default:
1444 sample_locs = &sample_locs_1x;
1445 break;
1446 case 2:
1447 sample_locs = &sample_locs_2x;
1448 break;
1449 case 4:
1450 sample_locs = &sample_locs_4x;
1451 break;
1452 case 8:
1453 sample_locs = sample_locs_8x;
1454 break;
1455 }
1456
1457 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1458 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1459 }
1460
1461 void radv_device_init_msaa(struct radv_device *device)
1462 {
1463 int i;
1464
1465 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1466
1467 for (i = 0; i < 2; i++)
1468 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1469 for (i = 0; i < 4; i++)
1470 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1471 for (i = 0; i < 8; i++)
1472 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1473 }