2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
6 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 /* command buffer handling for AMD GCN */
30 #include "radv_private.h"
31 #include "radv_shader.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
39 si_write_harvested_raster_configs(struct radv_physical_device
*physical_device
,
40 struct radeon_cmdbuf
*cs
,
41 unsigned raster_config
,
42 unsigned raster_config_1
)
44 unsigned num_se
= MAX2(physical_device
->rad_info
.max_se
, 1);
45 unsigned raster_config_se
[4];
48 ac_get_harvested_configs(&physical_device
->rad_info
,
53 for (se
= 0; se
< num_se
; se
++) {
54 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
55 if (physical_device
->rad_info
.chip_class
< GFX7
)
56 radeon_set_config_reg(cs
, R_00802C_GRBM_GFX_INDEX
,
57 S_00802C_SE_INDEX(se
) |
58 S_00802C_SH_BROADCAST_WRITES(1) |
59 S_00802C_INSTANCE_BROADCAST_WRITES(1));
61 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
62 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
63 S_030800_INSTANCE_BROADCAST_WRITES(1));
64 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
67 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
68 if (physical_device
->rad_info
.chip_class
< GFX7
)
69 radeon_set_config_reg(cs
, R_00802C_GRBM_GFX_INDEX
,
70 S_00802C_SE_BROADCAST_WRITES(1) |
71 S_00802C_SH_BROADCAST_WRITES(1) |
72 S_00802C_INSTANCE_BROADCAST_WRITES(1));
74 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
75 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
76 S_030800_INSTANCE_BROADCAST_WRITES(1));
78 if (physical_device
->rad_info
.chip_class
>= GFX7
)
79 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
83 si_emit_compute(struct radv_physical_device
*physical_device
,
84 struct radeon_cmdbuf
*cs
)
86 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
91 radeon_set_sh_reg_seq(cs
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
, 2);
92 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
93 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs
, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
96 if (physical_device
->rad_info
.chip_class
>= GFX7
) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs
,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
100 radeon_emit(cs
, S_00B864_SH0_CU_EN(0xffff) |
101 S_00B864_SH1_CU_EN(0xffff));
102 radeon_emit(cs
, S_00B868_SH0_CU_EN(0xffff) |
103 S_00B868_SH1_CU_EN(0xffff));
106 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
107 * and is now per pipe, so it should be handled in the
108 * kernel if we want to use something other than the default value,
109 * which is now 0x22f.
111 if (physical_device
->rad_info
.chip_class
<= GFX6
) {
112 /* XXX: This should be:
113 * (number of compute units) * 4 * (waves per simd) - 1 */
115 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
116 0x190 /* Default value */);
120 /* 12.4 fixed-point */
121 static unsigned radv_pack_float_12p4(float x
)
124 x
>= 4096 ? 0xffff : x
* 16;
128 si_set_raster_config(struct radv_physical_device
*physical_device
,
129 struct radeon_cmdbuf
*cs
)
131 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
132 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
133 unsigned raster_config
, raster_config_1
;
135 ac_get_raster_config(&physical_device
->rad_info
,
137 &raster_config_1
, NULL
);
139 /* Always use the default config when all backends are enabled
140 * (or when we failed to determine the enabled backends).
142 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
143 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
,
145 if (physical_device
->rad_info
.chip_class
>= GFX7
)
146 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
,
149 si_write_harvested_raster_configs(physical_device
, cs
,
156 si_emit_graphics(struct radv_physical_device
*physical_device
,
157 struct radeon_cmdbuf
*cs
)
161 /* Only GFX6 can disable CLEAR_STATE for now. */
162 assert(physical_device
->has_clear_state
||
163 physical_device
->rad_info
.chip_class
== GFX6
);
165 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
166 radeon_emit(cs
, CONTEXT_CONTROL_LOAD_ENABLE(1));
167 radeon_emit(cs
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
169 if (physical_device
->has_clear_state
) {
170 radeon_emit(cs
, PKT3(PKT3_CLEAR_STATE
, 0, 0));
174 if (physical_device
->rad_info
.chip_class
<= GFX8
)
175 si_set_raster_config(physical_device
, cs
);
177 radeon_set_context_reg(cs
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
178 if (!physical_device
->has_clear_state
)
179 radeon_set_context_reg(cs
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
181 /* FIXME calculate these values somehow ??? */
182 if (physical_device
->rad_info
.chip_class
<= GFX8
) {
183 radeon_set_context_reg(cs
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
184 radeon_set_context_reg(cs
, R_028A58_VGT_ES_PER_GS
, 0x40);
187 if (!physical_device
->has_clear_state
) {
188 radeon_set_context_reg(cs
, R_028A5C_VGT_GS_PER_VS
, 0x2);
189 radeon_set_context_reg(cs
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
190 radeon_set_context_reg(cs
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
193 radeon_set_context_reg(cs
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
194 if (!physical_device
->has_clear_state
)
195 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
196 if (physical_device
->rad_info
.chip_class
< GFX7
)
197 radeon_set_config_reg(cs
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
198 S_008A14_CLIP_VTX_REORDER_ENA(1));
200 if (!physical_device
->has_clear_state
)
201 radeon_set_context_reg(cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
203 /* CLEAR_STATE doesn't clear these correctly on certain generations.
204 * I don't know why. Deduced by trial and error.
206 if (physical_device
->rad_info
.chip_class
<= GFX7
) {
207 radeon_set_context_reg(cs
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
208 radeon_set_context_reg(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
,
209 S_028204_WINDOW_OFFSET_DISABLE(1));
210 radeon_set_context_reg(cs
, R_028240_PA_SC_GENERIC_SCISSOR_TL
,
211 S_028240_WINDOW_OFFSET_DISABLE(1));
212 radeon_set_context_reg(cs
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
213 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
214 radeon_set_context_reg(cs
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
215 radeon_set_context_reg(cs
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
216 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
219 if (!physical_device
->has_clear_state
) {
220 for (i
= 0; i
< 16; i
++) {
221 radeon_set_context_reg(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+ i
*8, 0);
222 radeon_set_context_reg(cs
, R_0282D4_PA_SC_VPORT_ZMAX_0
+ i
*8, fui(1.0));
226 if (!physical_device
->has_clear_state
) {
227 radeon_set_context_reg(cs
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
228 radeon_set_context_reg(cs
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
229 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
230 radeon_set_context_reg(cs
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
231 radeon_set_context_reg(cs
, R_028820_PA_CL_NANINF_CNTL
, 0);
232 radeon_set_context_reg(cs
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
233 radeon_set_context_reg(cs
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
234 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
237 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
,
238 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
239 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
241 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
242 radeon_set_uconfig_reg(cs
, R_030920_VGT_MAX_VTX_INDX
, ~0);
243 radeon_set_uconfig_reg(cs
, R_030924_VGT_MIN_VTX_INDX
, 0);
244 radeon_set_uconfig_reg(cs
, R_030928_VGT_INDX_OFFSET
, 0);
246 /* These registers, when written, also overwrite the
247 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
248 * them. It would be an issue if there was another UMD
251 radeon_set_context_reg(cs
, R_028400_VGT_MAX_VTX_INDX
, ~0);
252 radeon_set_context_reg(cs
, R_028404_VGT_MIN_VTX_INDX
, 0);
253 radeon_set_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, 0);
256 if (physical_device
->rad_info
.chip_class
>= GFX7
) {
257 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
258 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
259 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
261 radeon_set_sh_reg(cs
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
262 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
263 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
264 S_00B41C_WAVE_LIMIT(0x3F));
265 radeon_set_sh_reg(cs
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
266 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
267 /* If this is 0, Bonaire can hang even if GS isn't being used.
268 * Other chips are unaffected. These are suboptimal values,
269 * but we don't use on-chip GS.
271 radeon_set_context_reg(cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
272 S_028A44_ES_VERTS_PER_SUBGRP(64) |
273 S_028A44_GS_PRIMS_PER_SUBGRP(4));
275 radeon_set_sh_reg(cs
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
276 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
278 if (physical_device
->rad_info
.num_good_cu_per_sh
<= 4) {
279 /* Too few available compute units per SH. Disallowing
280 * VS to run on CU0 could hurt us more than late VS
281 * allocation would help.
283 * LATE_ALLOC_VS = 2 is the highest safe number.
285 radeon_set_sh_reg(cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
286 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
287 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(2));
289 /* Set LATE_ALLOC_VS == 31. It should be less than
290 * the number of scratch waves. Limitations:
291 * - VS can't execute on CU0.
292 * - If HS writes outputs to LDS, LS can't execute on CU0.
294 radeon_set_sh_reg(cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
295 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
296 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(31));
299 radeon_set_sh_reg(cs
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
300 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
303 if (physical_device
->rad_info
.chip_class
>= GFX8
) {
304 uint32_t vgt_tess_distribution
;
306 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) |
307 S_028B50_ACCUM_TRI(11) |
308 S_028B50_ACCUM_QUAD(11) |
309 S_028B50_DONUT_SPLIT(16);
311 if (physical_device
->rad_info
.family
== CHIP_FIJI
||
312 physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
313 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
315 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
316 vgt_tess_distribution
);
317 } else if (!physical_device
->has_clear_state
) {
318 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
319 radeon_set_context_reg(cs
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
322 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
323 unsigned num_se
= physical_device
->rad_info
.max_se
;
324 unsigned pc_lines
= 0;
326 switch (physical_device
->rad_info
.family
) {
340 radeon_set_context_reg(cs
, R_028C48_PA_SC_BINNER_CNTL_1
,
341 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
342 S_028C48_MAX_PRIM_PER_BATCH(1023));
343 radeon_set_context_reg(cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
344 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
345 radeon_set_uconfig_reg(cs
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
348 unsigned tmp
= (unsigned)(1.0 * 8.0);
349 radeon_set_context_reg_seq(cs
, R_028A00_PA_SU_POINT_SIZE
, 1);
350 radeon_emit(cs
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
351 radeon_set_context_reg_seq(cs
, R_028A04_PA_SU_POINT_MINMAX
, 1);
352 radeon_emit(cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
353 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
355 if (!physical_device
->has_clear_state
) {
356 radeon_set_context_reg(cs
, R_028004_DB_COUNT_CONTROL
,
357 S_028004_ZPASS_INCREMENT_DISABLE(1));
360 /* Enable the Polaris small primitive filter control.
361 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
362 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
363 * and AMDVLK doesn't have a workaround as well.
365 if (physical_device
->rad_info
.family
>= CHIP_POLARIS10
) {
366 unsigned small_prim_filter_cntl
=
367 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
368 /* Workaround for a hw line bug. */
369 S_028830_LINE_FILTER_DISABLE(physical_device
->rad_info
.family
<= CHIP_POLARIS12
);
371 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
372 small_prim_filter_cntl
);
375 si_emit_compute(physical_device
, cs
);
379 cik_create_gfx_config(struct radv_device
*device
)
381 struct radeon_cmdbuf
*cs
= device
->ws
->cs_create(device
->ws
, RING_GFX
);
385 si_emit_graphics(device
->physical_device
, cs
);
387 while (cs
->cdw
& 7) {
388 if (device
->physical_device
->rad_info
.gfx_ib_pad_with_type2
)
389 radeon_emit(cs
, 0x80000000);
391 radeon_emit(cs
, 0xffff1000);
394 device
->gfx_init
= device
->ws
->buffer_create(device
->ws
,
397 RADEON_FLAG_CPU_ACCESS
|
398 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
399 RADEON_FLAG_READ_ONLY
,
400 RADV_BO_PRIORITY_CS
);
401 if (!device
->gfx_init
)
404 void *map
= device
->ws
->buffer_map(device
->gfx_init
);
406 device
->ws
->buffer_destroy(device
->gfx_init
);
407 device
->gfx_init
= NULL
;
410 memcpy(map
, cs
->buf
, cs
->cdw
* 4);
412 device
->ws
->buffer_unmap(device
->gfx_init
);
413 device
->gfx_init_size_dw
= cs
->cdw
;
415 device
->ws
->cs_destroy(cs
);
419 get_viewport_xform(const VkViewport
*viewport
,
420 float scale
[3], float translate
[3])
422 float x
= viewport
->x
;
423 float y
= viewport
->y
;
424 float half_width
= 0.5f
* viewport
->width
;
425 float half_height
= 0.5f
* viewport
->height
;
426 double n
= viewport
->minDepth
;
427 double f
= viewport
->maxDepth
;
429 scale
[0] = half_width
;
430 translate
[0] = half_width
+ x
;
431 scale
[1] = half_height
;
432 translate
[1] = half_height
+ y
;
439 si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
440 int count
, const VkViewport
*viewports
)
445 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
446 first_vp
* 4 * 6, count
* 6);
448 for (i
= 0; i
< count
; i
++) {
449 float scale
[3], translate
[3];
452 get_viewport_xform(&viewports
[i
], scale
, translate
);
453 radeon_emit(cs
, fui(scale
[0]));
454 radeon_emit(cs
, fui(translate
[0]));
455 radeon_emit(cs
, fui(scale
[1]));
456 radeon_emit(cs
, fui(translate
[1]));
457 radeon_emit(cs
, fui(scale
[2]));
458 radeon_emit(cs
, fui(translate
[2]));
461 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
462 first_vp
* 4 * 2, count
* 2);
463 for (i
= 0; i
< count
; i
++) {
464 float zmin
= MIN2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
465 float zmax
= MAX2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
466 radeon_emit(cs
, fui(zmin
));
467 radeon_emit(cs
, fui(zmax
));
471 static VkRect2D
si_scissor_from_viewport(const VkViewport
*viewport
)
473 float scale
[3], translate
[3];
476 get_viewport_xform(viewport
, scale
, translate
);
478 rect
.offset
.x
= translate
[0] - fabs(scale
[0]);
479 rect
.offset
.y
= translate
[1] - fabs(scale
[1]);
480 rect
.extent
.width
= ceilf(translate
[0] + fabs(scale
[0])) - rect
.offset
.x
;
481 rect
.extent
.height
= ceilf(translate
[1] + fabs(scale
[1])) - rect
.offset
.y
;
486 static VkRect2D
si_intersect_scissor(const VkRect2D
*a
, const VkRect2D
*b
) {
488 ret
.offset
.x
= MAX2(a
->offset
.x
, b
->offset
.x
);
489 ret
.offset
.y
= MAX2(a
->offset
.y
, b
->offset
.y
);
490 ret
.extent
.width
= MIN2(a
->offset
.x
+ a
->extent
.width
,
491 b
->offset
.x
+ b
->extent
.width
) - ret
.offset
.x
;
492 ret
.extent
.height
= MIN2(a
->offset
.y
+ a
->extent
.height
,
493 b
->offset
.y
+ b
->extent
.height
) - ret
.offset
.y
;
498 si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
499 int count
, const VkRect2D
*scissors
,
500 const VkViewport
*viewports
, bool can_use_guardband
)
503 float scale
[3], translate
[3], guardband_x
= INFINITY
, guardband_y
= INFINITY
;
504 const float max_range
= 32767.0f
;
508 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ first
* 4 * 2, count
* 2);
509 for (i
= 0; i
< count
; i
++) {
510 VkRect2D viewport_scissor
= si_scissor_from_viewport(viewports
+ i
);
511 VkRect2D scissor
= si_intersect_scissor(&scissors
[i
], &viewport_scissor
);
513 get_viewport_xform(viewports
+ i
, scale
, translate
);
514 scale
[0] = fabsf(scale
[0]);
515 scale
[1] = fabsf(scale
[1]);
522 guardband_x
= MIN2(guardband_x
, (max_range
- fabsf(translate
[0])) / scale
[0]);
523 guardband_y
= MIN2(guardband_y
, (max_range
- fabsf(translate
[1])) / scale
[1]);
525 radeon_emit(cs
, S_028250_TL_X(scissor
.offset
.x
) |
526 S_028250_TL_Y(scissor
.offset
.y
) |
527 S_028250_WINDOW_OFFSET_DISABLE(1));
528 radeon_emit(cs
, S_028254_BR_X(scissor
.offset
.x
+ scissor
.extent
.width
) |
529 S_028254_BR_Y(scissor
.offset
.y
+ scissor
.extent
.height
));
531 if (!can_use_guardband
) {
536 radeon_set_context_reg_seq(cs
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
537 radeon_emit(cs
, fui(guardband_y
));
538 radeon_emit(cs
, fui(1.0));
539 radeon_emit(cs
, fui(guardband_x
));
540 radeon_emit(cs
, fui(1.0));
543 static inline unsigned
544 radv_prims_for_vertices(struct radv_prim_vertex_count
*info
, unsigned num
)
555 return 1 + ((num
- info
->min
) / info
->incr
);
559 si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
560 bool instanced_draw
, bool indirect_draw
,
561 bool count_from_stream_output
,
562 uint32_t draw_vertex_count
)
564 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
565 enum radeon_family family
= cmd_buffer
->device
->physical_device
->rad_info
.family
;
566 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
567 const unsigned max_primgroup_in_wave
= 2;
568 /* SWITCH_ON_EOP(0) is always preferable. */
569 bool wd_switch_on_eop
= false;
570 bool ia_switch_on_eop
= false;
571 bool ia_switch_on_eoi
= false;
572 bool partial_vs_wave
= false;
573 bool partial_es_wave
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.partial_es_wave
;
574 bool multi_instances_smaller_than_primgroup
;
576 multi_instances_smaller_than_primgroup
= indirect_draw
;
577 if (!multi_instances_smaller_than_primgroup
&& instanced_draw
) {
578 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
579 if (num_prims
< cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.primgroup_size
)
580 multi_instances_smaller_than_primgroup
= true;
583 ia_switch_on_eoi
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.ia_switch_on_eoi
;
584 partial_vs_wave
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.partial_vs_wave
;
586 if (chip_class
>= GFX7
) {
587 wd_switch_on_eop
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.wd_switch_on_eop
;
589 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
590 * We don't know that for indirect drawing, so treat it as
591 * always problematic. */
592 if (family
== CHIP_HAWAII
&&
593 (instanced_draw
|| indirect_draw
))
594 wd_switch_on_eop
= true;
596 /* Performance recommendation for 4 SE Gfx7-8 parts if
597 * instances are smaller than a primgroup.
598 * Assume indirect draws always use small instances.
599 * This is needed for good VS wave utilization.
601 if (chip_class
<= GFX8
&&
603 multi_instances_smaller_than_primgroup
)
604 wd_switch_on_eop
= true;
606 /* Required on GFX7 and later. */
607 if (info
->max_se
> 2 && !wd_switch_on_eop
)
608 ia_switch_on_eoi
= true;
610 /* Required by Hawaii and, for some special cases, by GFX8. */
611 if (ia_switch_on_eoi
&&
612 (family
== CHIP_HAWAII
||
613 (chip_class
== GFX8
&&
614 /* max primgroup in wave is always 2 - leave this for documentation */
615 (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
) || max_primgroup_in_wave
!= 2))))
616 partial_vs_wave
= true;
618 /* Instancing bug on Bonaire. */
619 if (family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
620 (instanced_draw
|| indirect_draw
))
621 partial_vs_wave
= true;
623 /* Hardware requirement when drawing primitives from a stream
626 if (count_from_stream_output
)
627 wd_switch_on_eop
= true;
629 /* If the WD switch is false, the IA switch must be false too. */
630 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
632 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
633 if (chip_class
<= GFX8
&& ia_switch_on_eoi
)
634 partial_es_wave
= true;
636 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
)) {
637 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
638 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
639 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
641 if (family
== CHIP_HAWAII
&& ia_switch_on_eoi
) {
642 bool set_vgt_flush
= indirect_draw
;
643 if (!set_vgt_flush
&& instanced_draw
) {
644 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
646 set_vgt_flush
= true;
649 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
653 return cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.base
|
654 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
655 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
656 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
657 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
658 S_028AA8_WD_SWITCH_ON_EOP(chip_class
>= GFX7
? wd_switch_on_eop
: 0);
662 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
663 enum chip_class chip_class
,
665 unsigned event
, unsigned event_flags
,
669 uint64_t gfx9_eop_bug_va
)
671 unsigned op
= EVENT_TYPE(event
) |
674 unsigned is_gfx8_mec
= is_mec
&& chip_class
< GFX9
;
675 unsigned sel
= EOP_DATA_SEL(data_sel
);
677 /* Wait for write confirmation before writing data, but don't send
679 if (data_sel
!= EOP_DATA_SEL_DISCARD
)
680 sel
|= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
);
682 if (chip_class
>= GFX9
|| is_gfx8_mec
) {
683 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
684 * counters) must immediately precede every timestamp event to
685 * prevent a GPU hang on GFX9.
687 if (chip_class
== GFX9
&& !is_mec
) {
688 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
689 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
690 radeon_emit(cs
, gfx9_eop_bug_va
);
691 radeon_emit(cs
, gfx9_eop_bug_va
>> 32);
694 radeon_emit(cs
, PKT3(PKT3_RELEASE_MEM
, is_gfx8_mec
? 5 : 6, false));
696 radeon_emit(cs
, sel
);
697 radeon_emit(cs
, va
); /* address lo */
698 radeon_emit(cs
, va
>> 32); /* address hi */
699 radeon_emit(cs
, new_fence
); /* immediate data lo */
700 radeon_emit(cs
, 0); /* immediate data hi */
702 radeon_emit(cs
, 0); /* unused */
704 if (chip_class
== GFX7
||
705 chip_class
== GFX8
) {
706 /* Two EOP events are required to make all engines go idle
707 * (and optional cache flushes executed) before the timestamp
710 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, false));
713 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
714 radeon_emit(cs
, 0); /* immediate data */
715 radeon_emit(cs
, 0); /* unused */
718 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, false));
721 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
722 radeon_emit(cs
, new_fence
); /* immediate data */
723 radeon_emit(cs
, 0); /* unused */
728 radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
729 uint32_t ref
, uint32_t mask
)
731 assert(op
== WAIT_REG_MEM_EQUAL
||
732 op
== WAIT_REG_MEM_NOT_EQUAL
||
733 op
== WAIT_REG_MEM_GREATER_OR_EQUAL
);
735 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, false));
736 radeon_emit(cs
, op
| WAIT_REG_MEM_MEM_SPACE(1));
738 radeon_emit(cs
, va
>> 32);
739 radeon_emit(cs
, ref
); /* reference value */
740 radeon_emit(cs
, mask
); /* mask */
741 radeon_emit(cs
, 4); /* poll interval */
745 si_emit_acquire_mem(struct radeon_cmdbuf
*cs
,
748 unsigned cp_coher_cntl
)
750 if (is_mec
|| is_gfx9
) {
751 uint32_t hi_val
= is_gfx9
? 0xffffff : 0xff;
752 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, false) |
753 PKT3_SHADER_TYPE_S(is_mec
));
754 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
755 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
756 radeon_emit(cs
, hi_val
); /* CP_COHER_SIZE_HI */
757 radeon_emit(cs
, 0); /* CP_COHER_BASE */
758 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
759 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
761 /* ACQUIRE_MEM is only required on a compute ring. */
762 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, false));
763 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
764 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
765 radeon_emit(cs
, 0); /* CP_COHER_BASE */
766 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
771 si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
772 enum chip_class chip_class
,
776 enum radv_cmd_flush_bits flush_bits
,
777 uint64_t gfx9_eop_bug_va
)
779 unsigned cp_coher_cntl
= 0;
780 uint32_t flush_cb_db
= flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
781 RADV_CMD_FLAG_FLUSH_AND_INV_DB
);
783 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
784 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
785 if (flush_bits
& RADV_CMD_FLAG_INV_SMEM_L1
)
786 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
788 if (chip_class
<= GFX8
) {
789 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
790 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
791 S_0085F0_CB0_DEST_BASE_ENA(1) |
792 S_0085F0_CB1_DEST_BASE_ENA(1) |
793 S_0085F0_CB2_DEST_BASE_ENA(1) |
794 S_0085F0_CB3_DEST_BASE_ENA(1) |
795 S_0085F0_CB4_DEST_BASE_ENA(1) |
796 S_0085F0_CB5_DEST_BASE_ENA(1) |
797 S_0085F0_CB6_DEST_BASE_ENA(1) |
798 S_0085F0_CB7_DEST_BASE_ENA(1);
800 /* Necessary for DCC */
801 if (chip_class
>= GFX8
) {
802 si_cs_emit_write_event_eop(cs
,
805 V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
807 EOP_DATA_SEL_DISCARD
,
812 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
813 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
814 S_0085F0_DB_DEST_BASE_ENA(1);
818 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) {
819 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
820 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
823 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) {
824 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
825 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
828 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
829 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
830 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
831 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
832 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
833 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
836 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
837 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
838 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
841 if (chip_class
>= GFX9
&& flush_cb_db
) {
842 unsigned cb_db_event
, tc_flags
;
844 /* Set the CB/DB flush event. */
845 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
847 /* These are the only allowed combinations. If you need to
848 * do multiple operations at once, do them separately.
849 * All operations that invalidate L2 also seem to invalidate
850 * metadata. Volatile (VOL) and WC flushes are not listed here.
852 * TC | TC_WB = writeback & invalidate L2 & L1
853 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
854 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
855 * TC | TC_NC = invalidate L2 for MTYPE == NC
856 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
857 * TCL1 = invalidate L1
859 tc_flags
= EVENT_TC_ACTION_ENA
|
860 EVENT_TC_MD_ACTION_ENA
;
862 /* Ideally flush TC together with CB/DB. */
863 if (flush_bits
& RADV_CMD_FLAG_INV_GLOBAL_L2
) {
864 /* Writeback and invalidate everything in L2 & L1. */
865 tc_flags
= EVENT_TC_ACTION_ENA
|
866 EVENT_TC_WB_ACTION_ENA
;
869 /* Clear the flags. */
870 flush_bits
&= ~(RADV_CMD_FLAG_INV_GLOBAL_L2
|
871 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
|
872 RADV_CMD_FLAG_INV_VMEM_L1
);
877 si_cs_emit_write_event_eop(cs
, chip_class
, false, cb_db_event
, tc_flags
,
878 EOP_DATA_SEL_VALUE_32BIT
,
879 flush_va
, *flush_cnt
,
881 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, flush_va
,
882 *flush_cnt
, 0xffffffff);
886 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
887 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
888 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
891 /* VGT streamout state sync */
892 if (flush_bits
& RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
) {
893 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
894 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
897 /* Make sure ME is idle (it executes most packets) before continuing.
898 * This prevents read-after-write hazards between PFP and ME.
900 if ((cp_coher_cntl
||
901 (flush_bits
& (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
902 RADV_CMD_FLAG_INV_VMEM_L1
|
903 RADV_CMD_FLAG_INV_GLOBAL_L2
|
904 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
))) &&
906 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
910 if ((flush_bits
& RADV_CMD_FLAG_INV_GLOBAL_L2
) ||
911 (chip_class
<= GFX7
&& (flush_bits
& RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
))) {
912 si_emit_acquire_mem(cs
, is_mec
, chip_class
>= GFX9
,
914 S_0085F0_TC_ACTION_ENA(1) |
915 S_0085F0_TCL1_ACTION_ENA(1) |
916 S_0301F0_TC_WB_ACTION_ENA(chip_class
>= GFX8
));
919 if(flush_bits
& RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
) {
921 * NC = apply to non-coherent MTYPEs
922 * (i.e. MTYPE <= 1, which is what we use everywhere)
924 * WB doesn't work without NC.
926 si_emit_acquire_mem(cs
, is_mec
,
929 S_0301F0_TC_WB_ACTION_ENA(1) |
930 S_0301F0_TC_NC_ACTION_ENA(1));
933 if (flush_bits
& RADV_CMD_FLAG_INV_VMEM_L1
) {
934 si_emit_acquire_mem(cs
, is_mec
,
937 S_0085F0_TCL1_ACTION_ENA(1));
942 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
943 * Therefore, it should be last. Done in PFP.
946 si_emit_acquire_mem(cs
, is_mec
, chip_class
>= GFX9
, cp_coher_cntl
);
948 if (flush_bits
& RADV_CMD_FLAG_START_PIPELINE_STATS
) {
949 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
950 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
952 } else if (flush_bits
& RADV_CMD_FLAG_STOP_PIPELINE_STATS
) {
953 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
954 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
960 si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
)
962 bool is_compute
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
965 cmd_buffer
->state
.flush_bits
&= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
966 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
967 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
968 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
969 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
970 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
971 RADV_CMD_FLAG_VGT_FLUSH
|
972 RADV_CMD_FLAG_START_PIPELINE_STATS
|
973 RADV_CMD_FLAG_STOP_PIPELINE_STATS
);
975 if (!cmd_buffer
->state
.flush_bits
)
978 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 128);
980 si_cs_emit_cache_flush(cmd_buffer
->cs
,
981 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
982 &cmd_buffer
->gfx9_fence_idx
,
983 cmd_buffer
->gfx9_fence_va
,
984 radv_cmd_buffer_uses_mec(cmd_buffer
),
985 cmd_buffer
->state
.flush_bits
,
986 cmd_buffer
->gfx9_eop_bug_va
);
989 if (unlikely(cmd_buffer
->device
->trace_bo
))
990 radv_cmd_buffer_trace_emit(cmd_buffer
);
992 /* Clear the caches that have been flushed to avoid syncing too much
993 * when there is some pending active queries.
995 cmd_buffer
->active_query_flush_bits
&= ~cmd_buffer
->state
.flush_bits
;
997 cmd_buffer
->state
.flush_bits
= 0;
999 /* If the driver used a compute shader for resetting a query pool, it
1000 * should be finished at this point.
1002 cmd_buffer
->pending_reset_query
= false;
1005 /* sets the CP predication state using a boolean stored at va */
1007 si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1008 bool draw_visible
, uint64_t va
)
1013 op
= PRED_OP(PREDICATION_OP_BOOL64
);
1015 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1016 * zero, all rendering commands are discarded. Otherwise, they
1017 * are discarded if the value is non zero.
1019 op
|= draw_visible
? PREDICATION_DRAW_VISIBLE
:
1020 PREDICATION_DRAW_NOT_VISIBLE
;
1022 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1023 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 2, 0));
1024 radeon_emit(cmd_buffer
->cs
, op
);
1025 radeon_emit(cmd_buffer
->cs
, va
);
1026 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1028 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 1, 0));
1029 radeon_emit(cmd_buffer
->cs
, va
);
1030 radeon_emit(cmd_buffer
->cs
, op
| ((va
>> 32) & 0xFF));
1034 /* Set this if you want the 3D engine to wait until CP DMA is done.
1035 * It should be set on the last CP DMA packet. */
1036 #define CP_DMA_SYNC (1 << 0)
1038 /* Set this if the source data was used as a destination in a previous CP DMA
1039 * packet. It's for preventing a read-after-write (RAW) hazard between two
1040 * CP DMA packets. */
1041 #define CP_DMA_RAW_WAIT (1 << 1)
1042 #define CP_DMA_USE_L2 (1 << 2)
1043 #define CP_DMA_CLEAR (1 << 3)
1045 /* Alignment for optimal performance. */
1046 #define SI_CPDMA_ALIGNMENT 32
1048 /* The max number of bytes that can be copied per packet. */
1049 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer
*cmd_buffer
)
1051 unsigned max
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
?
1052 S_414_BYTE_COUNT_GFX9(~0u) :
1053 S_414_BYTE_COUNT_GFX6(~0u);
1055 /* make it aligned for optimal performance */
1056 return max
& ~(SI_CPDMA_ALIGNMENT
- 1);
1059 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1060 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1063 static void si_emit_cp_dma(struct radv_cmd_buffer
*cmd_buffer
,
1064 uint64_t dst_va
, uint64_t src_va
,
1065 unsigned size
, unsigned flags
)
1067 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1068 uint32_t header
= 0, command
= 0;
1070 assert(size
<= cp_dma_max_byte_count(cmd_buffer
));
1072 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 9);
1073 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1074 command
|= S_414_BYTE_COUNT_GFX9(size
);
1076 command
|= S_414_BYTE_COUNT_GFX6(size
);
1079 if (flags
& CP_DMA_SYNC
)
1080 header
|= S_411_CP_SYNC(1);
1082 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1083 command
|= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1085 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1088 if (flags
& CP_DMA_RAW_WAIT
)
1089 command
|= S_414_RAW_WAIT(1);
1091 /* Src and dst flags. */
1092 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1093 !(flags
& CP_DMA_CLEAR
) &&
1095 header
|= S_411_DST_SEL(V_411_NOWHERE
); /* prefetch only */
1096 else if (flags
& CP_DMA_USE_L2
)
1097 header
|= S_411_DST_SEL(V_411_DST_ADDR_TC_L2
);
1099 if (flags
& CP_DMA_CLEAR
)
1100 header
|= S_411_SRC_SEL(V_411_DATA
);
1101 else if (flags
& CP_DMA_USE_L2
)
1102 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
);
1104 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1105 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, cmd_buffer
->state
.predicating
));
1106 radeon_emit(cs
, header
);
1107 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1108 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
1109 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1110 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
1111 radeon_emit(cs
, command
);
1113 assert(!(flags
& CP_DMA_USE_L2
));
1114 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
1115 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, cmd_buffer
->state
.predicating
));
1116 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1117 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
1118 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1119 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1120 radeon_emit(cs
, command
);
1123 /* CP DMA is executed in ME, but index buffers are read by PFP.
1124 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1125 * indices. If we wanted to execute CP DMA in PFP, this packet
1126 * should precede it.
1128 if (flags
& CP_DMA_SYNC
) {
1129 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
1130 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1134 /* CP will see the sync flag and wait for all DMAs to complete. */
1135 cmd_buffer
->state
.dma_is_busy
= false;
1138 if (unlikely(cmd_buffer
->device
->trace_bo
))
1139 radv_cmd_buffer_trace_emit(cmd_buffer
);
1142 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1145 uint64_t aligned_va
= va
& ~(SI_CPDMA_ALIGNMENT
- 1);
1146 uint64_t aligned_size
= ((va
+ size
+ SI_CPDMA_ALIGNMENT
-1) & ~(SI_CPDMA_ALIGNMENT
- 1)) - aligned_va
;
1148 si_emit_cp_dma(cmd_buffer
, aligned_va
, aligned_va
,
1149 aligned_size
, CP_DMA_USE_L2
);
1152 static void si_cp_dma_prepare(struct radv_cmd_buffer
*cmd_buffer
, uint64_t byte_count
,
1153 uint64_t remaining_size
, unsigned *flags
)
1156 /* Flush the caches for the first copy only.
1157 * Also wait for the previous CP DMA operations.
1159 if (cmd_buffer
->state
.flush_bits
) {
1160 si_emit_cache_flush(cmd_buffer
);
1161 *flags
|= CP_DMA_RAW_WAIT
;
1164 /* Do the synchronization after the last dma, so that all data
1165 * is written to memory.
1167 if (byte_count
== remaining_size
)
1168 *flags
|= CP_DMA_SYNC
;
1171 static void si_cp_dma_realign_engine(struct radv_cmd_buffer
*cmd_buffer
, unsigned size
)
1175 unsigned dma_flags
= 0;
1176 unsigned buf_size
= SI_CPDMA_ALIGNMENT
* 2;
1179 assert(size
< SI_CPDMA_ALIGNMENT
);
1181 radv_cmd_buffer_upload_alloc(cmd_buffer
, buf_size
, SI_CPDMA_ALIGNMENT
, &offset
, &ptr
);
1183 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1186 si_cp_dma_prepare(cmd_buffer
, size
, size
, &dma_flags
);
1188 si_emit_cp_dma(cmd_buffer
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
,
1192 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1193 uint64_t src_va
, uint64_t dest_va
,
1196 uint64_t main_src_va
, main_dest_va
;
1197 uint64_t skipped_size
= 0, realign_size
= 0;
1199 /* Assume that we are not going to sync after the last DMA operation. */
1200 cmd_buffer
->state
.dma_is_busy
= true;
1202 if (cmd_buffer
->device
->physical_device
->rad_info
.family
<= CHIP_CARRIZO
||
1203 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
) {
1204 /* If the size is not aligned, we must add a dummy copy at the end
1205 * just to align the internal counter. Otherwise, the DMA engine
1206 * would slow down by an order of magnitude for following copies.
1208 if (size
% SI_CPDMA_ALIGNMENT
)
1209 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
1211 /* If the copy begins unaligned, we must start copying from the next
1212 * aligned block and the skipped part should be copied after everything
1213 * else has been copied. Only the src alignment matters, not dst.
1215 if (src_va
% SI_CPDMA_ALIGNMENT
) {
1216 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_va
% SI_CPDMA_ALIGNMENT
);
1217 /* The main part will be skipped if the size is too small. */
1218 skipped_size
= MIN2(skipped_size
, size
);
1219 size
-= skipped_size
;
1222 main_src_va
= src_va
+ skipped_size
;
1223 main_dest_va
= dest_va
+ skipped_size
;
1226 unsigned dma_flags
= 0;
1227 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1229 si_cp_dma_prepare(cmd_buffer
, byte_count
,
1230 size
+ skipped_size
+ realign_size
,
1233 dma_flags
&= ~CP_DMA_SYNC
;
1235 si_emit_cp_dma(cmd_buffer
, main_dest_va
, main_src_va
,
1236 byte_count
, dma_flags
);
1239 main_src_va
+= byte_count
;
1240 main_dest_va
+= byte_count
;
1244 unsigned dma_flags
= 0;
1246 si_cp_dma_prepare(cmd_buffer
, skipped_size
,
1247 size
+ skipped_size
+ realign_size
,
1250 si_emit_cp_dma(cmd_buffer
, dest_va
, src_va
,
1251 skipped_size
, dma_flags
);
1254 si_cp_dma_realign_engine(cmd_buffer
, realign_size
);
1257 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1258 uint64_t size
, unsigned value
)
1264 assert(va
% 4 == 0 && size
% 4 == 0);
1266 /* Assume that we are not going to sync after the last DMA operation. */
1267 cmd_buffer
->state
.dma_is_busy
= true;
1270 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1271 unsigned dma_flags
= CP_DMA_CLEAR
;
1273 si_cp_dma_prepare(cmd_buffer
, byte_count
, size
, &dma_flags
);
1275 /* Emit the clear packet. */
1276 si_emit_cp_dma(cmd_buffer
, va
, value
, byte_count
,
1284 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
)
1286 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
< GFX7
)
1289 if (!cmd_buffer
->state
.dma_is_busy
)
1292 /* Issue a dummy DMA that copies zero bytes.
1294 * The DMA engine will see that there's no work to do and skip this
1295 * DMA request, however, the CP will see the sync flag and still wait
1296 * for all DMAs to complete.
1298 si_emit_cp_dma(cmd_buffer
, 0, 0, 0, CP_DMA_SYNC
);
1300 cmd_buffer
->state
.dma_is_busy
= false;
1303 /* For MSAA sample positions. */
1304 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1305 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1306 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1307 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1308 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1310 /* For obtaining location coordinates from registers */
1311 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1312 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1313 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1314 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1317 static const uint32_t sample_locs_1x
=
1318 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1319 static const unsigned max_dist_1x
= 0;
1320 static const uint64_t centroid_priority_1x
= 0x0000000000000000ull
;
1323 static const uint32_t sample_locs_2x
=
1324 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1325 static const unsigned max_dist_2x
= 4;
1326 static const uint64_t centroid_priority_2x
= 0x1010101010101010ull
;
1329 static const uint32_t sample_locs_4x
=
1330 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1331 static const unsigned max_dist_4x
= 6;
1332 static const uint64_t centroid_priority_4x
= 0x3210321032103210ull
;
1335 static const uint32_t sample_locs_8x
[] = {
1336 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1337 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1338 /* The following are unused by hardware, but we emit them to IBs
1339 * instead of multiple SET_CONTEXT_REG packets. */
1343 static const unsigned max_dist_8x
= 7;
1344 static const uint64_t centroid_priority_8x
= 0x7654321076543210ull
;
1346 unsigned radv_get_default_max_sample_dist(int log_samples
)
1348 unsigned max_dist
[] = {
1354 return max_dist
[log_samples
];
1357 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
)
1359 switch (nr_samples
) {
1362 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1363 radeon_emit(cs
, centroid_priority_1x
);
1364 radeon_emit(cs
, centroid_priority_1x
>> 32);
1365 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_1x
);
1366 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_1x
);
1367 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_1x
);
1368 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_1x
);
1371 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1372 radeon_emit(cs
, centroid_priority_2x
);
1373 radeon_emit(cs
, centroid_priority_2x
>> 32);
1374 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
);
1375 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
);
1376 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
);
1377 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
);
1380 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1381 radeon_emit(cs
, centroid_priority_4x
);
1382 radeon_emit(cs
, centroid_priority_4x
>> 32);
1383 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
);
1384 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
);
1385 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
);
1386 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
);
1389 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
1390 radeon_emit(cs
, centroid_priority_8x
);
1391 radeon_emit(cs
, centroid_priority_8x
>> 32);
1392 radeon_set_context_reg_seq(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
1393 radeon_emit_array(cs
, sample_locs_8x
, 4);
1394 radeon_emit_array(cs
, sample_locs_8x
, 4);
1395 radeon_emit_array(cs
, sample_locs_8x
, 4);
1396 radeon_emit_array(cs
, sample_locs_8x
, 2);
1401 static void radv_get_sample_position(struct radv_device
*device
,
1402 unsigned sample_count
,
1403 unsigned sample_index
, float *out_value
)
1405 const uint32_t *sample_locs
;
1407 switch (sample_count
) {
1410 sample_locs
= &sample_locs_1x
;
1413 sample_locs
= &sample_locs_2x
;
1416 sample_locs
= &sample_locs_4x
;
1419 sample_locs
= sample_locs_8x
;
1423 out_value
[0] = (GET_SX(sample_locs
, sample_index
) + 8) / 16.0f
;
1424 out_value
[1] = (GET_SY(sample_locs
, sample_index
) + 8) / 16.0f
;
1427 void radv_device_init_msaa(struct radv_device
*device
)
1431 radv_get_sample_position(device
, 1, 0, device
->sample_locations_1x
[0]);
1433 for (i
= 0; i
< 2; i
++)
1434 radv_get_sample_position(device
, 2, i
, device
->sample_locations_2x
[i
]);
1435 for (i
= 0; i
< 4; i
++)
1436 radv_get_sample_position(device
, 4, i
, device
->sample_locations_4x
[i
]);
1437 for (i
= 0; i
< 8; i
++)
1438 radv_get_sample_position(device
, 8, i
, device
->sample_locations_8x
[i
]);