2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
6 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 /* command buffer handling for SI */
30 #include "radv_private.h"
31 #include "radv_shader.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
39 si_write_harvested_raster_configs(struct radv_physical_device
*physical_device
,
40 struct radeon_cmdbuf
*cs
,
41 unsigned raster_config
,
42 unsigned raster_config_1
)
44 unsigned num_se
= MAX2(physical_device
->rad_info
.max_se
, 1);
45 unsigned raster_config_se
[4];
48 ac_get_harvested_configs(&physical_device
->rad_info
,
53 for (se
= 0; se
< num_se
; se
++) {
54 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
55 if (physical_device
->rad_info
.chip_class
< CIK
)
56 radeon_set_config_reg(cs
, R_00802C_GRBM_GFX_INDEX
,
57 S_00802C_SE_INDEX(se
) |
58 S_00802C_SH_BROADCAST_WRITES(1) |
59 S_00802C_INSTANCE_BROADCAST_WRITES(1));
61 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
62 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
63 S_030800_INSTANCE_BROADCAST_WRITES(1));
64 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
67 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
68 if (physical_device
->rad_info
.chip_class
< CIK
)
69 radeon_set_config_reg(cs
, R_00802C_GRBM_GFX_INDEX
,
70 S_00802C_SE_BROADCAST_WRITES(1) |
71 S_00802C_SH_BROADCAST_WRITES(1) |
72 S_00802C_INSTANCE_BROADCAST_WRITES(1));
74 radeon_set_uconfig_reg(cs
, R_030800_GRBM_GFX_INDEX
,
75 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
76 S_030800_INSTANCE_BROADCAST_WRITES(1));
78 if (physical_device
->rad_info
.chip_class
>= CIK
)
79 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
83 si_emit_compute(struct radv_physical_device
*physical_device
,
84 struct radeon_cmdbuf
*cs
)
86 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
91 radeon_set_sh_reg_seq(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
92 S_00B854_WAVES_PER_SH(0x3));
94 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
95 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
96 radeon_emit(cs
, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
98 if (physical_device
->rad_info
.chip_class
>= CIK
) {
99 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
100 radeon_set_sh_reg_seq(cs
,
101 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
102 radeon_emit(cs
, S_00B864_SH0_CU_EN(0xffff) |
103 S_00B864_SH1_CU_EN(0xffff));
104 radeon_emit(cs
, S_00B868_SH0_CU_EN(0xffff) |
105 S_00B868_SH1_CU_EN(0xffff));
108 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
109 * and is now per pipe, so it should be handled in the
110 * kernel if we want to use something other than the default value,
111 * which is now 0x22f.
113 if (physical_device
->rad_info
.chip_class
<= SI
) {
114 /* XXX: This should be:
115 * (number of compute units) * 4 * (waves per simd) - 1 */
117 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
118 0x190 /* Default value */);
123 si_init_compute(struct radv_cmd_buffer
*cmd_buffer
)
125 struct radv_physical_device
*physical_device
= cmd_buffer
->device
->physical_device
;
126 si_emit_compute(physical_device
, cmd_buffer
->cs
);
129 /* 12.4 fixed-point */
130 static unsigned radv_pack_float_12p4(float x
)
133 x
>= 4096 ? 0xffff : x
* 16;
137 si_set_raster_config(struct radv_physical_device
*physical_device
,
138 struct radeon_cmdbuf
*cs
)
140 unsigned num_rb
= MIN2(physical_device
->rad_info
.num_render_backends
, 16);
141 unsigned rb_mask
= physical_device
->rad_info
.enabled_rb_mask
;
142 unsigned raster_config
, raster_config_1
;
144 ac_get_raster_config(&physical_device
->rad_info
,
148 /* Always use the default config when all backends are enabled
149 * (or when we failed to determine the enabled backends).
151 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
152 radeon_set_context_reg(cs
, R_028350_PA_SC_RASTER_CONFIG
,
154 if (physical_device
->rad_info
.chip_class
>= CIK
)
155 radeon_set_context_reg(cs
, R_028354_PA_SC_RASTER_CONFIG_1
,
158 si_write_harvested_raster_configs(physical_device
, cs
,
165 si_emit_config(struct radv_physical_device
*physical_device
,
166 struct radeon_cmdbuf
*cs
)
170 /* Only SI can disable CLEAR_STATE for now. */
171 assert(physical_device
->has_clear_state
||
172 physical_device
->rad_info
.chip_class
== SI
);
174 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
175 radeon_emit(cs
, CONTEXT_CONTROL_LOAD_ENABLE(1));
176 radeon_emit(cs
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
178 if (physical_device
->has_clear_state
) {
179 radeon_emit(cs
, PKT3(PKT3_CLEAR_STATE
, 0, 0));
183 if (physical_device
->rad_info
.chip_class
<= VI
)
184 si_set_raster_config(physical_device
, cs
);
186 radeon_set_context_reg(cs
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
187 if (!physical_device
->has_clear_state
)
188 radeon_set_context_reg(cs
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
190 /* FIXME calculate these values somehow ??? */
191 if (physical_device
->rad_info
.chip_class
<= VI
) {
192 radeon_set_context_reg(cs
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
193 radeon_set_context_reg(cs
, R_028A58_VGT_ES_PER_GS
, 0x40);
196 if (!physical_device
->has_clear_state
) {
197 radeon_set_context_reg(cs
, R_028A5C_VGT_GS_PER_VS
, 0x2);
198 radeon_set_context_reg(cs
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
199 radeon_set_context_reg(cs
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
202 radeon_set_context_reg(cs
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
203 if (!physical_device
->has_clear_state
)
204 radeon_set_context_reg(cs
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
205 if (physical_device
->rad_info
.chip_class
< CIK
)
206 radeon_set_config_reg(cs
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
207 S_008A14_CLIP_VTX_REORDER_ENA(1));
209 radeon_set_context_reg(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
210 radeon_set_context_reg(cs
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
212 if (!physical_device
->has_clear_state
)
213 radeon_set_context_reg(cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
215 /* CLEAR_STATE doesn't clear these correctly on certain generations.
216 * I don't know why. Deduced by trial and error.
218 if (physical_device
->rad_info
.chip_class
<= CIK
) {
219 radeon_set_context_reg(cs
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
220 radeon_set_context_reg(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
,
221 S_028204_WINDOW_OFFSET_DISABLE(1));
222 radeon_set_context_reg(cs
, R_028240_PA_SC_GENERIC_SCISSOR_TL
,
223 S_028240_WINDOW_OFFSET_DISABLE(1));
224 radeon_set_context_reg(cs
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
225 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
226 radeon_set_context_reg(cs
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
227 radeon_set_context_reg(cs
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
228 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
231 if (!physical_device
->has_clear_state
) {
232 for (i
= 0; i
< 16; i
++) {
233 radeon_set_context_reg(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+ i
*8, 0);
234 radeon_set_context_reg(cs
, R_0282D4_PA_SC_VPORT_ZMAX_0
+ i
*8, fui(1.0));
238 if (!physical_device
->has_clear_state
) {
239 radeon_set_context_reg(cs
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
240 radeon_set_context_reg(cs
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
241 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
242 radeon_set_context_reg(cs
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
243 radeon_set_context_reg(cs
, R_028820_PA_CL_NANINF_CNTL
, 0);
244 radeon_set_context_reg(cs
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
245 radeon_set_context_reg(cs
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
246 radeon_set_context_reg(cs
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
249 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
,
250 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
251 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
253 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
254 radeon_set_uconfig_reg(cs
, R_030920_VGT_MAX_VTX_INDX
, ~0);
255 radeon_set_uconfig_reg(cs
, R_030924_VGT_MIN_VTX_INDX
, 0);
256 radeon_set_uconfig_reg(cs
, R_030928_VGT_INDX_OFFSET
, 0);
258 /* These registers, when written, also overwrite the
259 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
260 * them. It would be an issue if there was another UMD
263 radeon_set_context_reg(cs
, R_028400_VGT_MAX_VTX_INDX
, ~0);
264 radeon_set_context_reg(cs
, R_028404_VGT_MIN_VTX_INDX
, 0);
265 radeon_set_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, 0);
268 if (physical_device
->rad_info
.chip_class
>= CIK
) {
269 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
270 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
271 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
273 radeon_set_sh_reg(cs
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
274 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
275 radeon_set_sh_reg(cs
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
276 S_00B41C_WAVE_LIMIT(0x3F));
277 radeon_set_sh_reg(cs
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
278 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
279 /* If this is 0, Bonaire can hang even if GS isn't being used.
280 * Other chips are unaffected. These are suboptimal values,
281 * but we don't use on-chip GS.
283 radeon_set_context_reg(cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
284 S_028A44_ES_VERTS_PER_SUBGRP(64) |
285 S_028A44_GS_PRIMS_PER_SUBGRP(4));
287 radeon_set_sh_reg(cs
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
288 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
290 if (physical_device
->rad_info
.num_good_compute_units
/
291 (physical_device
->rad_info
.max_se
* physical_device
->rad_info
.max_sh_per_se
) <= 4) {
292 /* Too few available compute units per SH. Disallowing
293 * VS to run on CU0 could hurt us more than late VS
294 * allocation would help.
296 * LATE_ALLOC_VS = 2 is the highest safe number.
298 radeon_set_sh_reg(cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
299 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
300 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(2));
302 /* Set LATE_ALLOC_VS == 31. It should be less than
303 * the number of scratch waves. Limitations:
304 * - VS can't execute on CU0.
305 * - If HS writes outputs to LDS, LS can't execute on CU0.
307 radeon_set_sh_reg(cs
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
308 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
309 radeon_set_sh_reg(cs
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(31));
312 radeon_set_sh_reg(cs
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
313 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
316 if (physical_device
->rad_info
.chip_class
>= VI
) {
317 uint32_t vgt_tess_distribution
;
318 radeon_set_context_reg(cs
, R_028424_CB_DCC_CONTROL
,
319 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
320 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
322 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) |
323 S_028B50_ACCUM_TRI(11) |
324 S_028B50_ACCUM_QUAD(11) |
325 S_028B50_DONUT_SPLIT(16);
327 if (physical_device
->rad_info
.family
== CHIP_FIJI
||
328 physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
329 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
331 radeon_set_context_reg(cs
, R_028B50_VGT_TESS_DISTRIBUTION
,
332 vgt_tess_distribution
);
333 } else if (!physical_device
->has_clear_state
) {
334 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
335 radeon_set_context_reg(cs
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
338 if (physical_device
->rad_info
.chip_class
>= GFX9
) {
339 unsigned num_se
= physical_device
->rad_info
.max_se
;
340 unsigned pc_lines
= 0;
342 switch (physical_device
->rad_info
.family
) {
354 radeon_set_context_reg(cs
, R_028C48_PA_SC_BINNER_CNTL_1
,
355 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
356 S_028C48_MAX_PRIM_PER_BATCH(1023));
357 radeon_set_context_reg(cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
358 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
359 radeon_set_uconfig_reg(cs
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
362 unsigned tmp
= (unsigned)(1.0 * 8.0);
363 radeon_set_context_reg_seq(cs
, R_028A00_PA_SU_POINT_SIZE
, 1);
364 radeon_emit(cs
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
365 radeon_set_context_reg_seq(cs
, R_028A04_PA_SU_POINT_MINMAX
, 1);
366 radeon_emit(cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
367 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
369 if (!physical_device
->has_clear_state
) {
370 radeon_set_context_reg(cs
, R_028004_DB_COUNT_CONTROL
,
371 S_028004_ZPASS_INCREMENT_DISABLE(1));
374 /* Enable the Polaris small primitive filter control.
375 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
376 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
377 * and AMDVLK doesn't have a workaround as well.
379 if (physical_device
->rad_info
.family
>= CHIP_POLARIS10
) {
380 unsigned small_prim_filter_cntl
=
381 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
382 /* Workaround for a hw line bug. */
383 S_028830_LINE_FILTER_DISABLE(physical_device
->rad_info
.family
<= CHIP_POLARIS12
);
385 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
386 small_prim_filter_cntl
);
389 si_emit_compute(physical_device
, cs
);
392 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
)
394 struct radv_physical_device
*physical_device
= cmd_buffer
->device
->physical_device
;
396 si_emit_config(physical_device
, cmd_buffer
->cs
);
400 cik_create_gfx_config(struct radv_device
*device
)
402 struct radeon_cmdbuf
*cs
= device
->ws
->cs_create(device
->ws
, RING_GFX
);
406 si_emit_config(device
->physical_device
, cs
);
408 while (cs
->cdw
& 7) {
409 if (device
->physical_device
->rad_info
.gfx_ib_pad_with_type2
)
410 radeon_emit(cs
, 0x80000000);
412 radeon_emit(cs
, 0xffff1000);
415 device
->gfx_init
= device
->ws
->buffer_create(device
->ws
,
418 RADEON_FLAG_CPU_ACCESS
|
419 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
420 RADEON_FLAG_READ_ONLY
);
421 if (!device
->gfx_init
)
424 void *map
= device
->ws
->buffer_map(device
->gfx_init
);
426 device
->ws
->buffer_destroy(device
->gfx_init
);
427 device
->gfx_init
= NULL
;
430 memcpy(map
, cs
->buf
, cs
->cdw
* 4);
432 device
->ws
->buffer_unmap(device
->gfx_init
);
433 device
->gfx_init_size_dw
= cs
->cdw
;
435 device
->ws
->cs_destroy(cs
);
439 get_viewport_xform(const VkViewport
*viewport
,
440 float scale
[3], float translate
[3])
442 float x
= viewport
->x
;
443 float y
= viewport
->y
;
444 float half_width
= 0.5f
* viewport
->width
;
445 float half_height
= 0.5f
* viewport
->height
;
446 double n
= viewport
->minDepth
;
447 double f
= viewport
->maxDepth
;
449 scale
[0] = half_width
;
450 translate
[0] = half_width
+ x
;
451 scale
[1] = half_height
;
452 translate
[1] = half_height
+ y
;
459 si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
460 int count
, const VkViewport
*viewports
)
465 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
466 first_vp
* 4 * 6, count
* 6);
468 for (i
= 0; i
< count
; i
++) {
469 float scale
[3], translate
[3];
472 get_viewport_xform(&viewports
[i
], scale
, translate
);
473 radeon_emit(cs
, fui(scale
[0]));
474 radeon_emit(cs
, fui(translate
[0]));
475 radeon_emit(cs
, fui(scale
[1]));
476 radeon_emit(cs
, fui(translate
[1]));
477 radeon_emit(cs
, fui(scale
[2]));
478 radeon_emit(cs
, fui(translate
[2]));
481 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
+
482 first_vp
* 4 * 2, count
* 2);
483 for (i
= 0; i
< count
; i
++) {
484 float zmin
= MIN2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
485 float zmax
= MAX2(viewports
[i
].minDepth
, viewports
[i
].maxDepth
);
486 radeon_emit(cs
, fui(zmin
));
487 radeon_emit(cs
, fui(zmax
));
491 static VkRect2D
si_scissor_from_viewport(const VkViewport
*viewport
)
493 float scale
[3], translate
[3];
496 get_viewport_xform(viewport
, scale
, translate
);
498 rect
.offset
.x
= translate
[0] - fabs(scale
[0]);
499 rect
.offset
.y
= translate
[1] - fabs(scale
[1]);
500 rect
.extent
.width
= ceilf(translate
[0] + fabs(scale
[0])) - rect
.offset
.x
;
501 rect
.extent
.height
= ceilf(translate
[1] + fabs(scale
[1])) - rect
.offset
.y
;
506 static VkRect2D
si_intersect_scissor(const VkRect2D
*a
, const VkRect2D
*b
) {
508 ret
.offset
.x
= MAX2(a
->offset
.x
, b
->offset
.x
);
509 ret
.offset
.y
= MAX2(a
->offset
.y
, b
->offset
.y
);
510 ret
.extent
.width
= MIN2(a
->offset
.x
+ a
->extent
.width
,
511 b
->offset
.x
+ b
->extent
.width
) - ret
.offset
.x
;
512 ret
.extent
.height
= MIN2(a
->offset
.y
+ a
->extent
.height
,
513 b
->offset
.y
+ b
->extent
.height
) - ret
.offset
.y
;
518 si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
519 int count
, const VkRect2D
*scissors
,
520 const VkViewport
*viewports
, bool can_use_guardband
)
523 float scale
[3], translate
[3], guardband_x
= INFINITY
, guardband_y
= INFINITY
;
524 const float max_range
= 32767.0f
;
528 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ first
* 4 * 2, count
* 2);
529 for (i
= 0; i
< count
; i
++) {
530 VkRect2D viewport_scissor
= si_scissor_from_viewport(viewports
+ i
);
531 VkRect2D scissor
= si_intersect_scissor(&scissors
[i
], &viewport_scissor
);
533 get_viewport_xform(viewports
+ i
, scale
, translate
);
534 scale
[0] = abs(scale
[0]);
535 scale
[1] = abs(scale
[1]);
542 guardband_x
= MIN2(guardband_x
, (max_range
- abs(translate
[0])) / scale
[0]);
543 guardband_y
= MIN2(guardband_y
, (max_range
- abs(translate
[1])) / scale
[1]);
545 radeon_emit(cs
, S_028250_TL_X(scissor
.offset
.x
) |
546 S_028250_TL_Y(scissor
.offset
.y
) |
547 S_028250_WINDOW_OFFSET_DISABLE(1));
548 radeon_emit(cs
, S_028254_BR_X(scissor
.offset
.x
+ scissor
.extent
.width
) |
549 S_028254_BR_Y(scissor
.offset
.y
+ scissor
.extent
.height
));
551 if (!can_use_guardband
) {
556 radeon_set_context_reg_seq(cs
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 4);
557 radeon_emit(cs
, fui(guardband_y
));
558 radeon_emit(cs
, fui(1.0));
559 radeon_emit(cs
, fui(guardband_x
));
560 radeon_emit(cs
, fui(1.0));
563 static inline unsigned
564 radv_prims_for_vertices(struct radv_prim_vertex_count
*info
, unsigned num
)
575 return 1 + ((num
- info
->min
) / info
->incr
);
579 si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
580 bool instanced_draw
, bool indirect_draw
,
581 uint32_t draw_vertex_count
)
583 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
584 enum radeon_family family
= cmd_buffer
->device
->physical_device
->rad_info
.family
;
585 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
586 const unsigned max_primgroup_in_wave
= 2;
587 /* SWITCH_ON_EOP(0) is always preferable. */
588 bool wd_switch_on_eop
= false;
589 bool ia_switch_on_eop
= false;
590 bool ia_switch_on_eoi
= false;
591 bool partial_vs_wave
= false;
592 bool partial_es_wave
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.partial_es_wave
;
593 bool multi_instances_smaller_than_primgroup
;
595 multi_instances_smaller_than_primgroup
= indirect_draw
;
596 if (!multi_instances_smaller_than_primgroup
&& instanced_draw
) {
597 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
598 if (num_prims
< cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.primgroup_size
)
599 multi_instances_smaller_than_primgroup
= true;
602 ia_switch_on_eoi
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.ia_switch_on_eoi
;
603 partial_vs_wave
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.partial_vs_wave
;
605 if (chip_class
>= CIK
) {
606 wd_switch_on_eop
= cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.wd_switch_on_eop
;
608 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
609 * We don't know that for indirect drawing, so treat it as
610 * always problematic. */
611 if (family
== CHIP_HAWAII
&&
612 (instanced_draw
|| indirect_draw
))
613 wd_switch_on_eop
= true;
615 /* Performance recommendation for 4 SE Gfx7-8 parts if
616 * instances are smaller than a primgroup.
617 * Assume indirect draws always use small instances.
618 * This is needed for good VS wave utilization.
620 if (chip_class
<= VI
&&
622 multi_instances_smaller_than_primgroup
)
623 wd_switch_on_eop
= true;
625 /* Required on CIK and later. */
626 if (info
->max_se
> 2 && !wd_switch_on_eop
)
627 ia_switch_on_eoi
= true;
629 /* Required by Hawaii and, for some special cases, by VI. */
630 if (ia_switch_on_eoi
&&
631 (family
== CHIP_HAWAII
||
633 /* max primgroup in wave is always 2 - leave this for documentation */
634 (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
) || max_primgroup_in_wave
!= 2))))
635 partial_vs_wave
= true;
637 /* Instancing bug on Bonaire. */
638 if (family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
639 (instanced_draw
|| indirect_draw
))
640 partial_vs_wave
= true;
642 /* If the WD switch is false, the IA switch must be false too. */
643 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
645 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
646 if (chip_class
<= VI
&& ia_switch_on_eoi
)
647 partial_es_wave
= true;
649 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
)) {
650 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
651 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
652 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
654 if (family
== CHIP_HAWAII
&& ia_switch_on_eoi
) {
655 bool set_vgt_flush
= indirect_draw
;
656 if (!set_vgt_flush
&& instanced_draw
) {
657 uint32_t num_prims
= radv_prims_for_vertices(&cmd_buffer
->state
.pipeline
->graphics
.prim_vertex_count
, draw_vertex_count
);
659 set_vgt_flush
= true;
662 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
666 return cmd_buffer
->state
.pipeline
->graphics
.ia_multi_vgt_param
.base
|
667 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
668 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
669 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
670 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
671 S_028AA8_WD_SWITCH_ON_EOP(chip_class
>= CIK
? wd_switch_on_eop
: 0);
675 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
677 enum chip_class chip_class
,
679 unsigned event
, unsigned event_flags
,
685 unsigned op
= EVENT_TYPE(event
) |
688 unsigned is_gfx8_mec
= is_mec
&& chip_class
< GFX9
;
689 unsigned sel
= EOP_DATA_SEL(data_sel
);
691 /* Wait for write confirmation before writing data, but don't send
693 if (data_sel
!= EOP_DATA_SEL_DISCARD
)
694 sel
|= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
);
696 if (chip_class
>= GFX9
|| is_gfx8_mec
) {
697 radeon_emit(cs
, PKT3(PKT3_RELEASE_MEM
, is_gfx8_mec
? 5 : 6, predicated
));
699 radeon_emit(cs
, sel
);
700 radeon_emit(cs
, va
); /* address lo */
701 radeon_emit(cs
, va
>> 32); /* address hi */
702 radeon_emit(cs
, new_fence
); /* immediate data lo */
703 radeon_emit(cs
, 0); /* immediate data hi */
705 radeon_emit(cs
, 0); /* unused */
707 if (chip_class
== CIK
||
709 /* Two EOP events are required to make all engines go idle
710 * (and optional cache flushes executed) before the timestamp
713 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, predicated
));
716 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
717 radeon_emit(cs
, old_fence
); /* immediate data */
718 radeon_emit(cs
, 0); /* unused */
721 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, predicated
));
724 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
725 radeon_emit(cs
, new_fence
); /* immediate data */
726 radeon_emit(cs
, 0); /* unused */
731 si_emit_wait_fence(struct radeon_cmdbuf
*cs
,
733 uint64_t va
, uint32_t ref
,
736 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, predicated
));
737 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
739 radeon_emit(cs
, va
>> 32);
740 radeon_emit(cs
, ref
); /* reference value */
741 radeon_emit(cs
, mask
); /* mask */
742 radeon_emit(cs
, 4); /* poll interval */
746 si_emit_acquire_mem(struct radeon_cmdbuf
*cs
,
750 unsigned cp_coher_cntl
)
752 if (is_mec
|| is_gfx9
) {
753 uint32_t hi_val
= is_gfx9
? 0xffffff : 0xff;
754 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, predicated
) |
755 PKT3_SHADER_TYPE_S(is_mec
));
756 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
757 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
758 radeon_emit(cs
, hi_val
); /* CP_COHER_SIZE_HI */
759 radeon_emit(cs
, 0); /* CP_COHER_BASE */
760 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
761 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
763 /* ACQUIRE_MEM is only required on a compute ring. */
764 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, predicated
));
765 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
766 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
767 radeon_emit(cs
, 0); /* CP_COHER_BASE */
768 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
773 si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
774 enum chip_class chip_class
,
778 enum radv_cmd_flush_bits flush_bits
)
780 unsigned cp_coher_cntl
= 0;
781 uint32_t flush_cb_db
= flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
782 RADV_CMD_FLAG_FLUSH_AND_INV_DB
);
784 if (flush_bits
& RADV_CMD_FLAG_INV_ICACHE
)
785 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
786 if (flush_bits
& RADV_CMD_FLAG_INV_SMEM_L1
)
787 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
789 if (chip_class
<= VI
) {
790 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB
) {
791 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
792 S_0085F0_CB0_DEST_BASE_ENA(1) |
793 S_0085F0_CB1_DEST_BASE_ENA(1) |
794 S_0085F0_CB2_DEST_BASE_ENA(1) |
795 S_0085F0_CB3_DEST_BASE_ENA(1) |
796 S_0085F0_CB4_DEST_BASE_ENA(1) |
797 S_0085F0_CB5_DEST_BASE_ENA(1) |
798 S_0085F0_CB6_DEST_BASE_ENA(1) |
799 S_0085F0_CB7_DEST_BASE_ENA(1);
801 /* Necessary for DCC */
802 if (chip_class
>= VI
) {
803 si_cs_emit_write_event_eop(cs
,
807 V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
809 EOP_DATA_SEL_DISCARD
,
813 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB
) {
814 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
815 S_0085F0_DB_DEST_BASE_ENA(1);
819 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) {
820 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
821 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
824 if (flush_bits
& RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) {
825 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
826 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
829 if (flush_bits
& RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) {
830 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
831 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
832 } else if (flush_bits
& RADV_CMD_FLAG_VS_PARTIAL_FLUSH
) {
833 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
834 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
837 if (flush_bits
& RADV_CMD_FLAG_CS_PARTIAL_FLUSH
) {
838 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
839 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
842 if (chip_class
>= GFX9
&& flush_cb_db
) {
843 unsigned cb_db_event
, tc_flags
;
845 /* Set the CB/DB flush event. */
846 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
848 /* These are the only allowed combinations. If you need to
849 * do multiple operations at once, do them separately.
850 * All operations that invalidate L2 also seem to invalidate
851 * metadata. Volatile (VOL) and WC flushes are not listed here.
853 * TC | TC_WB = writeback & invalidate L2 & L1
854 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
855 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
856 * TC | TC_NC = invalidate L2 for MTYPE == NC
857 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
858 * TCL1 = invalidate L1
860 tc_flags
= EVENT_TC_ACTION_ENA
|
861 EVENT_TC_MD_ACTION_ENA
;
863 /* Ideally flush TC together with CB/DB. */
864 if (flush_bits
& RADV_CMD_FLAG_INV_GLOBAL_L2
) {
865 /* Writeback and invalidate everything in L2 & L1. */
866 tc_flags
= EVENT_TC_ACTION_ENA
|
867 EVENT_TC_WB_ACTION_ENA
;
870 /* Clear the flags. */
871 flush_bits
&= ~(RADV_CMD_FLAG_INV_GLOBAL_L2
|
872 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
|
873 RADV_CMD_FLAG_INV_VMEM_L1
);
876 uint32_t old_fence
= (*flush_cnt
)++;
878 si_cs_emit_write_event_eop(cs
, false, chip_class
, false, cb_db_event
, tc_flags
,
879 EOP_DATA_SEL_VALUE_32BIT
,
880 flush_va
, old_fence
, *flush_cnt
);
881 si_emit_wait_fence(cs
, false, flush_va
, *flush_cnt
, 0xffffffff);
885 if (flush_bits
& RADV_CMD_FLAG_VGT_FLUSH
) {
886 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
887 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
890 /* Make sure ME is idle (it executes most packets) before continuing.
891 * This prevents read-after-write hazards between PFP and ME.
893 if ((cp_coher_cntl
||
894 (flush_bits
& (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
895 RADV_CMD_FLAG_INV_VMEM_L1
|
896 RADV_CMD_FLAG_INV_GLOBAL_L2
|
897 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
))) &&
899 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
903 if ((flush_bits
& RADV_CMD_FLAG_INV_GLOBAL_L2
) ||
904 (chip_class
<= CIK
&& (flush_bits
& RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
))) {
905 si_emit_acquire_mem(cs
, is_mec
, false, chip_class
>= GFX9
,
907 S_0085F0_TC_ACTION_ENA(1) |
908 S_0085F0_TCL1_ACTION_ENA(1) |
909 S_0301F0_TC_WB_ACTION_ENA(chip_class
>= VI
));
912 if(flush_bits
& RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
) {
914 * NC = apply to non-coherent MTYPEs
915 * (i.e. MTYPE <= 1, which is what we use everywhere)
917 * WB doesn't work without NC.
919 si_emit_acquire_mem(cs
, is_mec
, false,
922 S_0301F0_TC_WB_ACTION_ENA(1) |
923 S_0301F0_TC_NC_ACTION_ENA(1));
926 if (flush_bits
& RADV_CMD_FLAG_INV_VMEM_L1
) {
927 si_emit_acquire_mem(cs
, is_mec
,
928 false, chip_class
>= GFX9
,
930 S_0085F0_TCL1_ACTION_ENA(1));
935 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
936 * Therefore, it should be last. Done in PFP.
939 si_emit_acquire_mem(cs
, is_mec
, false, chip_class
>= GFX9
, cp_coher_cntl
);
941 if (flush_bits
& RADV_CMD_FLAG_START_PIPELINE_STATS
) {
942 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
943 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
945 } else if (flush_bits
& RADV_CMD_FLAG_STOP_PIPELINE_STATS
) {
946 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
947 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
953 si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
)
955 bool is_compute
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
958 cmd_buffer
->state
.flush_bits
&= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
959 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
960 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
961 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
962 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
963 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
|
964 RADV_CMD_FLAG_VGT_FLUSH
);
966 if (!cmd_buffer
->state
.flush_bits
)
969 enum chip_class chip_class
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
970 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 128);
972 uint32_t *ptr
= NULL
;
974 if (chip_class
== GFX9
) {
975 va
= radv_buffer_get_va(cmd_buffer
->gfx9_fence_bo
) + cmd_buffer
->gfx9_fence_offset
;
976 ptr
= &cmd_buffer
->gfx9_fence_idx
;
978 si_cs_emit_cache_flush(cmd_buffer
->cs
,
979 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
981 radv_cmd_buffer_uses_mec(cmd_buffer
),
982 cmd_buffer
->state
.flush_bits
);
985 if (unlikely(cmd_buffer
->device
->trace_bo
))
986 radv_cmd_buffer_trace_emit(cmd_buffer
);
988 cmd_buffer
->state
.flush_bits
= 0;
991 /* sets the CP predication state using a boolean stored at va */
993 si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
998 op
= PRED_OP(PREDICATION_OP_BOOL64
) | PREDICATION_DRAW_VISIBLE
;
999 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1000 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 2, 0));
1001 radeon_emit(cmd_buffer
->cs
, op
);
1002 radeon_emit(cmd_buffer
->cs
, va
);
1003 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1005 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_SET_PREDICATION
, 1, 0));
1006 radeon_emit(cmd_buffer
->cs
, va
);
1007 radeon_emit(cmd_buffer
->cs
, op
| ((va
>> 32) & 0xFF));
1011 /* Set this if you want the 3D engine to wait until CP DMA is done.
1012 * It should be set on the last CP DMA packet. */
1013 #define CP_DMA_SYNC (1 << 0)
1015 /* Set this if the source data was used as a destination in a previous CP DMA
1016 * packet. It's for preventing a read-after-write (RAW) hazard between two
1017 * CP DMA packets. */
1018 #define CP_DMA_RAW_WAIT (1 << 1)
1019 #define CP_DMA_USE_L2 (1 << 2)
1020 #define CP_DMA_CLEAR (1 << 3)
1022 /* Alignment for optimal performance. */
1023 #define SI_CPDMA_ALIGNMENT 32
1025 /* The max number of bytes that can be copied per packet. */
1026 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer
*cmd_buffer
)
1028 unsigned max
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
?
1029 S_414_BYTE_COUNT_GFX9(~0u) :
1030 S_414_BYTE_COUNT_GFX6(~0u);
1032 /* make it aligned for optimal performance */
1033 return max
& ~(SI_CPDMA_ALIGNMENT
- 1);
1036 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1037 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1040 static void si_emit_cp_dma(struct radv_cmd_buffer
*cmd_buffer
,
1041 uint64_t dst_va
, uint64_t src_va
,
1042 unsigned size
, unsigned flags
)
1044 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1045 uint32_t header
= 0, command
= 0;
1048 assert(size
<= cp_dma_max_byte_count(cmd_buffer
));
1050 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 9);
1051 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1052 command
|= S_414_BYTE_COUNT_GFX9(size
);
1054 command
|= S_414_BYTE_COUNT_GFX6(size
);
1057 if (flags
& CP_DMA_SYNC
)
1058 header
|= S_411_CP_SYNC(1);
1060 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1061 command
|= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1063 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1066 if (flags
& CP_DMA_RAW_WAIT
)
1067 command
|= S_414_RAW_WAIT(1);
1069 /* Src and dst flags. */
1070 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1071 !(flags
& CP_DMA_CLEAR
) &&
1073 header
|= S_411_DSL_SEL(V_411_NOWHERE
); /* prefetch only */
1074 else if (flags
& CP_DMA_USE_L2
)
1075 header
|= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2
);
1077 if (flags
& CP_DMA_CLEAR
)
1078 header
|= S_411_SRC_SEL(V_411_DATA
);
1079 else if (flags
& CP_DMA_USE_L2
)
1080 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
);
1082 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1083 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, cmd_buffer
->state
.predicating
));
1084 radeon_emit(cs
, header
);
1085 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1086 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
1087 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1088 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
1089 radeon_emit(cs
, command
);
1091 assert(!(flags
& CP_DMA_USE_L2
));
1092 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
1093 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, cmd_buffer
->state
.predicating
));
1094 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
1095 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
1096 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
1097 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1098 radeon_emit(cs
, command
);
1101 /* CP DMA is executed in ME, but index buffers are read by PFP.
1102 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1103 * indices. If we wanted to execute CP DMA in PFP, this packet
1104 * should precede it.
1106 if ((flags
& CP_DMA_SYNC
) && cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
1107 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1111 if (unlikely(cmd_buffer
->device
->trace_bo
))
1112 radv_cmd_buffer_trace_emit(cmd_buffer
);
1115 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1118 uint64_t aligned_va
= va
& ~(SI_CPDMA_ALIGNMENT
- 1);
1119 uint64_t aligned_size
= ((va
+ size
+ SI_CPDMA_ALIGNMENT
-1) & ~(SI_CPDMA_ALIGNMENT
- 1)) - aligned_va
;
1121 si_emit_cp_dma(cmd_buffer
, aligned_va
, aligned_va
,
1122 aligned_size
, CP_DMA_USE_L2
);
1125 static void si_cp_dma_prepare(struct radv_cmd_buffer
*cmd_buffer
, uint64_t byte_count
,
1126 uint64_t remaining_size
, unsigned *flags
)
1129 /* Flush the caches for the first copy only.
1130 * Also wait for the previous CP DMA operations.
1132 if (cmd_buffer
->state
.flush_bits
) {
1133 si_emit_cache_flush(cmd_buffer
);
1134 *flags
|= CP_DMA_RAW_WAIT
;
1137 /* Do the synchronization after the last dma, so that all data
1138 * is written to memory.
1140 if (byte_count
== remaining_size
)
1141 *flags
|= CP_DMA_SYNC
;
1144 static void si_cp_dma_realign_engine(struct radv_cmd_buffer
*cmd_buffer
, unsigned size
)
1148 unsigned dma_flags
= 0;
1149 unsigned buf_size
= SI_CPDMA_ALIGNMENT
* 2;
1152 assert(size
< SI_CPDMA_ALIGNMENT
);
1154 radv_cmd_buffer_upload_alloc(cmd_buffer
, buf_size
, SI_CPDMA_ALIGNMENT
, &offset
, &ptr
);
1156 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1159 si_cp_dma_prepare(cmd_buffer
, size
, size
, &dma_flags
);
1161 si_emit_cp_dma(cmd_buffer
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
,
1165 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1166 uint64_t src_va
, uint64_t dest_va
,
1169 uint64_t main_src_va
, main_dest_va
;
1170 uint64_t skipped_size
= 0, realign_size
= 0;
1173 if (cmd_buffer
->device
->physical_device
->rad_info
.family
<= CHIP_CARRIZO
||
1174 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
) {
1175 /* If the size is not aligned, we must add a dummy copy at the end
1176 * just to align the internal counter. Otherwise, the DMA engine
1177 * would slow down by an order of magnitude for following copies.
1179 if (size
% SI_CPDMA_ALIGNMENT
)
1180 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
1182 /* If the copy begins unaligned, we must start copying from the next
1183 * aligned block and the skipped part should be copied after everything
1184 * else has been copied. Only the src alignment matters, not dst.
1186 if (src_va
% SI_CPDMA_ALIGNMENT
) {
1187 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_va
% SI_CPDMA_ALIGNMENT
);
1188 /* The main part will be skipped if the size is too small. */
1189 skipped_size
= MIN2(skipped_size
, size
);
1190 size
-= skipped_size
;
1193 main_src_va
= src_va
+ skipped_size
;
1194 main_dest_va
= dest_va
+ skipped_size
;
1197 unsigned dma_flags
= 0;
1198 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1200 si_cp_dma_prepare(cmd_buffer
, byte_count
,
1201 size
+ skipped_size
+ realign_size
,
1204 si_emit_cp_dma(cmd_buffer
, main_dest_va
, main_src_va
,
1205 byte_count
, dma_flags
);
1208 main_src_va
+= byte_count
;
1209 main_dest_va
+= byte_count
;
1213 unsigned dma_flags
= 0;
1215 si_cp_dma_prepare(cmd_buffer
, skipped_size
,
1216 size
+ skipped_size
+ realign_size
,
1219 si_emit_cp_dma(cmd_buffer
, dest_va
, src_va
,
1220 skipped_size
, dma_flags
);
1223 si_cp_dma_realign_engine(cmd_buffer
, realign_size
);
1226 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1227 uint64_t size
, unsigned value
)
1233 assert(va
% 4 == 0 && size
% 4 == 0);
1236 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(cmd_buffer
));
1237 unsigned dma_flags
= CP_DMA_CLEAR
;
1239 si_cp_dma_prepare(cmd_buffer
, byte_count
, size
, &dma_flags
);
1241 /* Emit the clear packet. */
1242 si_emit_cp_dma(cmd_buffer
, va
, value
, byte_count
,
1250 /* For MSAA sample positions. */
1251 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1252 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1253 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1254 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1255 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1259 * There are two locations (4, 4), (-4, -4). */
1260 const uint32_t eg_sample_locs_2x
[4] = {
1261 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1262 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1263 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1264 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1266 const unsigned eg_max_dist_2x
= 4;
1268 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1269 const uint32_t eg_sample_locs_4x
[4] = {
1270 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1271 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1272 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1273 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1275 const unsigned eg_max_dist_4x
= 6;
1278 static const uint32_t cm_sample_locs_8x
[] = {
1279 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1280 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1281 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1282 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1283 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1284 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1285 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1286 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1288 static const unsigned cm_max_dist_8x
= 8;
1289 /* Cayman 16xMSAA */
1290 static const uint32_t cm_sample_locs_16x
[] = {
1291 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1292 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1293 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1294 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1295 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1296 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1297 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1298 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1299 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1300 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1301 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1302 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1303 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1304 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1305 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1306 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1308 static const unsigned cm_max_dist_16x
= 8;
1310 unsigned radv_cayman_get_maxdist(int log_samples
)
1312 unsigned max_dist
[] = {
1319 return max_dist
[log_samples
];
1322 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf
*cs
, int nr_samples
)
1324 switch (nr_samples
) {
1327 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 0);
1328 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, 0);
1329 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, 0);
1330 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, 0);
1333 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, eg_sample_locs_2x
[0]);
1334 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, eg_sample_locs_2x
[1]);
1335 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, eg_sample_locs_2x
[2]);
1336 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, eg_sample_locs_2x
[3]);
1339 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, eg_sample_locs_4x
[0]);
1340 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, eg_sample_locs_4x
[1]);
1341 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, eg_sample_locs_4x
[2]);
1342 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, eg_sample_locs_4x
[3]);
1345 radeon_set_context_reg_seq(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
1346 radeon_emit(cs
, cm_sample_locs_8x
[0]);
1347 radeon_emit(cs
, cm_sample_locs_8x
[4]);
1350 radeon_emit(cs
, cm_sample_locs_8x
[1]);
1351 radeon_emit(cs
, cm_sample_locs_8x
[5]);
1354 radeon_emit(cs
, cm_sample_locs_8x
[2]);
1355 radeon_emit(cs
, cm_sample_locs_8x
[6]);
1358 radeon_emit(cs
, cm_sample_locs_8x
[3]);
1359 radeon_emit(cs
, cm_sample_locs_8x
[7]);
1362 radeon_set_context_reg_seq(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 16);
1363 radeon_emit(cs
, cm_sample_locs_16x
[0]);
1364 radeon_emit(cs
, cm_sample_locs_16x
[4]);
1365 radeon_emit(cs
, cm_sample_locs_16x
[8]);
1366 radeon_emit(cs
, cm_sample_locs_16x
[12]);
1367 radeon_emit(cs
, cm_sample_locs_16x
[1]);
1368 radeon_emit(cs
, cm_sample_locs_16x
[5]);
1369 radeon_emit(cs
, cm_sample_locs_16x
[9]);
1370 radeon_emit(cs
, cm_sample_locs_16x
[13]);
1371 radeon_emit(cs
, cm_sample_locs_16x
[2]);
1372 radeon_emit(cs
, cm_sample_locs_16x
[6]);
1373 radeon_emit(cs
, cm_sample_locs_16x
[10]);
1374 radeon_emit(cs
, cm_sample_locs_16x
[14]);
1375 radeon_emit(cs
, cm_sample_locs_16x
[3]);
1376 radeon_emit(cs
, cm_sample_locs_16x
[7]);
1377 radeon_emit(cs
, cm_sample_locs_16x
[11]);
1378 radeon_emit(cs
, cm_sample_locs_16x
[15]);
1383 static void radv_cayman_get_sample_position(struct radv_device
*device
,
1384 unsigned sample_count
,
1385 unsigned sample_index
, float *out_value
)
1391 switch (sample_count
) {
1394 out_value
[0] = out_value
[1] = 0.5;
1397 offset
= 4 * (sample_index
* 2);
1398 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
1399 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1400 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1401 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1404 offset
= 4 * (sample_index
* 2);
1405 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
1406 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1407 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1408 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1411 offset
= 4 * (sample_index
% 4 * 2);
1412 index
= (sample_index
/ 4) * 4;
1413 val
.idx
= (cm_sample_locs_8x
[index
] >> offset
) & 0xf;
1414 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1415 val
.idx
= (cm_sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1416 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1419 offset
= 4 * (sample_index
% 4 * 2);
1420 index
= (sample_index
/ 4) * 4;
1421 val
.idx
= (cm_sample_locs_16x
[index
] >> offset
) & 0xf;
1422 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1423 val
.idx
= (cm_sample_locs_16x
[index
] >> (offset
+ 4)) & 0xf;
1424 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1429 void radv_device_init_msaa(struct radv_device
*device
)
1432 radv_cayman_get_sample_position(device
, 1, 0, device
->sample_locations_1x
[0]);
1434 for (i
= 0; i
< 2; i
++)
1435 radv_cayman_get_sample_position(device
, 2, i
, device
->sample_locations_2x
[i
]);
1436 for (i
= 0; i
< 4; i
++)
1437 radv_cayman_get_sample_position(device
, 4, i
, device
->sample_locations_4x
[i
]);
1438 for (i
= 0; i
< 8; i
++)
1439 radv_cayman_get_sample_position(device
, 8, i
, device
->sample_locations_8x
[i
]);
1440 for (i
= 0; i
< 16; i
++)
1441 radv_cayman_get_sample_position(device
, 16, i
, device
->sample_locations_16x
[i
]);