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radv/gfx10: disable CLEAR_STATE
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
92 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
95
96 if (physical_device->rad_info.chip_class >= GFX7) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
100 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
101 S_00B858_SH1_CU_EN(0xffff));
102 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
103 S_00B858_SH1_CU_EN(0xffff));
104 }
105
106 if (physical_device->rad_info.chip_class >= GFX10)
107 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
108
109 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
110 * and is now per pipe, so it should be handled in the
111 * kernel if we want to use something other than the default value,
112 * which is now 0x22f.
113 */
114 if (physical_device->rad_info.chip_class <= GFX6) {
115 /* XXX: This should be:
116 * (number of compute units) * 4 * (waves per simd) - 1 */
117
118 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
119 0x190 /* Default value */);
120 }
121 }
122
123 /* 12.4 fixed-point */
124 static unsigned radv_pack_float_12p4(float x)
125 {
126 return x <= 0 ? 0 :
127 x >= 4096 ? 0xffff : x * 16;
128 }
129
130 static void
131 si_set_raster_config(struct radv_physical_device *physical_device,
132 struct radeon_cmdbuf *cs)
133 {
134 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
135 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
136 unsigned raster_config, raster_config_1;
137
138 ac_get_raster_config(&physical_device->rad_info,
139 &raster_config,
140 &raster_config_1, NULL);
141
142 /* Always use the default config when all backends are enabled
143 * (or when we failed to determine the enabled backends).
144 */
145 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
146 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
147 raster_config);
148 if (physical_device->rad_info.chip_class >= GFX7)
149 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
150 raster_config_1);
151 } else {
152 si_write_harvested_raster_configs(physical_device, cs,
153 raster_config,
154 raster_config_1);
155 }
156 }
157
158 void
159 si_emit_graphics(struct radv_physical_device *physical_device,
160 struct radeon_cmdbuf *cs)
161 {
162 int i;
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (physical_device->has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!physical_device->has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!physical_device->has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
193 if (!physical_device->has_clear_state)
194 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
195 if (physical_device->rad_info.chip_class < GFX7)
196 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
197 S_008A14_CLIP_VTX_REORDER_ENA(1));
198
199 if (!physical_device->has_clear_state)
200 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
201
202 /* CLEAR_STATE doesn't clear these correctly on certain generations.
203 * I don't know why. Deduced by trial and error.
204 */
205 if (physical_device->rad_info.chip_class <= GFX7) {
206 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
207 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
208 S_028204_WINDOW_OFFSET_DISABLE(1));
209 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
210 S_028240_WINDOW_OFFSET_DISABLE(1));
211 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
212 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
213 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
214 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
215 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
216 }
217
218 if (!physical_device->has_clear_state) {
219 for (i = 0; i < 16; i++) {
220 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
221 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
222 }
223 }
224
225 if (!physical_device->has_clear_state) {
226 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
227 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
228 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
229 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
230 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
231 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
232 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
233 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
234 }
235
236 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
237 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
238 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
239
240 if (physical_device->rad_info.chip_class >= GFX10) {
241 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
242 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
243 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
244 } else if (physical_device->rad_info.chip_class >= GFX9) {
245 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
246 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
247 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
248 } else {
249 /* These registers, when written, also overwrite the
250 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
251 * them. It would be an issue if there was another UMD
252 * changing them.
253 */
254 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
255 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
256 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
257 }
258
259 if (physical_device->rad_info.chip_class >= GFX7) {
260 if (physical_device->rad_info.chip_class >= GFX10) {
261 /* Logical CUs 16 - 31 */
262 radeon_set_sh_reg(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
263 S_00B404_CU_EN(0xffff));
264 radeon_set_sh_reg(cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
265 S_00B204_CU_EN(0xffff) |
266 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
267 radeon_set_sh_reg(cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
268 S_00B104_CU_EN(0xffff));
269 radeon_set_sh_reg(cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
270 S_00B004_CU_EN(0xffff));
271 }
272
273 if (physical_device->rad_info.chip_class >= GFX9) {
274 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
275 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
276 } else {
277 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
278 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
279 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
280 S_00B41C_WAVE_LIMIT(0x3F));
281 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
282 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
283 /* If this is 0, Bonaire can hang even if GS isn't being used.
284 * Other chips are unaffected. These are suboptimal values,
285 * but we don't use on-chip GS.
286 */
287 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
288 S_028A44_ES_VERTS_PER_SUBGRP(64) |
289 S_028A44_GS_PRIMS_PER_SUBGRP(4));
290 }
291 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
292 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
293
294 if (physical_device->rad_info.num_good_cu_per_sh <= 4) {
295 /* Too few available compute units per SH. Disallowing
296 * VS to run on CU0 could hurt us more than late VS
297 * allocation would help.
298 *
299 * LATE_ALLOC_VS = 2 is the highest safe number.
300 */
301 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
302 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
303 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
304 } else {
305 /* Set LATE_ALLOC_VS == 31. It should be less than
306 * the number of scratch waves. Limitations:
307 * - VS can't execute on CU0.
308 * - If HS writes outputs to LDS, LS can't execute on CU0.
309 */
310 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
311 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
312 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
313 }
314
315 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
316 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
317 }
318
319 if (physical_device->rad_info.chip_class >= GFX10) {
320 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
321 radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
322 physical_device->rad_info.pa_sc_tile_steering_override);
323 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
324 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
325 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
326 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
327 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
328 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
329 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
330 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
331
332 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
333 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
334 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
335 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
336 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
337 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
338 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
339 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
340 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
341 }
342
343 if (physical_device->rad_info.chip_class >= GFX8) {
344 uint32_t vgt_tess_distribution;
345
346 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
347 S_028B50_ACCUM_TRI(11) |
348 S_028B50_ACCUM_QUAD(11) |
349 S_028B50_DONUT_SPLIT(16);
350
351 if (physical_device->rad_info.family == CHIP_FIJI ||
352 physical_device->rad_info.family >= CHIP_POLARIS10)
353 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
354
355 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
356 vgt_tess_distribution);
357 } else if (!physical_device->has_clear_state) {
358 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
359 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
360 }
361
362 if (physical_device->rad_info.chip_class >= GFX9) {
363 unsigned num_se = physical_device->rad_info.max_se;
364 unsigned pc_lines = 0;
365 unsigned max_alloc_count = 0;
366
367 switch (physical_device->rad_info.family) {
368 case CHIP_VEGA10:
369 case CHIP_VEGA12:
370 case CHIP_VEGA20:
371 pc_lines = 4096;
372 break;
373 case CHIP_RAVEN:
374 case CHIP_RAVEN2:
375 case CHIP_NAVI10:
376 case CHIP_NAVI12:
377 pc_lines = 1024;
378 break;
379 case CHIP_NAVI14:
380 pc_lines = 512;
381 break;
382 default:
383 assert(0);
384 }
385
386 if (physical_device->rad_info.chip_class >= GFX10) {
387 max_alloc_count = pc_lines / 3;
388 } else {
389 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
390 }
391
392 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
393 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
394 S_028C48_MAX_PRIM_PER_BATCH(1023));
395 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
396 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
397 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
398 }
399
400 unsigned tmp = (unsigned)(1.0 * 8.0);
401 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
402 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
403 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
404 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
405 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
406
407 if (!physical_device->has_clear_state) {
408 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
409 S_028004_ZPASS_INCREMENT_DISABLE(1));
410 }
411
412 /* Enable the Polaris small primitive filter control.
413 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
414 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
415 * and AMDVLK doesn't have a workaround as well.
416 */
417 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
418 unsigned small_prim_filter_cntl =
419 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
420 /* Workaround for a hw line bug. */
421 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
422
423 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
424 small_prim_filter_cntl);
425 }
426
427 si_emit_compute(physical_device, cs);
428 }
429
430 void
431 cik_create_gfx_config(struct radv_device *device)
432 {
433 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
434 if (!cs)
435 return;
436
437 si_emit_graphics(device->physical_device, cs);
438
439 while (cs->cdw & 7) {
440 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
441 radeon_emit(cs, 0x80000000);
442 else
443 radeon_emit(cs, 0xffff1000);
444 }
445
446 device->gfx_init = device->ws->buffer_create(device->ws,
447 cs->cdw * 4, 4096,
448 RADEON_DOMAIN_GTT,
449 RADEON_FLAG_CPU_ACCESS|
450 RADEON_FLAG_NO_INTERPROCESS_SHARING |
451 RADEON_FLAG_READ_ONLY,
452 RADV_BO_PRIORITY_CS);
453 if (!device->gfx_init)
454 goto fail;
455
456 void *map = device->ws->buffer_map(device->gfx_init);
457 if (!map) {
458 device->ws->buffer_destroy(device->gfx_init);
459 device->gfx_init = NULL;
460 goto fail;
461 }
462 memcpy(map, cs->buf, cs->cdw * 4);
463
464 device->ws->buffer_unmap(device->gfx_init);
465 device->gfx_init_size_dw = cs->cdw;
466 fail:
467 device->ws->cs_destroy(cs);
468 }
469
470 static void
471 get_viewport_xform(const VkViewport *viewport,
472 float scale[3], float translate[3])
473 {
474 float x = viewport->x;
475 float y = viewport->y;
476 float half_width = 0.5f * viewport->width;
477 float half_height = 0.5f * viewport->height;
478 double n = viewport->minDepth;
479 double f = viewport->maxDepth;
480
481 scale[0] = half_width;
482 translate[0] = half_width + x;
483 scale[1] = half_height;
484 translate[1] = half_height + y;
485
486 scale[2] = (f - n);
487 translate[2] = n;
488 }
489
490 void
491 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
492 int count, const VkViewport *viewports)
493 {
494 int i;
495
496 assert(count);
497 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
498 first_vp * 4 * 6, count * 6);
499
500 for (i = 0; i < count; i++) {
501 float scale[3], translate[3];
502
503
504 get_viewport_xform(&viewports[i], scale, translate);
505 radeon_emit(cs, fui(scale[0]));
506 radeon_emit(cs, fui(translate[0]));
507 radeon_emit(cs, fui(scale[1]));
508 radeon_emit(cs, fui(translate[1]));
509 radeon_emit(cs, fui(scale[2]));
510 radeon_emit(cs, fui(translate[2]));
511 }
512
513 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
514 first_vp * 4 * 2, count * 2);
515 for (i = 0; i < count; i++) {
516 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
517 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
518 radeon_emit(cs, fui(zmin));
519 radeon_emit(cs, fui(zmax));
520 }
521 }
522
523 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
524 {
525 float scale[3], translate[3];
526 VkRect2D rect;
527
528 get_viewport_xform(viewport, scale, translate);
529
530 rect.offset.x = translate[0] - fabs(scale[0]);
531 rect.offset.y = translate[1] - fabs(scale[1]);
532 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
533 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
534
535 return rect;
536 }
537
538 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
539 VkRect2D ret;
540 ret.offset.x = MAX2(a->offset.x, b->offset.x);
541 ret.offset.y = MAX2(a->offset.y, b->offset.y);
542 ret.extent.width = MIN2(a->offset.x + a->extent.width,
543 b->offset.x + b->extent.width) - ret.offset.x;
544 ret.extent.height = MIN2(a->offset.y + a->extent.height,
545 b->offset.y + b->extent.height) - ret.offset.y;
546 return ret;
547 }
548
549 void
550 si_write_scissors(struct radeon_cmdbuf *cs, int first,
551 int count, const VkRect2D *scissors,
552 const VkViewport *viewports, bool can_use_guardband)
553 {
554 int i;
555 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
556 const float max_range = 32767.0f;
557 if (!count)
558 return;
559
560 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
561 for (i = 0; i < count; i++) {
562 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
563 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
564
565 get_viewport_xform(viewports + i, scale, translate);
566 scale[0] = fabsf(scale[0]);
567 scale[1] = fabsf(scale[1]);
568
569 if (scale[0] < 0.5)
570 scale[0] = 0.5;
571 if (scale[1] < 0.5)
572 scale[1] = 0.5;
573
574 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
575 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
576
577 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
578 S_028250_TL_Y(scissor.offset.y) |
579 S_028250_WINDOW_OFFSET_DISABLE(1));
580 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
581 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
582 }
583 if (!can_use_guardband) {
584 guardband_x = 1.0;
585 guardband_y = 1.0;
586 }
587
588 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
589 radeon_emit(cs, fui(guardband_y));
590 radeon_emit(cs, fui(1.0));
591 radeon_emit(cs, fui(guardband_x));
592 radeon_emit(cs, fui(1.0));
593 }
594
595 static inline unsigned
596 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
597 {
598 if (num == 0)
599 return 0;
600
601 if (info->incr == 0)
602 return 0;
603
604 if (num < info->min)
605 return 0;
606
607 return 1 + ((num - info->min) / info->incr);
608 }
609
610 uint32_t
611 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
612 bool instanced_draw, bool indirect_draw,
613 bool count_from_stream_output,
614 uint32_t draw_vertex_count)
615 {
616 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
617 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
618 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
619 const unsigned max_primgroup_in_wave = 2;
620 /* SWITCH_ON_EOP(0) is always preferable. */
621 bool wd_switch_on_eop = false;
622 bool ia_switch_on_eop = false;
623 bool ia_switch_on_eoi = false;
624 bool partial_vs_wave = false;
625 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
626 bool multi_instances_smaller_than_primgroup;
627
628 multi_instances_smaller_than_primgroup = indirect_draw;
629 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
630 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
631 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
632 multi_instances_smaller_than_primgroup = true;
633 }
634
635 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
636 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
637
638 if (chip_class >= GFX7) {
639 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
640
641 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
642 * We don't know that for indirect drawing, so treat it as
643 * always problematic. */
644 if (family == CHIP_HAWAII &&
645 (instanced_draw || indirect_draw))
646 wd_switch_on_eop = true;
647
648 /* Performance recommendation for 4 SE Gfx7-8 parts if
649 * instances are smaller than a primgroup.
650 * Assume indirect draws always use small instances.
651 * This is needed for good VS wave utilization.
652 */
653 if (chip_class <= GFX8 &&
654 info->max_se == 4 &&
655 multi_instances_smaller_than_primgroup)
656 wd_switch_on_eop = true;
657
658 /* Required on GFX7 and later. */
659 if (info->max_se > 2 && !wd_switch_on_eop)
660 ia_switch_on_eoi = true;
661
662 /* Required by Hawaii and, for some special cases, by GFX8. */
663 if (ia_switch_on_eoi &&
664 (family == CHIP_HAWAII ||
665 (chip_class == GFX8 &&
666 /* max primgroup in wave is always 2 - leave this for documentation */
667 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
668 partial_vs_wave = true;
669
670 /* Instancing bug on Bonaire. */
671 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
672 (instanced_draw || indirect_draw))
673 partial_vs_wave = true;
674
675 /* Hardware requirement when drawing primitives from a stream
676 * output buffer.
677 */
678 if (count_from_stream_output)
679 wd_switch_on_eop = true;
680
681 /* If the WD switch is false, the IA switch must be false too. */
682 assert(wd_switch_on_eop || !ia_switch_on_eop);
683 }
684 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
685 if (chip_class <= GFX8 && ia_switch_on_eoi)
686 partial_es_wave = true;
687
688 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
689 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
690 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
691 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
692 */
693 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
694 bool set_vgt_flush = indirect_draw;
695 if (!set_vgt_flush && instanced_draw) {
696 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
697 if (num_prims <= 1)
698 set_vgt_flush = true;
699 }
700 if (set_vgt_flush)
701 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
702 }
703 }
704
705 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
706 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
707 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
708 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
709 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
710 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
711
712 }
713
714 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
715 enum chip_class chip_class,
716 bool is_mec,
717 unsigned event, unsigned event_flags,
718 unsigned data_sel,
719 uint64_t va,
720 uint32_t new_fence,
721 uint64_t gfx9_eop_bug_va)
722 {
723 unsigned op = EVENT_TYPE(event) |
724 EVENT_INDEX(5) |
725 event_flags;
726 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
727 unsigned sel = EOP_DATA_SEL(data_sel);
728
729 /* Wait for write confirmation before writing data, but don't send
730 * an interrupt. */
731 if (data_sel != EOP_DATA_SEL_DISCARD)
732 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
733
734 if (chip_class >= GFX9 || is_gfx8_mec) {
735 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
736 * counters) must immediately precede every timestamp event to
737 * prevent a GPU hang on GFX9.
738 */
739 if (chip_class == GFX9 && !is_mec) {
740 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
741 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
742 radeon_emit(cs, gfx9_eop_bug_va);
743 radeon_emit(cs, gfx9_eop_bug_va >> 32);
744 }
745
746 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
747 radeon_emit(cs, op);
748 radeon_emit(cs, sel);
749 radeon_emit(cs, va); /* address lo */
750 radeon_emit(cs, va >> 32); /* address hi */
751 radeon_emit(cs, new_fence); /* immediate data lo */
752 radeon_emit(cs, 0); /* immediate data hi */
753 if (!is_gfx8_mec)
754 radeon_emit(cs, 0); /* unused */
755 } else {
756 if (chip_class == GFX7 ||
757 chip_class == GFX8) {
758 /* Two EOP events are required to make all engines go idle
759 * (and optional cache flushes executed) before the timestamp
760 * is written.
761 */
762 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
763 radeon_emit(cs, op);
764 radeon_emit(cs, va);
765 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
766 radeon_emit(cs, 0); /* immediate data */
767 radeon_emit(cs, 0); /* unused */
768 }
769
770 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
771 radeon_emit(cs, op);
772 radeon_emit(cs, va);
773 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
774 radeon_emit(cs, new_fence); /* immediate data */
775 radeon_emit(cs, 0); /* unused */
776 }
777 }
778
779 void
780 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
781 uint32_t ref, uint32_t mask)
782 {
783 assert(op == WAIT_REG_MEM_EQUAL ||
784 op == WAIT_REG_MEM_NOT_EQUAL ||
785 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
786
787 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
788 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
789 radeon_emit(cs, va);
790 radeon_emit(cs, va >> 32);
791 radeon_emit(cs, ref); /* reference value */
792 radeon_emit(cs, mask); /* mask */
793 radeon_emit(cs, 4); /* poll interval */
794 }
795
796 static void
797 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
798 bool is_mec,
799 bool is_gfx9,
800 unsigned cp_coher_cntl)
801 {
802 if (is_mec || is_gfx9) {
803 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
804 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
805 PKT3_SHADER_TYPE_S(is_mec));
806 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
807 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
808 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
809 radeon_emit(cs, 0); /* CP_COHER_BASE */
810 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
811 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
812 } else {
813 /* ACQUIRE_MEM is only required on a compute ring. */
814 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
815 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
816 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
817 radeon_emit(cs, 0); /* CP_COHER_BASE */
818 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
819 }
820 }
821
822 static void
823 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
824 enum chip_class chip_class,
825 uint32_t *flush_cnt,
826 uint64_t flush_va,
827 bool is_mec,
828 enum radv_cmd_flush_bits flush_bits,
829 uint64_t gfx9_eop_bug_va)
830 {
831 uint32_t gcr_cntl = 0;
832 unsigned cb_db_event = 0;
833
834 /* We don't need these. */
835 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_FLUSH |
836 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
837
838 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
839 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
840 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
841 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
842 * to FORWARD when both L1 and L2 are written out (WB or INV).
843 */
844 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
845 }
846 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
847 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
848 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
849 /* Writeback and invalidate everything in L2. */
850 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
851 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
852 /* Writeback but do not invalidate. */
853 gcr_cntl |= S_586_GL2_WB(1);
854 }
855
856 /* TODO: Implement this new flag for GFX9+.
857 if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
858 gcr_cntl |= S_586_GLM_INV(1);
859 */
860
861 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
862 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
863 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
864 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
865 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
866 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
867 EVENT_INDEX(0));
868 }
869
870 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
871 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
872 /* Flush HTILE. Will wait for idle later. */
873 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
874 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
875 EVENT_INDEX(0));
876 }
877
878 /* First flush CB/DB, then L1/L2. */
879 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
880
881 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
882 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
883 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
884 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
885 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
886 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
887 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
888 } else {
889 assert(0);
890 }
891 } else {
892 /* Wait for graphics shaders to go idle if requested. */
893 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
894 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
895 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
896 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
897 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
898 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
899 }
900 }
901
902 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
903 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
904 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
905 }
906
907 if (cb_db_event) {
908 /* CB/DB flush and invalidate (or possibly just a wait for a
909 * meta flush) via RELEASE_MEM.
910 *
911 * Combine this with other cache flushes when possible; this
912 * requires affected shaders to be idle, so do it after the
913 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
914 * implied).
915 */
916 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
917 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
918 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
919 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
920 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
921 assert(G_586_GL2_US(gcr_cntl) == 0);
922 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
923 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
924 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
925 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
926 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
927
928 gcr_cntl &= C_586_GLM_WB &
929 C_586_GLM_INV &
930 C_586_GLV_INV &
931 C_586_GL1_INV &
932 C_586_GL2_INV &
933 C_586_GL2_WB; /* keep SEQ */
934
935 assert(flush_cnt);
936 (*flush_cnt)++;
937
938 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
939 S_490_GLM_WB(glm_wb) |
940 S_490_GLM_INV(glm_inv) |
941 S_490_GLV_INV(glv_inv) |
942 S_490_GL1_INV(gl1_inv) |
943 S_490_GL2_INV(gl2_inv) |
944 S_490_GL2_WB(gl2_wb) |
945 S_490_SEQ(gcr_seq),
946 EOP_DATA_SEL_VALUE_32BIT,
947 flush_va, *flush_cnt,
948 gfx9_eop_bug_va);
949
950 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
951 *flush_cnt, 0xffffffff);
952 }
953
954 /* Ignore fields that only modify the behavior of other fields. */
955 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
956 /* Flush caches and wait for the caches to assert idle.
957 * The cache flush is executed in the ME, but the PFP waits
958 * for completion.
959 */
960 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
961 radeon_emit(cs, 0); /* CP_COHER_CNTL */
962 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
963 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
964 radeon_emit(cs, 0); /* CP_COHER_BASE */
965 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
966 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
967 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
968 } else if (cb_db_event ||
969 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
970 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
971 RADV_CMD_FLAG_CS_PARTIAL_FLUSH))) {
972 /* We need to ensure that PFP waits as well. */
973 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
974 radeon_emit(cs, 0);
975 }
976
977 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
978 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
979 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
980 EVENT_INDEX(0));
981 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
982 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
983 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
984 EVENT_INDEX(0));
985 }
986 }
987
988 void
989 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
990 enum chip_class chip_class,
991 uint32_t *flush_cnt,
992 uint64_t flush_va,
993 bool is_mec,
994 enum radv_cmd_flush_bits flush_bits,
995 uint64_t gfx9_eop_bug_va)
996 {
997 unsigned cp_coher_cntl = 0;
998 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
999 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1000
1001 if (chip_class >= GFX10) {
1002 /* GFX10 cache flush handling is quite different. */
1003 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1004 is_mec, flush_bits, gfx9_eop_bug_va);
1005 return;
1006 }
1007
1008 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1009 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1010 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1011 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1012
1013 if (chip_class <= GFX8) {
1014 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1015 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1016 S_0085F0_CB0_DEST_BASE_ENA(1) |
1017 S_0085F0_CB1_DEST_BASE_ENA(1) |
1018 S_0085F0_CB2_DEST_BASE_ENA(1) |
1019 S_0085F0_CB3_DEST_BASE_ENA(1) |
1020 S_0085F0_CB4_DEST_BASE_ENA(1) |
1021 S_0085F0_CB5_DEST_BASE_ENA(1) |
1022 S_0085F0_CB6_DEST_BASE_ENA(1) |
1023 S_0085F0_CB7_DEST_BASE_ENA(1);
1024
1025 /* Necessary for DCC */
1026 if (chip_class >= GFX8) {
1027 si_cs_emit_write_event_eop(cs,
1028 chip_class,
1029 is_mec,
1030 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1031 0,
1032 EOP_DATA_SEL_DISCARD,
1033 0, 0,
1034 gfx9_eop_bug_va);
1035 }
1036 }
1037 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1038 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1039 S_0085F0_DB_DEST_BASE_ENA(1);
1040 }
1041 }
1042
1043 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1044 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1045 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1046 }
1047
1048 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1049 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1050 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1051 }
1052
1053 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1054 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1055 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1056 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1057 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1058 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1059 }
1060
1061 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1062 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1063 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1064 }
1065
1066 if (chip_class >= GFX9 && flush_cb_db) {
1067 unsigned cb_db_event, tc_flags;
1068
1069 /* Set the CB/DB flush event. */
1070 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1071
1072 /* These are the only allowed combinations. If you need to
1073 * do multiple operations at once, do them separately.
1074 * All operations that invalidate L2 also seem to invalidate
1075 * metadata. Volatile (VOL) and WC flushes are not listed here.
1076 *
1077 * TC | TC_WB = writeback & invalidate L2 & L1
1078 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1079 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1080 * TC | TC_NC = invalidate L2 for MTYPE == NC
1081 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1082 * TCL1 = invalidate L1
1083 */
1084 tc_flags = EVENT_TC_ACTION_ENA |
1085 EVENT_TC_MD_ACTION_ENA;
1086
1087 /* Ideally flush TC together with CB/DB. */
1088 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1089 /* Writeback and invalidate everything in L2 & L1. */
1090 tc_flags = EVENT_TC_ACTION_ENA |
1091 EVENT_TC_WB_ACTION_ENA;
1092
1093
1094 /* Clear the flags. */
1095 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1096 RADV_CMD_FLAG_WB_L2 |
1097 RADV_CMD_FLAG_INV_VCACHE);
1098 }
1099 assert(flush_cnt);
1100 (*flush_cnt)++;
1101
1102 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1103 EOP_DATA_SEL_VALUE_32BIT,
1104 flush_va, *flush_cnt,
1105 gfx9_eop_bug_va);
1106 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1107 *flush_cnt, 0xffffffff);
1108 }
1109
1110 /* VGT state sync */
1111 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1112 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1113 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1114 }
1115
1116 /* VGT streamout state sync */
1117 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1118 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1119 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1120 }
1121
1122 /* Make sure ME is idle (it executes most packets) before continuing.
1123 * This prevents read-after-write hazards between PFP and ME.
1124 */
1125 if ((cp_coher_cntl ||
1126 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1127 RADV_CMD_FLAG_INV_VCACHE |
1128 RADV_CMD_FLAG_INV_L2 |
1129 RADV_CMD_FLAG_WB_L2))) &&
1130 !is_mec) {
1131 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1132 radeon_emit(cs, 0);
1133 }
1134
1135 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1136 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1137 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
1138 cp_coher_cntl |
1139 S_0085F0_TC_ACTION_ENA(1) |
1140 S_0085F0_TCL1_ACTION_ENA(1) |
1141 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1142 cp_coher_cntl = 0;
1143 } else {
1144 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1145 /* WB = write-back
1146 * NC = apply to non-coherent MTYPEs
1147 * (i.e. MTYPE <= 1, which is what we use everywhere)
1148 *
1149 * WB doesn't work without NC.
1150 */
1151 si_emit_acquire_mem(cs, is_mec,
1152 chip_class >= GFX9,
1153 cp_coher_cntl |
1154 S_0301F0_TC_WB_ACTION_ENA(1) |
1155 S_0301F0_TC_NC_ACTION_ENA(1));
1156 cp_coher_cntl = 0;
1157 }
1158 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1159 si_emit_acquire_mem(cs, is_mec,
1160 chip_class >= GFX9,
1161 cp_coher_cntl |
1162 S_0085F0_TCL1_ACTION_ENA(1));
1163 cp_coher_cntl = 0;
1164 }
1165 }
1166
1167 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1168 * Therefore, it should be last. Done in PFP.
1169 */
1170 if (cp_coher_cntl)
1171 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
1172
1173 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1174 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1175 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1176 EVENT_INDEX(0));
1177 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1178 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1179 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1180 EVENT_INDEX(0));
1181 }
1182 }
1183
1184 void
1185 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1186 {
1187 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1188
1189 if (is_compute)
1190 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1191 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1192 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1193 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1194 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1195 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1196 RADV_CMD_FLAG_VGT_FLUSH |
1197 RADV_CMD_FLAG_START_PIPELINE_STATS |
1198 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1199
1200 if (!cmd_buffer->state.flush_bits)
1201 return;
1202
1203 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1204
1205 si_cs_emit_cache_flush(cmd_buffer->cs,
1206 cmd_buffer->device->physical_device->rad_info.chip_class,
1207 &cmd_buffer->gfx9_fence_idx,
1208 cmd_buffer->gfx9_fence_va,
1209 radv_cmd_buffer_uses_mec(cmd_buffer),
1210 cmd_buffer->state.flush_bits,
1211 cmd_buffer->gfx9_eop_bug_va);
1212
1213
1214 if (unlikely(cmd_buffer->device->trace_bo))
1215 radv_cmd_buffer_trace_emit(cmd_buffer);
1216
1217 /* Clear the caches that have been flushed to avoid syncing too much
1218 * when there is some pending active queries.
1219 */
1220 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1221
1222 cmd_buffer->state.flush_bits = 0;
1223
1224 /* If the driver used a compute shader for resetting a query pool, it
1225 * should be finished at this point.
1226 */
1227 cmd_buffer->pending_reset_query = false;
1228 }
1229
1230 /* sets the CP predication state using a boolean stored at va */
1231 void
1232 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1233 bool draw_visible, uint64_t va)
1234 {
1235 uint32_t op = 0;
1236
1237 if (va) {
1238 op = PRED_OP(PREDICATION_OP_BOOL64);
1239
1240 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1241 * zero, all rendering commands are discarded. Otherwise, they
1242 * are discarded if the value is non zero.
1243 */
1244 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1245 PREDICATION_DRAW_NOT_VISIBLE;
1246 }
1247 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1248 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1249 radeon_emit(cmd_buffer->cs, op);
1250 radeon_emit(cmd_buffer->cs, va);
1251 radeon_emit(cmd_buffer->cs, va >> 32);
1252 } else {
1253 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1254 radeon_emit(cmd_buffer->cs, va);
1255 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1256 }
1257 }
1258
1259 /* Set this if you want the 3D engine to wait until CP DMA is done.
1260 * It should be set on the last CP DMA packet. */
1261 #define CP_DMA_SYNC (1 << 0)
1262
1263 /* Set this if the source data was used as a destination in a previous CP DMA
1264 * packet. It's for preventing a read-after-write (RAW) hazard between two
1265 * CP DMA packets. */
1266 #define CP_DMA_RAW_WAIT (1 << 1)
1267 #define CP_DMA_USE_L2 (1 << 2)
1268 #define CP_DMA_CLEAR (1 << 3)
1269
1270 /* Alignment for optimal performance. */
1271 #define SI_CPDMA_ALIGNMENT 32
1272
1273 /* The max number of bytes that can be copied per packet. */
1274 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1275 {
1276 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1277 S_414_BYTE_COUNT_GFX9(~0u) :
1278 S_414_BYTE_COUNT_GFX6(~0u);
1279
1280 /* make it aligned for optimal performance */
1281 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1282 }
1283
1284 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1285 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1286 * clear value.
1287 */
1288 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1289 uint64_t dst_va, uint64_t src_va,
1290 unsigned size, unsigned flags)
1291 {
1292 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1293 uint32_t header = 0, command = 0;
1294
1295 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1296
1297 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1298 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1299 command |= S_414_BYTE_COUNT_GFX9(size);
1300 else
1301 command |= S_414_BYTE_COUNT_GFX6(size);
1302
1303 /* Sync flags. */
1304 if (flags & CP_DMA_SYNC)
1305 header |= S_411_CP_SYNC(1);
1306 else {
1307 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1308 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1309 else
1310 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1311 }
1312
1313 if (flags & CP_DMA_RAW_WAIT)
1314 command |= S_414_RAW_WAIT(1);
1315
1316 /* Src and dst flags. */
1317 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1318 !(flags & CP_DMA_CLEAR) &&
1319 src_va == dst_va)
1320 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1321 else if (flags & CP_DMA_USE_L2)
1322 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1323
1324 if (flags & CP_DMA_CLEAR)
1325 header |= S_411_SRC_SEL(V_411_DATA);
1326 else if (flags & CP_DMA_USE_L2)
1327 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1328
1329 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1330 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1331 radeon_emit(cs, header);
1332 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1333 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1334 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1335 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1336 radeon_emit(cs, command);
1337 } else {
1338 assert(!(flags & CP_DMA_USE_L2));
1339 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1340 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1341 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1342 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1343 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1344 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1345 radeon_emit(cs, command);
1346 }
1347
1348 /* CP DMA is executed in ME, but index buffers are read by PFP.
1349 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1350 * indices. If we wanted to execute CP DMA in PFP, this packet
1351 * should precede it.
1352 */
1353 if (flags & CP_DMA_SYNC) {
1354 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1355 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1356 radeon_emit(cs, 0);
1357 }
1358
1359 /* CP will see the sync flag and wait for all DMAs to complete. */
1360 cmd_buffer->state.dma_is_busy = false;
1361 }
1362
1363 if (unlikely(cmd_buffer->device->trace_bo))
1364 radv_cmd_buffer_trace_emit(cmd_buffer);
1365 }
1366
1367 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1368 unsigned size)
1369 {
1370 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1371 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1372
1373 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1374 aligned_size, CP_DMA_USE_L2);
1375 }
1376
1377 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1378 uint64_t remaining_size, unsigned *flags)
1379 {
1380
1381 /* Flush the caches for the first copy only.
1382 * Also wait for the previous CP DMA operations.
1383 */
1384 if (cmd_buffer->state.flush_bits) {
1385 si_emit_cache_flush(cmd_buffer);
1386 *flags |= CP_DMA_RAW_WAIT;
1387 }
1388
1389 /* Do the synchronization after the last dma, so that all data
1390 * is written to memory.
1391 */
1392 if (byte_count == remaining_size)
1393 *flags |= CP_DMA_SYNC;
1394 }
1395
1396 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1397 {
1398 uint64_t va;
1399 uint32_t offset;
1400 unsigned dma_flags = 0;
1401 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1402 void *ptr;
1403
1404 assert(size < SI_CPDMA_ALIGNMENT);
1405
1406 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1407
1408 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1409 va += offset;
1410
1411 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1412
1413 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1414 dma_flags);
1415 }
1416
1417 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1418 uint64_t src_va, uint64_t dest_va,
1419 uint64_t size)
1420 {
1421 uint64_t main_src_va, main_dest_va;
1422 uint64_t skipped_size = 0, realign_size = 0;
1423
1424 /* Assume that we are not going to sync after the last DMA operation. */
1425 cmd_buffer->state.dma_is_busy = true;
1426
1427 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1428 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1429 /* If the size is not aligned, we must add a dummy copy at the end
1430 * just to align the internal counter. Otherwise, the DMA engine
1431 * would slow down by an order of magnitude for following copies.
1432 */
1433 if (size % SI_CPDMA_ALIGNMENT)
1434 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1435
1436 /* If the copy begins unaligned, we must start copying from the next
1437 * aligned block and the skipped part should be copied after everything
1438 * else has been copied. Only the src alignment matters, not dst.
1439 */
1440 if (src_va % SI_CPDMA_ALIGNMENT) {
1441 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1442 /* The main part will be skipped if the size is too small. */
1443 skipped_size = MIN2(skipped_size, size);
1444 size -= skipped_size;
1445 }
1446 }
1447 main_src_va = src_va + skipped_size;
1448 main_dest_va = dest_va + skipped_size;
1449
1450 while (size) {
1451 unsigned dma_flags = 0;
1452 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1453
1454 si_cp_dma_prepare(cmd_buffer, byte_count,
1455 size + skipped_size + realign_size,
1456 &dma_flags);
1457
1458 dma_flags &= ~CP_DMA_SYNC;
1459
1460 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1461 byte_count, dma_flags);
1462
1463 size -= byte_count;
1464 main_src_va += byte_count;
1465 main_dest_va += byte_count;
1466 }
1467
1468 if (skipped_size) {
1469 unsigned dma_flags = 0;
1470
1471 si_cp_dma_prepare(cmd_buffer, skipped_size,
1472 size + skipped_size + realign_size,
1473 &dma_flags);
1474
1475 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1476 skipped_size, dma_flags);
1477 }
1478 if (realign_size)
1479 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1480 }
1481
1482 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1483 uint64_t size, unsigned value)
1484 {
1485
1486 if (!size)
1487 return;
1488
1489 assert(va % 4 == 0 && size % 4 == 0);
1490
1491 /* Assume that we are not going to sync after the last DMA operation. */
1492 cmd_buffer->state.dma_is_busy = true;
1493
1494 while (size) {
1495 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1496 unsigned dma_flags = CP_DMA_CLEAR;
1497
1498 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1499
1500 /* Emit the clear packet. */
1501 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1502 dma_flags);
1503
1504 size -= byte_count;
1505 va += byte_count;
1506 }
1507 }
1508
1509 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1510 {
1511 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1512 return;
1513
1514 if (!cmd_buffer->state.dma_is_busy)
1515 return;
1516
1517 /* Issue a dummy DMA that copies zero bytes.
1518 *
1519 * The DMA engine will see that there's no work to do and skip this
1520 * DMA request, however, the CP will see the sync flag and still wait
1521 * for all DMAs to complete.
1522 */
1523 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1524
1525 cmd_buffer->state.dma_is_busy = false;
1526 }
1527
1528 /* For MSAA sample positions. */
1529 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1530 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1531 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1532 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1533 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1534
1535 /* For obtaining location coordinates from registers */
1536 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1537 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1538 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1539 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1540
1541 /* 1x MSAA */
1542 static const uint32_t sample_locs_1x =
1543 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1544 static const unsigned max_dist_1x = 0;
1545 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1546
1547 /* 2xMSAA */
1548 static const uint32_t sample_locs_2x =
1549 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1550 static const unsigned max_dist_2x = 4;
1551 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1552
1553 /* 4xMSAA */
1554 static const uint32_t sample_locs_4x =
1555 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1556 static const unsigned max_dist_4x = 6;
1557 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1558
1559 /* 8xMSAA */
1560 static const uint32_t sample_locs_8x[] = {
1561 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1562 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1563 /* The following are unused by hardware, but we emit them to IBs
1564 * instead of multiple SET_CONTEXT_REG packets. */
1565 0,
1566 0,
1567 };
1568 static const unsigned max_dist_8x = 7;
1569 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1570
1571 unsigned radv_get_default_max_sample_dist(int log_samples)
1572 {
1573 unsigned max_dist[] = {
1574 max_dist_1x,
1575 max_dist_2x,
1576 max_dist_4x,
1577 max_dist_8x,
1578 };
1579 return max_dist[log_samples];
1580 }
1581
1582 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1583 {
1584 switch (nr_samples) {
1585 default:
1586 case 1:
1587 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1588 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1589 radeon_emit(cs, centroid_priority_1x >> 32);
1590 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1591 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1592 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1593 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1594 break;
1595 case 2:
1596 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1597 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1598 radeon_emit(cs, centroid_priority_2x >> 32);
1599 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1600 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1601 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1602 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1603 break;
1604 case 4:
1605 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1606 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1607 radeon_emit(cs, centroid_priority_4x >> 32);
1608 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1609 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1610 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1611 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1612 break;
1613 case 8:
1614 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1615 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1616 radeon_emit(cs, centroid_priority_8x >> 32);
1617 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1618 radeon_emit_array(cs, sample_locs_8x, 4);
1619 radeon_emit_array(cs, sample_locs_8x, 4);
1620 radeon_emit_array(cs, sample_locs_8x, 4);
1621 radeon_emit_array(cs, sample_locs_8x, 2);
1622 break;
1623 }
1624 }
1625
1626 static void radv_get_sample_position(struct radv_device *device,
1627 unsigned sample_count,
1628 unsigned sample_index, float *out_value)
1629 {
1630 const uint32_t *sample_locs;
1631
1632 switch (sample_count) {
1633 case 1:
1634 default:
1635 sample_locs = &sample_locs_1x;
1636 break;
1637 case 2:
1638 sample_locs = &sample_locs_2x;
1639 break;
1640 case 4:
1641 sample_locs = &sample_locs_4x;
1642 break;
1643 case 8:
1644 sample_locs = sample_locs_8x;
1645 break;
1646 }
1647
1648 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1649 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1650 }
1651
1652 void radv_device_init_msaa(struct radv_device *device)
1653 {
1654 int i;
1655
1656 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1657
1658 for (i = 0; i < 2; i++)
1659 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1660 for (i = 0; i < 4; i++)
1661 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1662 for (i = 0; i < 8; i++)
1663 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1664 }