2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based on amdgpu winsys.
6 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
7 * Copyright © 2015 Advanced Micro Devices, Inc.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "radv_amdgpu_bo.h"
34 #include <amdgpu_drm.h>
39 #include "util/u_atomic.h"
41 static void radv_amdgpu_winsys_bo_destroy(struct radeon_winsys_bo
*_bo
);
44 radv_amdgpu_bo_va_op(struct radv_amdgpu_winsys
*ws
,
52 uint64_t flags
= AMDGPU_VM_PAGE_READABLE
|
53 AMDGPU_VM_PAGE_EXECUTABLE
;
55 if ((bo_flags
& RADEON_FLAG_VA_UNCACHED
) && ws
->info
.chip_class
>= GFX9
)
56 flags
|= AMDGPU_VM_MTYPE_UC
;
58 if (!(bo_flags
& RADEON_FLAG_READ_ONLY
))
59 flags
|= AMDGPU_VM_PAGE_WRITEABLE
;
61 size
= ALIGN(size
, getpagesize());
63 return amdgpu_bo_va_op_raw(ws
->dev
, bo
, offset
, size
, addr
,
68 radv_amdgpu_winsys_virtual_map(struct radv_amdgpu_winsys_bo
*bo
,
69 const struct radv_amdgpu_map_range
*range
)
74 return; /* TODO: PRT mapping */
76 p_atomic_inc(&range
->bo
->ref_count
);
77 int r
= radv_amdgpu_bo_va_op(bo
->ws
, range
->bo
->bo
, range
->bo_offset
,
78 range
->size
, range
->offset
+ bo
->base
.va
,
85 radv_amdgpu_winsys_virtual_unmap(struct radv_amdgpu_winsys_bo
*bo
,
86 const struct radv_amdgpu_map_range
*range
)
91 return; /* TODO: PRT mapping */
93 int r
= radv_amdgpu_bo_va_op(bo
->ws
, range
->bo
->bo
, range
->bo_offset
,
94 range
->size
, range
->offset
+ bo
->base
.va
,
95 0, AMDGPU_VA_OP_UNMAP
);
98 radv_amdgpu_winsys_bo_destroy((struct radeon_winsys_bo
*)range
->bo
);
101 static int bo_comparator(const void *ap
, const void *bp
) {
102 struct radv_amdgpu_bo
*a
= *(struct radv_amdgpu_bo
*const *)ap
;
103 struct radv_amdgpu_bo
*b
= *(struct radv_amdgpu_bo
*const *)bp
;
104 return (a
> b
) ? 1 : (a
< b
) ? -1 : 0;
108 radv_amdgpu_winsys_rebuild_bo_list(struct radv_amdgpu_winsys_bo
*bo
)
110 if (bo
->bo_capacity
< bo
->range_count
) {
111 uint32_t new_count
= MAX2(bo
->bo_capacity
* 2, bo
->range_count
);
112 bo
->bos
= realloc(bo
->bos
, new_count
* sizeof(struct radv_amdgpu_winsys_bo
*));
113 bo
->bo_capacity
= new_count
;
116 uint32_t temp_bo_count
= 0;
117 for (uint32_t i
= 0; i
< bo
->range_count
; ++i
)
118 if (bo
->ranges
[i
].bo
)
119 bo
->bos
[temp_bo_count
++] = bo
->ranges
[i
].bo
;
121 qsort(bo
->bos
, temp_bo_count
, sizeof(struct radv_amdgpu_winsys_bo
*), &bo_comparator
);
123 uint32_t final_bo_count
= 1;
124 for (uint32_t i
= 1; i
< temp_bo_count
; ++i
)
125 if (bo
->bos
[i
] != bo
->bos
[i
- 1])
126 bo
->bos
[final_bo_count
++] = bo
->bos
[i
];
128 bo
->bo_count
= final_bo_count
;
132 radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys_bo
*_parent
,
133 uint64_t offset
, uint64_t size
,
134 struct radeon_winsys_bo
*_bo
, uint64_t bo_offset
)
136 struct radv_amdgpu_winsys_bo
*parent
= (struct radv_amdgpu_winsys_bo
*)_parent
;
137 struct radv_amdgpu_winsys_bo
*bo
= (struct radv_amdgpu_winsys_bo
*)_bo
;
138 int range_count_delta
, new_idx
;
140 struct radv_amdgpu_map_range new_first
, new_last
;
142 assert(parent
->is_virtual
);
143 assert(!bo
|| !bo
->is_virtual
);
148 /* We have at most 2 new ranges (1 by the bind, and another one by splitting a range that contains the newly bound range). */
149 if (parent
->range_capacity
- parent
->range_count
< 2) {
150 parent
->range_capacity
+= 2;
151 parent
->ranges
= realloc(parent
->ranges
,
152 parent
->range_capacity
* sizeof(struct radv_amdgpu_map_range
));
156 * [first, last] is exactly the range of ranges that either overlap the
157 * new parent, or are adjacent to it. This corresponds to the bind ranges
160 while(first
+ 1 < parent
->range_count
&& parent
->ranges
[first
].offset
+ parent
->ranges
[first
].size
< offset
)
164 while(last
+ 1 < parent
->range_count
&& parent
->ranges
[last
].offset
<= offset
+ size
)
167 /* Whether the first or last range are going to be totally removed or just
168 * resized/left alone. Note that in the case of first == last, we will split
169 * this into a part before and after the new range. The remove flag is then
170 * whether to not create the corresponding split part. */
171 bool remove_first
= parent
->ranges
[first
].offset
== offset
;
172 bool remove_last
= parent
->ranges
[last
].offset
+ parent
->ranges
[last
].size
== offset
+ size
;
173 bool unmapped_first
= false;
175 assert(parent
->ranges
[first
].offset
<= offset
);
176 assert(parent
->ranges
[last
].offset
+ parent
->ranges
[last
].size
>= offset
+ size
);
178 /* Try to merge the new range with the first range. */
179 if (parent
->ranges
[first
].bo
== bo
&& (!bo
|| offset
- bo_offset
== parent
->ranges
[first
].offset
- parent
->ranges
[first
].bo_offset
)) {
180 size
+= offset
- parent
->ranges
[first
].offset
;
181 offset
= parent
->ranges
[first
].offset
;
182 bo_offset
= parent
->ranges
[first
].bo_offset
;
186 /* Try to merge the new range with the last range. */
187 if (parent
->ranges
[last
].bo
== bo
&& (!bo
|| offset
- bo_offset
== parent
->ranges
[last
].offset
- parent
->ranges
[last
].bo_offset
)) {
188 size
= parent
->ranges
[last
].offset
+ parent
->ranges
[last
].size
- offset
;
192 range_count_delta
= 1 - (last
- first
+ 1) + !remove_first
+ !remove_last
;
193 new_idx
= first
+ !remove_first
;
195 /* Any range between first and last is going to be entirely covered by the new range so just unmap them. */
196 for (int i
= first
+ 1; i
< last
; ++i
)
197 radv_amdgpu_winsys_virtual_unmap(parent
, parent
->ranges
+ i
);
199 /* If the first/last range are not left alone we unmap then and optionally map
200 * them again after modifications. Not that this implicitly can do the splitting
201 * if first == last. */
202 new_first
= parent
->ranges
[first
];
203 new_last
= parent
->ranges
[last
];
205 if (parent
->ranges
[first
].offset
+ parent
->ranges
[first
].size
> offset
|| remove_first
) {
206 radv_amdgpu_winsys_virtual_unmap(parent
, parent
->ranges
+ first
);
207 unmapped_first
= true;
210 new_first
.size
= offset
- new_first
.offset
;
211 radv_amdgpu_winsys_virtual_map(parent
, &new_first
);
215 if (parent
->ranges
[last
].offset
< offset
+ size
|| remove_last
) {
216 if (first
!= last
|| !unmapped_first
)
217 radv_amdgpu_winsys_virtual_unmap(parent
, parent
->ranges
+ last
);
220 new_last
.size
-= offset
+ size
- new_last
.offset
;
221 new_last
.offset
= offset
+ size
;
222 radv_amdgpu_winsys_virtual_map(parent
, &new_last
);
226 /* Moves the range list after last to account for the changed number of ranges. */
227 memmove(parent
->ranges
+ last
+ 1 + range_count_delta
, parent
->ranges
+ last
+ 1,
228 sizeof(struct radv_amdgpu_map_range
) * (parent
->range_count
- last
- 1));
231 parent
->ranges
[first
] = new_first
;
234 parent
->ranges
[new_idx
+ 1] = new_last
;
236 /* Actually set up the new range. */
237 parent
->ranges
[new_idx
].offset
= offset
;
238 parent
->ranges
[new_idx
].size
= size
;
239 parent
->ranges
[new_idx
].bo
= bo
;
240 parent
->ranges
[new_idx
].bo_offset
= bo_offset
;
242 radv_amdgpu_winsys_virtual_map(parent
, parent
->ranges
+ new_idx
);
244 parent
->range_count
+= range_count_delta
;
246 radv_amdgpu_winsys_rebuild_bo_list(parent
);
249 static void radv_amdgpu_winsys_bo_destroy(struct radeon_winsys_bo
*_bo
)
251 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
252 struct radv_amdgpu_winsys
*ws
= bo
->ws
;
254 if (p_atomic_dec_return(&bo
->ref_count
))
256 if (bo
->is_virtual
) {
257 for (uint32_t i
= 0; i
< bo
->range_count
; ++i
) {
258 radv_amdgpu_winsys_virtual_unmap(bo
, bo
->ranges
+ i
);
263 if (bo
->ws
->debug_all_bos
) {
264 pthread_mutex_lock(&bo
->ws
->global_bo_list_lock
);
265 LIST_DEL(&bo
->global_list_item
);
266 bo
->ws
->num_buffers
--;
267 pthread_mutex_unlock(&bo
->ws
->global_bo_list_lock
);
269 radv_amdgpu_bo_va_op(bo
->ws
, bo
->bo
, 0, bo
->size
, bo
->base
.va
,
270 0, AMDGPU_VA_OP_UNMAP
);
271 amdgpu_bo_free(bo
->bo
);
274 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
275 p_atomic_add(&ws
->allocated_vram
,
276 -align64(bo
->size
, ws
->info
.gart_page_size
));
277 if (bo
->base
.vram_cpu_access
)
278 p_atomic_add(&ws
->allocated_vram_vis
,
279 -align64(bo
->size
, ws
->info
.gart_page_size
));
280 if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
281 p_atomic_add(&ws
->allocated_gtt
,
282 -align64(bo
->size
, ws
->info
.gart_page_size
));
284 amdgpu_va_range_free(bo
->va_handle
);
288 static void radv_amdgpu_add_buffer_to_global_list(struct radv_amdgpu_winsys_bo
*bo
)
290 struct radv_amdgpu_winsys
*ws
= bo
->ws
;
292 if (bo
->ws
->debug_all_bos
) {
293 pthread_mutex_lock(&ws
->global_bo_list_lock
);
294 list_addtail(&bo
->global_list_item
, &ws
->global_bo_list
);
296 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
300 static struct radeon_winsys_bo
*
301 radv_amdgpu_winsys_bo_create(struct radeon_winsys
*_ws
,
304 enum radeon_bo_domain initial_domain
,
308 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
309 struct radv_amdgpu_winsys_bo
*bo
;
310 struct amdgpu_bo_alloc_request request
= {0};
311 amdgpu_bo_handle buf_handle
;
313 amdgpu_va_handle va_handle
;
315 bo
= CALLOC_STRUCT(radv_amdgpu_winsys_bo
);
320 unsigned virt_alignment
= alignment
;
321 if (size
>= ws
->info
.pte_fragment_size
)
322 virt_alignment
= MAX2(virt_alignment
, ws
->info
.pte_fragment_size
);
324 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
325 size
, virt_alignment
, 0, &va
, &va_handle
,
326 (flags
& RADEON_FLAG_32BIT
? AMDGPU_VA_RANGE_32_BIT
: 0) |
327 AMDGPU_VA_RANGE_HIGH
);
332 bo
->va_handle
= va_handle
;
335 bo
->is_virtual
= !!(flags
& RADEON_FLAG_VIRTUAL
);
338 if (flags
& RADEON_FLAG_VIRTUAL
) {
339 bo
->ranges
= realloc(NULL
, sizeof(struct radv_amdgpu_map_range
));
341 bo
->range_capacity
= 1;
343 bo
->ranges
[0].offset
= 0;
344 bo
->ranges
[0].size
= size
;
345 bo
->ranges
[0].bo
= NULL
;
346 bo
->ranges
[0].bo_offset
= 0;
348 radv_amdgpu_winsys_virtual_map(bo
, bo
->ranges
);
349 return (struct radeon_winsys_bo
*)bo
;
352 request
.alloc_size
= size
;
353 request
.phys_alignment
= alignment
;
355 if (initial_domain
& RADEON_DOMAIN_VRAM
)
356 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
357 if (initial_domain
& RADEON_DOMAIN_GTT
)
358 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
359 if (initial_domain
& RADEON_DOMAIN_GDS
)
360 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GDS
;
361 if (initial_domain
& RADEON_DOMAIN_OA
)
362 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_OA
;
364 if (flags
& RADEON_FLAG_CPU_ACCESS
) {
365 bo
->base
.vram_cpu_access
= initial_domain
& RADEON_DOMAIN_VRAM
;
366 request
.flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
368 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
369 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
370 if (flags
& RADEON_FLAG_GTT_WC
)
371 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
372 if (!(flags
& RADEON_FLAG_IMPLICIT_SYNC
) && ws
->info
.drm_minor
>= 22)
373 request
.flags
|= AMDGPU_GEM_CREATE_EXPLICIT_SYNC
;
374 if (flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
375 ws
->info
.has_local_buffers
&&
376 (ws
->use_local_bos
|| (flags
& RADEON_FLAG_PREFER_LOCAL_BO
))) {
377 bo
->base
.is_local
= true;
378 request
.flags
|= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
;
381 /* this won't do anything on pre 4.9 kernels */
382 if (ws
->zero_all_vram_allocs
&& (initial_domain
& RADEON_DOMAIN_VRAM
))
383 request
.flags
|= AMDGPU_GEM_CREATE_VRAM_CLEARED
;
384 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
386 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
387 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
388 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
389 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
393 r
= radv_amdgpu_bo_va_op(ws
, buf_handle
, 0, size
, va
, flags
,
399 bo
->initial_domain
= initial_domain
;
400 bo
->is_shared
= false;
401 bo
->priority
= priority
;
403 r
= amdgpu_bo_export(buf_handle
, amdgpu_bo_handle_type_kms
, &bo
->bo_handle
);
406 if (initial_domain
& RADEON_DOMAIN_VRAM
)
407 p_atomic_add(&ws
->allocated_vram
,
408 align64(bo
->size
, ws
->info
.gart_page_size
));
409 if (bo
->base
.vram_cpu_access
)
410 p_atomic_add(&ws
->allocated_vram_vis
,
411 align64(bo
->size
, ws
->info
.gart_page_size
));
412 if (initial_domain
& RADEON_DOMAIN_GTT
)
413 p_atomic_add(&ws
->allocated_gtt
,
414 align64(bo
->size
, ws
->info
.gart_page_size
));
416 radv_amdgpu_add_buffer_to_global_list(bo
);
417 return (struct radeon_winsys_bo
*)bo
;
419 amdgpu_bo_free(buf_handle
);
422 amdgpu_va_range_free(va_handle
);
430 radv_amdgpu_winsys_bo_map(struct radeon_winsys_bo
*_bo
)
432 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
435 ret
= amdgpu_bo_cpu_map(bo
->bo
, &data
);
442 radv_amdgpu_winsys_bo_unmap(struct radeon_winsys_bo
*_bo
)
444 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
445 amdgpu_bo_cpu_unmap(bo
->bo
);
449 radv_amdgpu_get_optimal_vm_alignment(struct radv_amdgpu_winsys
*ws
,
450 uint64_t size
, unsigned alignment
)
452 uint64_t vm_alignment
= alignment
;
454 /* Increase the VM alignment for faster address translation. */
455 if (size
>= ws
->info
.pte_fragment_size
)
456 vm_alignment
= MAX2(vm_alignment
, ws
->info
.pte_fragment_size
);
458 /* Gfx9: Increase the VM alignment to the most significant bit set
459 * in the size for faster address translation.
461 if (ws
->info
.chip_class
>= GFX9
) {
462 unsigned msb
= util_last_bit64(size
); /* 0 = no bit is set */
463 uint64_t msb_alignment
= msb
? 1ull << (msb
- 1) : 0;
465 vm_alignment
= MAX2(vm_alignment
, msb_alignment
);
470 static struct radeon_winsys_bo
*
471 radv_amdgpu_winsys_bo_from_ptr(struct radeon_winsys
*_ws
,
476 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
477 amdgpu_bo_handle buf_handle
;
478 struct radv_amdgpu_winsys_bo
*bo
;
480 amdgpu_va_handle va_handle
;
481 uint64_t vm_alignment
;
483 bo
= CALLOC_STRUCT(radv_amdgpu_winsys_bo
);
487 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
, size
, &buf_handle
))
490 /* Using the optimal VM alignment also fixes GPU hangs for buffers that
493 vm_alignment
= radv_amdgpu_get_optimal_vm_alignment(ws
, size
,
494 ws
->info
.gart_page_size
);
496 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
497 size
, vm_alignment
, 0, &va
, &va_handle
,
498 AMDGPU_VA_RANGE_HIGH
))
501 if (amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
))
506 bo
->va_handle
= va_handle
;
511 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
512 bo
->priority
= priority
;
514 ASSERTED
int r
= amdgpu_bo_export(buf_handle
, amdgpu_bo_handle_type_kms
, &bo
->bo_handle
);
517 p_atomic_add(&ws
->allocated_gtt
,
518 align64(bo
->size
, ws
->info
.gart_page_size
));
520 radv_amdgpu_add_buffer_to_global_list(bo
);
521 return (struct radeon_winsys_bo
*)bo
;
524 amdgpu_va_range_free(va_handle
);
527 amdgpu_bo_free(buf_handle
);
534 static struct radeon_winsys_bo
*
535 radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys
*_ws
,
536 int fd
, unsigned priority
,
537 uint64_t *alloc_size
)
539 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
540 struct radv_amdgpu_winsys_bo
*bo
;
542 amdgpu_va_handle va_handle
;
543 enum amdgpu_bo_handle_type type
= amdgpu_bo_handle_type_dma_buf_fd
;
544 struct amdgpu_bo_import_result result
= {0};
545 struct amdgpu_bo_info info
= {0};
546 enum radeon_bo_domain initial
= 0;
548 bo
= CALLOC_STRUCT(radv_amdgpu_winsys_bo
);
552 r
= amdgpu_bo_import(ws
->dev
, type
, fd
, &result
);
556 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
561 *alloc_size
= info
.alloc_size
;
564 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
565 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
,
566 AMDGPU_VA_RANGE_HIGH
);
570 r
= radv_amdgpu_bo_va_op(ws
, result
.buf_handle
, 0, result
.alloc_size
,
571 va
, 0, AMDGPU_VA_OP_MAP
);
575 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
576 initial
|= RADEON_DOMAIN_VRAM
;
577 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
578 initial
|= RADEON_DOMAIN_GTT
;
580 bo
->bo
= result
.buf_handle
;
582 bo
->va_handle
= va_handle
;
583 bo
->initial_domain
= initial
;
584 bo
->size
= result
.alloc_size
;
585 bo
->is_shared
= true;
587 bo
->priority
= priority
;
590 r
= amdgpu_bo_export(result
.buf_handle
, amdgpu_bo_handle_type_kms
, &bo
->bo_handle
);
593 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
594 p_atomic_add(&ws
->allocated_vram
,
595 align64(bo
->size
, ws
->info
.gart_page_size
));
596 if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
597 p_atomic_add(&ws
->allocated_gtt
,
598 align64(bo
->size
, ws
->info
.gart_page_size
));
600 radv_amdgpu_add_buffer_to_global_list(bo
);
601 return (struct radeon_winsys_bo
*)bo
;
603 amdgpu_va_range_free(va_handle
);
606 amdgpu_bo_free(result
.buf_handle
);
614 radv_amdgpu_winsys_get_fd(struct radeon_winsys
*_ws
,
615 struct radeon_winsys_bo
*_bo
,
618 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
619 enum amdgpu_bo_handle_type type
= amdgpu_bo_handle_type_dma_buf_fd
;
622 r
= amdgpu_bo_export(bo
->bo
, type
, &handle
);
627 bo
->is_shared
= true;
631 static unsigned eg_tile_split(unsigned tile_split
)
633 switch (tile_split
) {
634 case 0: tile_split
= 64; break;
635 case 1: tile_split
= 128; break;
636 case 2: tile_split
= 256; break;
637 case 3: tile_split
= 512; break;
639 case 4: tile_split
= 1024; break;
640 case 5: tile_split
= 2048; break;
641 case 6: tile_split
= 4096; break;
646 static unsigned radv_eg_tile_split_rev(unsigned eg_tile_split
)
648 switch (eg_tile_split
) {
661 radv_amdgpu_winsys_bo_set_metadata(struct radeon_winsys_bo
*_bo
,
662 struct radeon_bo_metadata
*md
)
664 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
665 struct amdgpu_bo_metadata metadata
= {0};
666 uint32_t tiling_flags
= 0;
668 if (bo
->ws
->info
.chip_class
>= GFX9
) {
669 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
671 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
672 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
673 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
674 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
676 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
678 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
679 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
680 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
681 if (md
->u
.legacy
.tile_split
)
682 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, radv_eg_tile_split_rev(md
->u
.legacy
.tile_split
));
683 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
684 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
686 if (md
->u
.legacy
.scanout
)
687 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
689 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
692 metadata
.tiling_info
= tiling_flags
;
693 metadata
.size_metadata
= md
->size_metadata
;
694 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
696 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
700 radv_amdgpu_winsys_bo_get_metadata(struct radeon_winsys_bo
*_bo
,
701 struct radeon_bo_metadata
*md
)
703 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
704 struct amdgpu_bo_info info
= {0};
706 int r
= amdgpu_bo_query_info(bo
->bo
, &info
);
710 uint64_t tiling_flags
= info
.metadata
.tiling_info
;
712 if (bo
->ws
->info
.chip_class
>= GFX9
) {
713 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
715 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
716 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
718 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
719 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
720 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
721 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
723 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
724 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
725 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
726 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
727 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
728 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
729 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
732 md
->size_metadata
= info
.metadata
.size_metadata
;
733 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
736 void radv_amdgpu_bo_init_functions(struct radv_amdgpu_winsys
*ws
)
738 ws
->base
.buffer_create
= radv_amdgpu_winsys_bo_create
;
739 ws
->base
.buffer_destroy
= radv_amdgpu_winsys_bo_destroy
;
740 ws
->base
.buffer_map
= radv_amdgpu_winsys_bo_map
;
741 ws
->base
.buffer_unmap
= radv_amdgpu_winsys_bo_unmap
;
742 ws
->base
.buffer_from_ptr
= radv_amdgpu_winsys_bo_from_ptr
;
743 ws
->base
.buffer_from_fd
= radv_amdgpu_winsys_bo_from_fd
;
744 ws
->base
.buffer_get_fd
= radv_amdgpu_winsys_get_fd
;
745 ws
->base
.buffer_set_metadata
= radv_amdgpu_winsys_bo_set_metadata
;
746 ws
->base
.buffer_get_metadata
= radv_amdgpu_winsys_bo_get_metadata
;
747 ws
->base
.buffer_virtual_bind
= radv_amdgpu_winsys_bo_virtual_bind
;