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[mesa.git] / src / amd / vulkan / winsys / amdgpu / radv_amdgpu_cs.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdlib.h>
26 #include <amdgpu.h>
27 #include "drm-uapi/amdgpu_drm.h"
28 #include <assert.h>
29 #include <pthread.h>
30 #include <errno.h>
31
32 #include "util/u_memory.h"
33 #include "ac_debug.h"
34 #include "radv_radeon_winsys.h"
35 #include "radv_amdgpu_cs.h"
36 #include "radv_amdgpu_bo.h"
37 #include "sid.h"
38
39
40 enum {
41 VIRTUAL_BUFFER_HASH_TABLE_SIZE = 1024
42 };
43
44 struct radv_amdgpu_cs {
45 struct radeon_cmdbuf base;
46 struct radv_amdgpu_winsys *ws;
47
48 struct amdgpu_cs_ib_info ib;
49
50 struct radeon_winsys_bo *ib_buffer;
51 uint8_t *ib_mapped;
52 unsigned max_num_buffers;
53 unsigned num_buffers;
54 struct drm_amdgpu_bo_list_entry *handles;
55
56 struct radeon_winsys_bo **old_ib_buffers;
57 unsigned num_old_ib_buffers;
58 unsigned max_num_old_ib_buffers;
59 unsigned *ib_size_ptr;
60 bool failed;
61 bool is_chained;
62
63 int buffer_hash_table[1024];
64 unsigned hw_ip;
65
66 unsigned num_virtual_buffers;
67 unsigned max_num_virtual_buffers;
68 struct radeon_winsys_bo **virtual_buffers;
69 int *virtual_buffer_hash_table;
70
71 /* For chips that don't support chaining. */
72 struct radeon_cmdbuf *old_cs_buffers;
73 unsigned num_old_cs_buffers;
74 };
75
76 static inline struct radv_amdgpu_cs *
77 radv_amdgpu_cs(struct radeon_cmdbuf *base)
78 {
79 return (struct radv_amdgpu_cs*)base;
80 }
81
82 static int ring_to_hw_ip(enum ring_type ring)
83 {
84 switch (ring) {
85 case RING_GFX:
86 return AMDGPU_HW_IP_GFX;
87 case RING_DMA:
88 return AMDGPU_HW_IP_DMA;
89 case RING_COMPUTE:
90 return AMDGPU_HW_IP_COMPUTE;
91 default:
92 unreachable("unsupported ring");
93 }
94 }
95
96 struct radv_amdgpu_cs_request {
97 /** Specify flags with additional information */
98 uint64_t flags;
99
100 /** Specify HW IP block type to which to send the IB. */
101 unsigned ip_type;
102
103 /** IP instance index if there are several IPs of the same type. */
104 unsigned ip_instance;
105
106 /**
107 * Specify ring index of the IP. We could have several rings
108 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
109 */
110 uint32_t ring;
111
112 /**
113 * List handle with resources used by this request. This is a raw
114 * bo list handle used by the kernel.
115 */
116 uint32_t resources;
117
118 /**
119 * Number of dependencies this Command submission needs to
120 * wait for before starting execution.
121 */
122 uint32_t number_of_dependencies;
123
124 /**
125 * Array of dependencies which need to be met before
126 * execution can start.
127 */
128 struct amdgpu_cs_fence *dependencies;
129
130 /** Number of IBs to submit in the field ibs. */
131 uint32_t number_of_ibs;
132
133 /**
134 * IBs to submit. Those IBs will be submit together as single entity
135 */
136 struct amdgpu_cs_ib_info *ibs;
137
138 /**
139 * The returned sequence number for the command submission
140 */
141 uint64_t seq_no;
142
143 /**
144 * The fence information
145 */
146 struct amdgpu_cs_fence_info fence_info;
147 };
148
149
150 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
151 uint32_t ip_type,
152 uint32_t ring,
153 struct radv_winsys_sem_info *sem_info);
154 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
155 struct radv_amdgpu_cs_request *request,
156 struct radv_winsys_sem_info *sem_info);
157
158 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx,
159 struct radv_amdgpu_fence *fence,
160 struct radv_amdgpu_cs_request *req)
161 {
162 fence->fence.context = ctx->ctx;
163 fence->fence.ip_type = req->ip_type;
164 fence->fence.ip_instance = req->ip_instance;
165 fence->fence.ring = req->ring;
166 fence->fence.fence = req->seq_no;
167 fence->user_ptr = (volatile uint64_t*)(ctx->fence_map + (req->ip_type * MAX_RINGS_PER_TYPE + req->ring) * sizeof(uint64_t));
168 }
169
170 static struct radeon_winsys_fence *radv_amdgpu_create_fence()
171 {
172 struct radv_amdgpu_fence *fence = calloc(1, sizeof(struct radv_amdgpu_fence));
173 fence->fence.fence = UINT64_MAX;
174 return (struct radeon_winsys_fence*)fence;
175 }
176
177 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence *_fence)
178 {
179 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
180 free(fence);
181 }
182
183 static void radv_amdgpu_reset_fence(struct radeon_winsys_fence *_fence)
184 {
185 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
186 fence->fence.fence = UINT64_MAX;
187 }
188
189 static void radv_amdgpu_signal_fence(struct radeon_winsys_fence *_fence)
190 {
191 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
192 fence->fence.fence = 0;
193 }
194
195 static bool radv_amdgpu_is_fence_waitable(struct radeon_winsys_fence *_fence)
196 {
197 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
198 return fence->fence.fence < UINT64_MAX;
199 }
200
201 static bool radv_amdgpu_fence_wait(struct radeon_winsys *_ws,
202 struct radeon_winsys_fence *_fence,
203 bool absolute,
204 uint64_t timeout)
205 {
206 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
207 unsigned flags = absolute ? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE : 0;
208 int r;
209 uint32_t expired = 0;
210
211 /* Special casing 0 and UINT64_MAX so that they work without user_ptr/fence.ctx */
212 if (fence->fence.fence == UINT64_MAX)
213 return false;
214
215 if (fence->fence.fence == 0)
216 return true;
217
218 if (fence->user_ptr) {
219 if (*fence->user_ptr >= fence->fence.fence)
220 return true;
221 if (!absolute && !timeout)
222 return false;
223 }
224
225 /* Now use the libdrm query. */
226 r = amdgpu_cs_query_fence_status(&fence->fence,
227 timeout,
228 flags,
229 &expired);
230
231 if (r) {
232 fprintf(stderr, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
233 return false;
234 }
235
236 if (expired)
237 return true;
238
239 return false;
240 }
241
242
243 static bool radv_amdgpu_fences_wait(struct radeon_winsys *_ws,
244 struct radeon_winsys_fence *const *_fences,
245 uint32_t fence_count,
246 bool wait_all,
247 uint64_t timeout)
248 {
249 struct amdgpu_cs_fence *fences = malloc(sizeof(struct amdgpu_cs_fence) * fence_count);
250 int r;
251 uint32_t expired = 0, first = 0;
252
253 if (!fences)
254 return false;
255
256 for (uint32_t i = 0; i < fence_count; ++i)
257 fences[i] = ((struct radv_amdgpu_fence *)_fences[i])->fence;
258
259 /* Now use the libdrm query. */
260 r = amdgpu_cs_wait_fences(fences, fence_count, wait_all,
261 timeout, &expired, &first);
262
263 free(fences);
264 if (r) {
265 fprintf(stderr, "amdgpu: amdgpu_cs_wait_fences failed.\n");
266 return false;
267 }
268
269 if (expired)
270 return true;
271
272 return false;
273 }
274
275 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
276 {
277 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs);
278
279 if (cs->ib_buffer)
280 cs->ws->base.buffer_destroy(cs->ib_buffer);
281 else
282 free(cs->base.buf);
283
284 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
285 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
286
287 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
288 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
289 free(rcs->buf);
290 }
291
292 free(cs->old_cs_buffers);
293 free(cs->old_ib_buffers);
294 free(cs->virtual_buffers);
295 free(cs->virtual_buffer_hash_table);
296 free(cs->handles);
297 free(cs);
298 }
299
300 static void radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
301 enum ring_type ring_type)
302 {
303 for (int i = 0; i < ARRAY_SIZE(cs->buffer_hash_table); ++i)
304 cs->buffer_hash_table[i] = -1;
305
306 cs->hw_ip = ring_to_hw_ip(ring_type);
307 }
308
309 static struct radeon_cmdbuf *
310 radv_amdgpu_cs_create(struct radeon_winsys *ws,
311 enum ring_type ring_type)
312 {
313 struct radv_amdgpu_cs *cs;
314 uint32_t ib_size = 20 * 1024 * 4;
315 cs = calloc(1, sizeof(struct radv_amdgpu_cs));
316 if (!cs)
317 return NULL;
318
319 cs->ws = radv_amdgpu_winsys(ws);
320 radv_amdgpu_init_cs(cs, ring_type);
321
322 if (cs->ws->use_ib_bos) {
323 cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
324 RADEON_DOMAIN_GTT,
325 RADEON_FLAG_CPU_ACCESS |
326 RADEON_FLAG_NO_INTERPROCESS_SHARING |
327 RADEON_FLAG_READ_ONLY,
328 RADV_BO_PRIORITY_CS);
329 if (!cs->ib_buffer) {
330 free(cs);
331 return NULL;
332 }
333
334 cs->ib_mapped = ws->buffer_map(cs->ib_buffer);
335 if (!cs->ib_mapped) {
336 ws->buffer_destroy(cs->ib_buffer);
337 free(cs);
338 return NULL;
339 }
340
341 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
342 cs->base.buf = (uint32_t *)cs->ib_mapped;
343 cs->base.max_dw = ib_size / 4 - 4;
344 cs->ib_size_ptr = &cs->ib.size;
345 cs->ib.size = 0;
346
347 ws->cs_add_buffer(&cs->base, cs->ib_buffer);
348 } else {
349 cs->base.buf = malloc(16384);
350 cs->base.max_dw = 4096;
351 if (!cs->base.buf) {
352 free(cs);
353 return NULL;
354 }
355 }
356
357 return &cs->base;
358 }
359
360 static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
361 {
362 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
363
364 if (cs->failed) {
365 cs->base.cdw = 0;
366 return;
367 }
368
369 if (!cs->ws->use_ib_bos) {
370 const uint64_t limit_dws = 0xffff8;
371 uint64_t ib_dws = MAX2(cs->base.cdw + min_size,
372 MIN2(cs->base.max_dw * 2, limit_dws));
373
374 /* The total ib size cannot exceed limit_dws dwords. */
375 if (ib_dws > limit_dws)
376 {
377 /* The maximum size in dwords has been reached,
378 * try to allocate a new one.
379 */
380 cs->old_cs_buffers =
381 realloc(cs->old_cs_buffers,
382 (cs->num_old_cs_buffers + 1) * sizeof(*cs->old_cs_buffers));
383 if (!cs->old_cs_buffers) {
384 cs->failed = true;
385 cs->base.cdw = 0;
386 return;
387 }
388
389 /* Store the current one for submitting it later. */
390 cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw;
391 cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw = cs->base.max_dw;
392 cs->old_cs_buffers[cs->num_old_cs_buffers].buf = cs->base.buf;
393 cs->num_old_cs_buffers++;
394
395 /* Reset the cs, it will be re-allocated below. */
396 cs->base.cdw = 0;
397 cs->base.buf = NULL;
398
399 /* Re-compute the number of dwords to allocate. */
400 ib_dws = MAX2(cs->base.cdw + min_size,
401 MIN2(cs->base.max_dw * 2, limit_dws));
402 if (ib_dws > limit_dws) {
403 fprintf(stderr, "amdgpu: Too high number of "
404 "dwords to allocate\n");
405 cs->failed = true;
406 return;
407 }
408 }
409
410 uint32_t *new_buf = realloc(cs->base.buf, ib_dws * 4);
411 if (new_buf) {
412 cs->base.buf = new_buf;
413 cs->base.max_dw = ib_dws;
414 } else {
415 cs->failed = true;
416 cs->base.cdw = 0;
417 }
418 return;
419 }
420
421 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2);
422
423 /* max that fits in the chain size field. */
424 ib_size = MIN2(ib_size, 0xfffff);
425
426 while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
427 radeon_emit(&cs->base, 0xffff1000);
428
429 *cs->ib_size_ptr |= cs->base.cdw + 4;
430
431 if (cs->num_old_ib_buffers == cs->max_num_old_ib_buffers) {
432 cs->max_num_old_ib_buffers = MAX2(1, cs->max_num_old_ib_buffers * 2);
433 cs->old_ib_buffers = realloc(cs->old_ib_buffers,
434 cs->max_num_old_ib_buffers * sizeof(void*));
435 }
436
437 cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
438
439 cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
440 RADEON_DOMAIN_GTT,
441 RADEON_FLAG_CPU_ACCESS |
442 RADEON_FLAG_NO_INTERPROCESS_SHARING |
443 RADEON_FLAG_READ_ONLY,
444 RADV_BO_PRIORITY_CS);
445
446 if (!cs->ib_buffer) {
447 cs->base.cdw = 0;
448 cs->failed = true;
449 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
450 }
451
452 cs->ib_mapped = cs->ws->base.buffer_map(cs->ib_buffer);
453 if (!cs->ib_mapped) {
454 cs->ws->base.buffer_destroy(cs->ib_buffer);
455 cs->base.cdw = 0;
456 cs->failed = true;
457 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
458 }
459
460 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
461
462 radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
463 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va);
464 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va >> 32);
465 radeon_emit(&cs->base, S_3F2_CHAIN(1) | S_3F2_VALID(1));
466
467 cs->ib_size_ptr = cs->base.buf + cs->base.cdw - 1;
468
469 cs->base.buf = (uint32_t *)cs->ib_mapped;
470 cs->base.cdw = 0;
471 cs->base.max_dw = ib_size / 4 - 4;
472
473 }
474
475 static bool radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
476 {
477 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
478
479 if (cs->ws->use_ib_bos) {
480 while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
481 radeon_emit(&cs->base, 0xffff1000);
482
483 *cs->ib_size_ptr |= cs->base.cdw;
484
485 cs->is_chained = false;
486 }
487
488 return !cs->failed;
489 }
490
491 static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
492 {
493 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
494 cs->base.cdw = 0;
495 cs->failed = false;
496
497 for (unsigned i = 0; i < cs->num_buffers; ++i) {
498 unsigned hash = cs->handles[i].bo_handle &
499 (ARRAY_SIZE(cs->buffer_hash_table) - 1);
500 cs->buffer_hash_table[hash] = -1;
501 }
502
503 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
504 unsigned hash = ((uintptr_t)cs->virtual_buffers[i] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
505 cs->virtual_buffer_hash_table[hash] = -1;
506 }
507
508 cs->num_buffers = 0;
509 cs->num_virtual_buffers = 0;
510
511 if (cs->ws->use_ib_bos) {
512 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
513
514 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
515 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
516
517 cs->num_old_ib_buffers = 0;
518 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
519 cs->ib_size_ptr = &cs->ib.size;
520 cs->ib.size = 0;
521 } else {
522 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
523 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
524 free(rcs->buf);
525 }
526
527 free(cs->old_cs_buffers);
528 cs->old_cs_buffers = NULL;
529 cs->num_old_cs_buffers = 0;
530 }
531 }
532
533 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs *cs,
534 uint32_t bo)
535 {
536 unsigned hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
537 int index = cs->buffer_hash_table[hash];
538
539 if (index == -1)
540 return -1;
541
542 if (cs->handles[index].bo_handle == bo)
543 return index;
544
545 for (unsigned i = 0; i < cs->num_buffers; ++i) {
546 if (cs->handles[i].bo_handle == bo) {
547 cs->buffer_hash_table[hash] = i;
548 return i;
549 }
550 }
551
552 return -1;
553 }
554
555 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
556 uint32_t bo, uint8_t priority)
557 {
558 unsigned hash;
559 int index = radv_amdgpu_cs_find_buffer(cs, bo);
560
561 if (index != -1)
562 return;
563
564 if (cs->num_buffers == cs->max_num_buffers) {
565 unsigned new_count = MAX2(1, cs->max_num_buffers * 2);
566 cs->handles = realloc(cs->handles, new_count * sizeof(struct drm_amdgpu_bo_list_entry));
567 cs->max_num_buffers = new_count;
568 }
569
570 cs->handles[cs->num_buffers].bo_handle = bo;
571 cs->handles[cs->num_buffers].bo_priority = priority;
572
573 hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
574 cs->buffer_hash_table[hash] = cs->num_buffers;
575
576 ++cs->num_buffers;
577 }
578
579 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
580 struct radeon_winsys_bo *bo)
581 {
582 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
583 unsigned hash = ((uintptr_t)bo >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
584
585
586 if (!cs->virtual_buffer_hash_table) {
587 cs->virtual_buffer_hash_table = malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE * sizeof(int));
588 for (int i = 0; i < VIRTUAL_BUFFER_HASH_TABLE_SIZE; ++i)
589 cs->virtual_buffer_hash_table[i] = -1;
590 }
591
592 if (cs->virtual_buffer_hash_table[hash] >= 0) {
593 int idx = cs->virtual_buffer_hash_table[hash];
594 if (cs->virtual_buffers[idx] == bo) {
595 return;
596 }
597 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
598 if (cs->virtual_buffers[i] == bo) {
599 cs->virtual_buffer_hash_table[hash] = i;
600 return;
601 }
602 }
603 }
604
605 if(cs->max_num_virtual_buffers <= cs->num_virtual_buffers) {
606 cs->max_num_virtual_buffers = MAX2(2, cs->max_num_virtual_buffers * 2);
607 cs->virtual_buffers = realloc(cs->virtual_buffers, sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * cs->max_num_virtual_buffers);
608 }
609
610 cs->virtual_buffers[cs->num_virtual_buffers] = bo;
611
612 cs->virtual_buffer_hash_table[hash] = cs->num_virtual_buffers;
613 ++cs->num_virtual_buffers;
614
615 }
616
617 static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf *_cs,
618 struct radeon_winsys_bo *_bo)
619 {
620 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
621 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
622
623 if (bo->is_virtual) {
624 radv_amdgpu_cs_add_virtual_buffer(_cs, _bo);
625 return;
626 }
627
628 if (bo->base.is_local)
629 return;
630
631 radv_amdgpu_cs_add_buffer_internal(cs, bo->bo_handle, bo->priority);
632 }
633
634 static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent,
635 struct radeon_cmdbuf *_child)
636 {
637 struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
638 struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
639
640 for (unsigned i = 0; i < child->num_buffers; ++i) {
641 radv_amdgpu_cs_add_buffer_internal(parent,
642 child->handles[i].bo_handle,
643 child->handles[i].bo_priority);
644 }
645
646 for (unsigned i = 0; i < child->num_virtual_buffers; ++i) {
647 radv_amdgpu_cs_add_buffer(&parent->base, child->virtual_buffers[i]);
648 }
649
650 if (parent->ws->use_ib_bos) {
651 if (parent->base.cdw + 4 > parent->base.max_dw)
652 radv_amdgpu_cs_grow(&parent->base, 4);
653
654 radeon_emit(&parent->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
655 radeon_emit(&parent->base, child->ib.ib_mc_address);
656 radeon_emit(&parent->base, child->ib.ib_mc_address >> 32);
657 radeon_emit(&parent->base, child->ib.size);
658 } else {
659 if (parent->base.cdw + child->base.cdw > parent->base.max_dw)
660 radv_amdgpu_cs_grow(&parent->base, child->base.cdw);
661
662 memcpy(parent->base.buf + parent->base.cdw, child->base.buf, 4 * child->base.cdw);
663 parent->base.cdw += child->base.cdw;
664 }
665 }
666
667 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
668 struct radeon_cmdbuf **cs_array,
669 unsigned count,
670 struct radv_amdgpu_winsys_bo **extra_bo_array,
671 unsigned num_extra_bo,
672 struct radeon_cmdbuf *extra_cs,
673 const struct radv_winsys_bo_list *radv_bo_list,
674 uint32_t *bo_list)
675 {
676 int r = 0;
677
678 if (ws->debug_all_bos) {
679 struct radv_amdgpu_winsys_bo *bo;
680 struct drm_amdgpu_bo_list_entry *handles;
681 unsigned num = 0;
682
683 pthread_mutex_lock(&ws->global_bo_list_lock);
684
685 handles = malloc(sizeof(handles[0]) * ws->num_buffers);
686 if (!handles) {
687 pthread_mutex_unlock(&ws->global_bo_list_lock);
688 return -ENOMEM;
689 }
690
691 LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
692 assert(num < ws->num_buffers);
693 handles[num].bo_handle = bo->bo_handle;
694 handles[num].bo_priority = bo->priority;
695 num++;
696 }
697
698 r = amdgpu_bo_list_create_raw(ws->dev, ws->num_buffers,
699 handles, bo_list);
700 free(handles);
701 pthread_mutex_unlock(&ws->global_bo_list_lock);
702 } else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list &&
703 !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
704 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
705 if (cs->num_buffers == 0) {
706 *bo_list = 0;
707 return 0;
708 }
709 r = amdgpu_bo_list_create_raw(ws->dev, cs->num_buffers, cs->handles,
710 bo_list);
711 } else {
712 unsigned total_buffer_count = num_extra_bo;
713 unsigned unique_bo_count = num_extra_bo;
714 for (unsigned i = 0; i < count; ++i) {
715 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[i];
716 total_buffer_count += cs->num_buffers;
717 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j)
718 total_buffer_count += radv_amdgpu_winsys_bo(cs->virtual_buffers[j])->bo_count;
719 }
720
721 if (extra_cs) {
722 total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
723 }
724
725 if (radv_bo_list) {
726 total_buffer_count += radv_bo_list->count;
727 }
728
729 if (total_buffer_count == 0) {
730 *bo_list = 0;
731 return 0;
732 }
733 struct drm_amdgpu_bo_list_entry *handles = malloc(sizeof(struct drm_amdgpu_bo_list_entry) * total_buffer_count);
734 if (!handles)
735 return -ENOMEM;
736
737 for (unsigned i = 0; i < num_extra_bo; i++) {
738 handles[i].bo_handle = extra_bo_array[i]->bo_handle;
739 handles[i].bo_priority = extra_bo_array[i]->priority;
740 }
741
742 for (unsigned i = 0; i < count + !!extra_cs; ++i) {
743 struct radv_amdgpu_cs *cs;
744
745 if (i == count)
746 cs = (struct radv_amdgpu_cs*)extra_cs;
747 else
748 cs = (struct radv_amdgpu_cs*)cs_array[i];
749
750 if (!cs->num_buffers)
751 continue;
752
753 if (unique_bo_count == 0 && !cs->num_virtual_buffers) {
754 memcpy(handles, cs->handles, cs->num_buffers * sizeof(struct drm_amdgpu_bo_list_entry));
755 unique_bo_count = cs->num_buffers;
756 continue;
757 }
758 int unique_bo_so_far = unique_bo_count;
759 for (unsigned j = 0; j < cs->num_buffers; ++j) {
760 bool found = false;
761 for (unsigned k = 0; k < unique_bo_so_far; ++k) {
762 if (handles[k].bo_handle == cs->handles[j].bo_handle) {
763 found = true;
764 break;
765 }
766 }
767 if (!found) {
768 handles[unique_bo_count] = cs->handles[j];
769 ++unique_bo_count;
770 }
771 }
772 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j) {
773 struct radv_amdgpu_winsys_bo *virtual_bo = radv_amdgpu_winsys_bo(cs->virtual_buffers[j]);
774 for(unsigned k = 0; k < virtual_bo->bo_count; ++k) {
775 struct radv_amdgpu_winsys_bo *bo = virtual_bo->bos[k];
776 bool found = false;
777 for (unsigned m = 0; m < unique_bo_count; ++m) {
778 if (handles[m].bo_handle == bo->bo_handle) {
779 found = true;
780 break;
781 }
782 }
783 if (!found) {
784 handles[unique_bo_count].bo_handle = bo->bo_handle;
785 handles[unique_bo_count].bo_priority = bo->priority;
786 ++unique_bo_count;
787 }
788 }
789 }
790 }
791
792 if (radv_bo_list) {
793 unsigned unique_bo_so_far = unique_bo_count;
794 for (unsigned i = 0; i < radv_bo_list->count; ++i) {
795 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(radv_bo_list->bos[i]);
796 bool found = false;
797 for (unsigned j = 0; j < unique_bo_so_far; ++j) {
798 if (bo->bo_handle == handles[j].bo_handle) {
799 found = true;
800 break;
801 }
802 }
803 if (!found) {
804 handles[unique_bo_count].bo_handle = bo->bo_handle;
805 handles[unique_bo_count].bo_priority = bo->priority;
806 ++unique_bo_count;
807 }
808 }
809 }
810
811 if (unique_bo_count > 0) {
812 r = amdgpu_bo_list_create_raw(ws->dev, unique_bo_count, handles,
813 bo_list);
814 } else {
815 *bo_list = 0;
816 }
817
818 free(handles);
819 }
820
821 return r;
822 }
823
824 static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_ctx *ctx, int ip_type, int ring)
825 {
826 struct amdgpu_cs_fence_info ret = {0};
827 if (ctx->fence_map) {
828 ret.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
829 ret.offset = (ip_type * MAX_RINGS_PER_TYPE + ring) * sizeof(uint64_t);
830 }
831 return ret;
832 }
833
834 static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
835 struct radv_amdgpu_cs_request *request)
836 {
837 radv_amdgpu_request_to_fence(ctx,
838 &ctx->last_submission[request->ip_type][request->ring],
839 request);
840 }
841
842 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
843 int queue_idx,
844 struct radv_winsys_sem_info *sem_info,
845 const struct radv_winsys_bo_list *radv_bo_list,
846 struct radeon_cmdbuf **cs_array,
847 unsigned cs_count,
848 struct radeon_cmdbuf *initial_preamble_cs,
849 struct radeon_cmdbuf *continue_preamble_cs,
850 struct radeon_winsys_fence *_fence)
851 {
852 int r;
853 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
854 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
855 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
856 uint32_t bo_list;
857 struct radv_amdgpu_cs_request request = {0};
858 struct amdgpu_cs_ib_info ibs[2];
859 unsigned number_of_ibs = 1;
860
861 for (unsigned i = cs_count; i--;) {
862 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
863
864 if (cs->is_chained) {
865 *cs->ib_size_ptr -= 4;
866 cs->is_chained = false;
867 }
868
869 if (i + 1 < cs_count) {
870 struct radv_amdgpu_cs *next = radv_amdgpu_cs(cs_array[i + 1]);
871 assert(cs->base.cdw + 4 <= cs->base.max_dw);
872
873 cs->is_chained = true;
874 *cs->ib_size_ptr += 4;
875
876 cs->base.buf[cs->base.cdw + 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
877 cs->base.buf[cs->base.cdw + 1] = next->ib.ib_mc_address;
878 cs->base.buf[cs->base.cdw + 2] = next->ib.ib_mc_address >> 32;
879 cs->base.buf[cs->base.cdw + 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next->ib.size;
880 }
881 }
882
883 /* Create a buffer object list. */
884 r = radv_amdgpu_create_bo_list(cs0->ws, cs_array, cs_count, NULL, 0,
885 initial_preamble_cs, radv_bo_list,
886 &bo_list);
887 if (r) {
888 fprintf(stderr, "amdgpu: buffer list creation failed for the "
889 "chained submission(%d)\n", r);
890 return r;
891 }
892
893 /* Configure the CS request. */
894 if (initial_preamble_cs) {
895 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
896 ibs[1] = cs0->ib;
897 number_of_ibs++;
898 } else {
899 ibs[0] = cs0->ib;
900 }
901
902 request.ip_type = cs0->hw_ip;
903 request.ring = queue_idx;
904 request.number_of_ibs = number_of_ibs;
905 request.ibs = ibs;
906 request.resources = bo_list;
907 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
908
909 /* Submit the CS. */
910 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
911 if (r) {
912 if (r == -ENOMEM)
913 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
914 else
915 fprintf(stderr, "amdgpu: The CS has been rejected, "
916 "see dmesg for more information.\n");
917 }
918
919 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
920
921 if (r)
922 return r;
923
924 if (fence)
925 radv_amdgpu_request_to_fence(ctx, fence, &request);
926
927 radv_assign_last_submit(ctx, &request);
928
929 return 0;
930 }
931
932 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
933 int queue_idx,
934 struct radv_winsys_sem_info *sem_info,
935 const struct radv_winsys_bo_list *radv_bo_list,
936 struct radeon_cmdbuf **cs_array,
937 unsigned cs_count,
938 struct radeon_cmdbuf *initial_preamble_cs,
939 struct radeon_cmdbuf *continue_preamble_cs,
940 struct radeon_winsys_fence *_fence)
941 {
942 int r;
943 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
944 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
945 uint32_t bo_list;
946 struct radv_amdgpu_cs_request request = {};
947 struct amdgpu_cs_ib_info *ibs;
948 struct radv_amdgpu_cs *cs0;
949 unsigned number_of_ibs;
950
951 assert(cs_count);
952 cs0 = radv_amdgpu_cs(cs_array[0]);
953
954 /* Compute the number of IBs for this submit. */
955 number_of_ibs = cs_count + !!initial_preamble_cs;
956
957 /* Create a buffer object list. */
958 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[0], cs_count, NULL, 0,
959 initial_preamble_cs, radv_bo_list,
960 &bo_list);
961 if (r) {
962 fprintf(stderr, "amdgpu: buffer list creation failed "
963 "for the fallback submission (%d)\n", r);
964 return r;
965 }
966
967 ibs = malloc(number_of_ibs * sizeof(*ibs));
968 if (!ibs) {
969 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
970 return -ENOMEM;
971 }
972
973 /* Configure the CS request. */
974 if (initial_preamble_cs)
975 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
976
977 for (unsigned i = 0; i < cs_count; i++) {
978 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
979
980 ibs[i + !!initial_preamble_cs] = cs->ib;
981
982 if (cs->is_chained) {
983 *cs->ib_size_ptr -= 4;
984 cs->is_chained = false;
985 }
986 }
987
988 request.ip_type = cs0->hw_ip;
989 request.ring = queue_idx;
990 request.resources = bo_list;
991 request.number_of_ibs = number_of_ibs;
992 request.ibs = ibs;
993 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
994
995 /* Submit the CS. */
996 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
997 if (r) {
998 if (r == -ENOMEM)
999 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1000 else
1001 fprintf(stderr, "amdgpu: The CS has been rejected, "
1002 "see dmesg for more information.\n");
1003 }
1004
1005 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
1006 free(ibs);
1007
1008 if (r)
1009 return r;
1010
1011 if (fence)
1012 radv_amdgpu_request_to_fence(ctx, fence, &request);
1013
1014 radv_assign_last_submit(ctx, &request);
1015
1016 return 0;
1017 }
1018
1019 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
1020 int queue_idx,
1021 struct radv_winsys_sem_info *sem_info,
1022 const struct radv_winsys_bo_list *radv_bo_list,
1023 struct radeon_cmdbuf **cs_array,
1024 unsigned cs_count,
1025 struct radeon_cmdbuf *initial_preamble_cs,
1026 struct radeon_cmdbuf *continue_preamble_cs,
1027 struct radeon_winsys_fence *_fence)
1028 {
1029 int r;
1030 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1031 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
1032 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
1033 struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
1034 uint32_t bo_list;
1035 struct radv_amdgpu_cs_request request;
1036 uint32_t pad_word = 0xffff1000U;
1037 bool emit_signal_sem = sem_info->cs_emit_signal;
1038
1039 if (radv_amdgpu_winsys(ws)->info.chip_class == GFX6)
1040 pad_word = 0x80000000;
1041
1042 assert(cs_count);
1043
1044 for (unsigned i = 0; i < cs_count;) {
1045 struct amdgpu_cs_ib_info *ibs;
1046 struct radeon_winsys_bo **bos;
1047 struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
1048 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
1049 unsigned number_of_ibs;
1050 uint32_t *ptr;
1051 unsigned cnt = 0;
1052 unsigned size = 0;
1053 unsigned pad_words = 0;
1054
1055 /* Compute the number of IBs for this submit. */
1056 number_of_ibs = cs->num_old_cs_buffers + 1;
1057
1058 ibs = malloc(number_of_ibs * sizeof(*ibs));
1059 if (!ibs)
1060 return -ENOMEM;
1061
1062 bos = malloc(number_of_ibs * sizeof(*bos));
1063 if (!bos) {
1064 free(ibs);
1065 return -ENOMEM;
1066 }
1067
1068 if (number_of_ibs > 1) {
1069 /* Special path when the maximum size in dwords has
1070 * been reached because we need to handle more than one
1071 * IB per submit.
1072 */
1073 struct radeon_cmdbuf **new_cs_array;
1074 unsigned idx = 0;
1075
1076 new_cs_array = malloc(cs->num_old_cs_buffers *
1077 sizeof(*new_cs_array));
1078 assert(new_cs_array);
1079
1080 for (unsigned j = 0; j < cs->num_old_cs_buffers; j++)
1081 new_cs_array[idx++] = &cs->old_cs_buffers[j];
1082 new_cs_array[idx++] = cs_array[i];
1083
1084 for (unsigned j = 0; j < number_of_ibs; j++) {
1085 struct radeon_cmdbuf *rcs = new_cs_array[j];
1086 bool needs_preamble = preamble_cs && j == 0;
1087 unsigned size = 0;
1088
1089 if (needs_preamble)
1090 size += preamble_cs->cdw;
1091 size += rcs->cdw;
1092
1093 assert(size < 0xffff8);
1094
1095 while (!size || (size & 7)) {
1096 size++;
1097 pad_words++;
1098 }
1099
1100 bos[j] = ws->buffer_create(ws, 4 * size, 4096,
1101 RADEON_DOMAIN_GTT,
1102 RADEON_FLAG_CPU_ACCESS |
1103 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1104 RADEON_FLAG_READ_ONLY,
1105 RADV_BO_PRIORITY_CS);
1106 ptr = ws->buffer_map(bos[j]);
1107
1108 if (needs_preamble) {
1109 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1110 ptr += preamble_cs->cdw;
1111 }
1112
1113 memcpy(ptr, rcs->buf, 4 * rcs->cdw);
1114 ptr += rcs->cdw;
1115
1116 for (unsigned k = 0; k < pad_words; ++k)
1117 *ptr++ = pad_word;
1118
1119 ibs[j].size = size;
1120 ibs[j].ib_mc_address = radv_buffer_get_va(bos[j]);
1121 ibs[j].flags = 0;
1122 }
1123
1124 cnt++;
1125 free(new_cs_array);
1126 } else {
1127 if (preamble_cs)
1128 size += preamble_cs->cdw;
1129
1130 while (i + cnt < cs_count && 0xffff8 - size >= radv_amdgpu_cs(cs_array[i + cnt])->base.cdw) {
1131 size += radv_amdgpu_cs(cs_array[i + cnt])->base.cdw;
1132 ++cnt;
1133 }
1134
1135 while (!size || (size & 7)) {
1136 size++;
1137 pad_words++;
1138 }
1139 assert(cnt);
1140
1141 bos[0] = ws->buffer_create(ws, 4 * size, 4096,
1142 RADEON_DOMAIN_GTT,
1143 RADEON_FLAG_CPU_ACCESS |
1144 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1145 RADEON_FLAG_READ_ONLY,
1146 RADV_BO_PRIORITY_CS);
1147 ptr = ws->buffer_map(bos[0]);
1148
1149 if (preamble_cs) {
1150 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1151 ptr += preamble_cs->cdw;
1152 }
1153
1154 for (unsigned j = 0; j < cnt; ++j) {
1155 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + j]);
1156 memcpy(ptr, cs->base.buf, 4 * cs->base.cdw);
1157 ptr += cs->base.cdw;
1158
1159 }
1160
1161 for (unsigned j = 0; j < pad_words; ++j)
1162 *ptr++ = pad_word;
1163
1164 ibs[0].size = size;
1165 ibs[0].ib_mc_address = radv_buffer_get_va(bos[0]);
1166 ibs[0].flags = 0;
1167 }
1168
1169 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt,
1170 (struct radv_amdgpu_winsys_bo **)bos,
1171 number_of_ibs, preamble_cs,
1172 radv_bo_list, &bo_list);
1173 if (r) {
1174 fprintf(stderr, "amdgpu: buffer list creation failed "
1175 "for the sysmem submission (%d)\n", r);
1176 free(ibs);
1177 free(bos);
1178 return r;
1179 }
1180
1181 memset(&request, 0, sizeof(request));
1182
1183 request.ip_type = cs0->hw_ip;
1184 request.ring = queue_idx;
1185 request.resources = bo_list;
1186 request.number_of_ibs = number_of_ibs;
1187 request.ibs = ibs;
1188 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
1189
1190 sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
1191 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
1192 if (r) {
1193 if (r == -ENOMEM)
1194 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1195 else
1196 fprintf(stderr, "amdgpu: The CS has been rejected, "
1197 "see dmesg for more information.\n");
1198 }
1199
1200 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
1201
1202 for (unsigned j = 0; j < number_of_ibs; j++) {
1203 ws->buffer_destroy(bos[j]);
1204 }
1205
1206 free(ibs);
1207 free(bos);
1208
1209 if (r)
1210 return r;
1211
1212 i += cnt;
1213 }
1214 if (fence)
1215 radv_amdgpu_request_to_fence(ctx, fence, &request);
1216
1217 radv_assign_last_submit(ctx, &request);
1218
1219 return 0;
1220 }
1221
1222 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
1223 int queue_idx,
1224 struct radeon_cmdbuf **cs_array,
1225 unsigned cs_count,
1226 struct radeon_cmdbuf *initial_preamble_cs,
1227 struct radeon_cmdbuf *continue_preamble_cs,
1228 struct radv_winsys_sem_info *sem_info,
1229 const struct radv_winsys_bo_list *bo_list,
1230 bool can_patch,
1231 struct radeon_winsys_fence *_fence)
1232 {
1233 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
1234 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1235 int ret;
1236
1237 assert(sem_info);
1238 if (!cs->ws->use_ib_bos) {
1239 ret = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, bo_list, cs_array,
1240 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1241 } else if (can_patch) {
1242 ret = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, bo_list, cs_array,
1243 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1244 } else {
1245 ret = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, bo_list, cs_array,
1246 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1247 }
1248
1249 radv_amdgpu_signal_sems(ctx, cs->hw_ip, queue_idx, sem_info);
1250 return ret;
1251 }
1252
1253 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
1254 {
1255 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1256 void *ret = NULL;
1257
1258 if (!cs->ib_buffer)
1259 return NULL;
1260 for (unsigned i = 0; i <= cs->num_old_ib_buffers; ++i) {
1261 struct radv_amdgpu_winsys_bo *bo;
1262
1263 bo = (struct radv_amdgpu_winsys_bo*)
1264 (i == cs->num_old_ib_buffers ? cs->ib_buffer : cs->old_ib_buffers[i]);
1265 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1266 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0)
1267 return (char *)ret + (addr - bo->base.va);
1268 }
1269 }
1270 if(cs->ws->debug_all_bos) {
1271 pthread_mutex_lock(&cs->ws->global_bo_list_lock);
1272 list_for_each_entry(struct radv_amdgpu_winsys_bo, bo,
1273 &cs->ws->global_bo_list, global_list_item) {
1274 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1275 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0) {
1276 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1277 return (char *)ret + (addr - bo->base.va);
1278 }
1279 }
1280 }
1281 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1282 }
1283 return ret;
1284 }
1285
1286 static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs,
1287 FILE* file,
1288 const int *trace_ids, int trace_id_count)
1289 {
1290 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1291 void *ib = cs->base.buf;
1292 int num_dw = cs->base.cdw;
1293
1294 if (cs->ws->use_ib_bos) {
1295 ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
1296 num_dw = cs->ib.size;
1297 }
1298 assert(ib);
1299 ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB",
1300 cs->ws->info.chip_class, radv_amdgpu_winsys_get_cpu_addr, cs);
1301 }
1302
1303 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority)
1304 {
1305 switch (radv_priority) {
1306 case RADEON_CTX_PRIORITY_REALTIME:
1307 return AMDGPU_CTX_PRIORITY_VERY_HIGH;
1308 case RADEON_CTX_PRIORITY_HIGH:
1309 return AMDGPU_CTX_PRIORITY_HIGH;
1310 case RADEON_CTX_PRIORITY_MEDIUM:
1311 return AMDGPU_CTX_PRIORITY_NORMAL;
1312 case RADEON_CTX_PRIORITY_LOW:
1313 return AMDGPU_CTX_PRIORITY_LOW;
1314 default:
1315 unreachable("Invalid context priority");
1316 }
1317 }
1318
1319 static VkResult radv_amdgpu_ctx_create(struct radeon_winsys *_ws,
1320 enum radeon_ctx_priority priority,
1321 struct radeon_winsys_ctx **rctx)
1322 {
1323 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1324 struct radv_amdgpu_ctx *ctx = CALLOC_STRUCT(radv_amdgpu_ctx);
1325 uint32_t amdgpu_priority = radv_to_amdgpu_priority(priority);
1326 VkResult result;
1327 int r;
1328
1329 if (!ctx)
1330 return VK_ERROR_OUT_OF_HOST_MEMORY;
1331
1332 r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
1333 if (r && r == -EACCES) {
1334 result = VK_ERROR_NOT_PERMITTED_EXT;
1335 goto error_create;
1336 } else if (r) {
1337 fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r);
1338 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1339 goto error_create;
1340 }
1341 ctx->ws = ws;
1342
1343 assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
1344 ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
1345 RADEON_DOMAIN_GTT,
1346 RADEON_FLAG_CPU_ACCESS |
1347 RADEON_FLAG_NO_INTERPROCESS_SHARING,
1348 RADV_BO_PRIORITY_CS);
1349 if (ctx->fence_bo)
1350 ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
1351 if (ctx->fence_map)
1352 memset(ctx->fence_map, 0, 4096);
1353
1354 *rctx = (struct radeon_winsys_ctx *)ctx;
1355 return VK_SUCCESS;
1356 error_create:
1357 FREE(ctx);
1358 return result;
1359 }
1360
1361 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
1362 {
1363 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1364 ctx->ws->base.buffer_destroy(ctx->fence_bo);
1365 amdgpu_cs_ctx_free(ctx->ctx);
1366 FREE(ctx);
1367 }
1368
1369 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
1370 enum ring_type ring_type, int ring_index)
1371 {
1372 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1373 int ip_type = ring_to_hw_ip(ring_type);
1374
1375 if (ctx->last_submission[ip_type][ring_index].fence.fence) {
1376 uint32_t expired;
1377 int ret = amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index].fence,
1378 1000000000ull, 0, &expired);
1379
1380 if (ret || !expired)
1381 return false;
1382 }
1383
1384 return true;
1385 }
1386
1387 static struct radeon_winsys_sem *radv_amdgpu_create_sem(struct radeon_winsys *_ws)
1388 {
1389 struct amdgpu_cs_fence *sem = CALLOC_STRUCT(amdgpu_cs_fence);
1390 if (!sem)
1391 return NULL;
1392
1393 return (struct radeon_winsys_sem *)sem;
1394 }
1395
1396 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem *_sem)
1397 {
1398 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)_sem;
1399 FREE(sem);
1400 }
1401
1402 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
1403 uint32_t ip_type,
1404 uint32_t ring,
1405 struct radv_winsys_sem_info *sem_info)
1406 {
1407 for (unsigned i = 0; i < sem_info->signal.sem_count; i++) {
1408 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)(sem_info->signal.sem)[i];
1409
1410 if (sem->context)
1411 return -EINVAL;
1412
1413 *sem = ctx->last_submission[ip_type][ring].fence;
1414 }
1415 return 0;
1416 }
1417
1418 static struct drm_amdgpu_cs_chunk_sem *radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts *counts,
1419 struct drm_amdgpu_cs_chunk *chunk, int chunk_id)
1420 {
1421 struct drm_amdgpu_cs_chunk_sem *syncobj = malloc(sizeof(struct drm_amdgpu_cs_chunk_sem) * counts->syncobj_count);
1422 if (!syncobj)
1423 return NULL;
1424
1425 for (unsigned i = 0; i < counts->syncobj_count; i++) {
1426 struct drm_amdgpu_cs_chunk_sem *sem = &syncobj[i];
1427 sem->handle = counts->syncobj[i];
1428 }
1429
1430 chunk->chunk_id = chunk_id;
1431 chunk->length_dw = sizeof(struct drm_amdgpu_cs_chunk_sem) / 4 * counts->syncobj_count;
1432 chunk->chunk_data = (uint64_t)(uintptr_t)syncobj;
1433 return syncobj;
1434 }
1435
1436 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
1437 struct radv_amdgpu_cs_request *request,
1438 struct radv_winsys_sem_info *sem_info)
1439 {
1440 int r;
1441 int num_chunks;
1442 int size;
1443 bool user_fence;
1444 struct drm_amdgpu_cs_chunk *chunks;
1445 struct drm_amdgpu_cs_chunk_data *chunk_data;
1446 struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
1447 struct drm_amdgpu_cs_chunk_sem *wait_syncobj = NULL, *signal_syncobj = NULL;
1448 int i;
1449 struct amdgpu_cs_fence *sem;
1450
1451 user_fence = (request->fence_info.handle != NULL);
1452 size = request->number_of_ibs + (user_fence ? 2 : 1) + 3;
1453
1454 chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
1455
1456 size = request->number_of_ibs + (user_fence ? 1 : 0);
1457
1458 chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
1459
1460 num_chunks = request->number_of_ibs;
1461 for (i = 0; i < request->number_of_ibs; i++) {
1462 struct amdgpu_cs_ib_info *ib;
1463 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
1464 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
1465 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1466
1467 ib = &request->ibs[i];
1468
1469 chunk_data[i].ib_data._pad = 0;
1470 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
1471 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
1472 chunk_data[i].ib_data.ip_type = request->ip_type;
1473 chunk_data[i].ib_data.ip_instance = request->ip_instance;
1474 chunk_data[i].ib_data.ring = request->ring;
1475 chunk_data[i].ib_data.flags = ib->flags;
1476 }
1477
1478 if (user_fence) {
1479 i = num_chunks++;
1480
1481 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
1482 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
1483 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1484
1485 amdgpu_cs_chunk_fence_info_to_data(&request->fence_info,
1486 &chunk_data[i]);
1487 }
1488
1489 if (sem_info->wait.syncobj_count && sem_info->cs_emit_wait) {
1490 wait_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->wait,
1491 &chunks[num_chunks],
1492 AMDGPU_CHUNK_ID_SYNCOBJ_IN);
1493 if (!wait_syncobj) {
1494 r = -ENOMEM;
1495 goto error_out;
1496 }
1497 num_chunks++;
1498
1499 if (sem_info->wait.sem_count == 0)
1500 sem_info->cs_emit_wait = false;
1501
1502 }
1503
1504 if (sem_info->wait.sem_count && sem_info->cs_emit_wait) {
1505 sem_dependencies = alloca(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_info->wait.sem_count);
1506 int sem_count = 0;
1507
1508 for (unsigned j = 0; j < sem_info->wait.sem_count; j++) {
1509 sem = (struct amdgpu_cs_fence *)sem_info->wait.sem[j];
1510 if (!sem->context)
1511 continue;
1512 struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
1513
1514 amdgpu_cs_chunk_fence_to_dep(sem, dep);
1515
1516 sem->context = NULL;
1517 }
1518 i = num_chunks++;
1519
1520 /* dependencies chunk */
1521 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
1522 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
1523 chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
1524
1525 sem_info->cs_emit_wait = false;
1526 }
1527
1528 if (sem_info->signal.syncobj_count && sem_info->cs_emit_signal) {
1529 signal_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->signal,
1530 &chunks[num_chunks],
1531 AMDGPU_CHUNK_ID_SYNCOBJ_OUT);
1532 if (!signal_syncobj) {
1533 r = -ENOMEM;
1534 goto error_out;
1535 }
1536 num_chunks++;
1537 }
1538
1539 r = amdgpu_cs_submit_raw2(ctx->ws->dev,
1540 ctx->ctx,
1541 request->resources,
1542 num_chunks,
1543 chunks,
1544 &request->seq_no);
1545 error_out:
1546 free(wait_syncobj);
1547 free(signal_syncobj);
1548 return r;
1549 }
1550
1551 static int radv_amdgpu_create_syncobj(struct radeon_winsys *_ws,
1552 uint32_t *handle)
1553 {
1554 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1555 return amdgpu_cs_create_syncobj(ws->dev, handle);
1556 }
1557
1558 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys *_ws,
1559 uint32_t handle)
1560 {
1561 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1562 amdgpu_cs_destroy_syncobj(ws->dev, handle);
1563 }
1564
1565 static void radv_amdgpu_reset_syncobj(struct radeon_winsys *_ws,
1566 uint32_t handle)
1567 {
1568 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1569 amdgpu_cs_syncobj_reset(ws->dev, &handle, 1);
1570 }
1571
1572 static void radv_amdgpu_signal_syncobj(struct radeon_winsys *_ws,
1573 uint32_t handle)
1574 {
1575 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1576 amdgpu_cs_syncobj_signal(ws->dev, &handle, 1);
1577 }
1578
1579 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys *_ws, const uint32_t *handles,
1580 uint32_t handle_count, bool wait_all, uint64_t timeout)
1581 {
1582 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1583 uint32_t tmp;
1584
1585 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1586 timeout = MIN2(timeout, INT64_MAX);
1587
1588 int ret = amdgpu_cs_syncobj_wait(ws->dev, (uint32_t*)handles, handle_count, timeout,
1589 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT |
1590 (wait_all ? DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL : 0),
1591 &tmp);
1592 if (ret == 0) {
1593 return true;
1594 } else if (ret == -ETIME) {
1595 return false;
1596 } else {
1597 fprintf(stderr, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno);
1598 return false;
1599 }
1600 }
1601
1602 static int radv_amdgpu_export_syncobj(struct radeon_winsys *_ws,
1603 uint32_t syncobj,
1604 int *fd)
1605 {
1606 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1607
1608 return amdgpu_cs_export_syncobj(ws->dev, syncobj, fd);
1609 }
1610
1611 static int radv_amdgpu_import_syncobj(struct radeon_winsys *_ws,
1612 int fd,
1613 uint32_t *syncobj)
1614 {
1615 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1616
1617 return amdgpu_cs_import_syncobj(ws->dev, fd, syncobj);
1618 }
1619
1620
1621 static int radv_amdgpu_export_syncobj_to_sync_file(struct radeon_winsys *_ws,
1622 uint32_t syncobj,
1623 int *fd)
1624 {
1625 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1626
1627 return amdgpu_cs_syncobj_export_sync_file(ws->dev, syncobj, fd);
1628 }
1629
1630 static int radv_amdgpu_import_syncobj_from_sync_file(struct radeon_winsys *_ws,
1631 uint32_t syncobj,
1632 int fd)
1633 {
1634 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1635
1636 return amdgpu_cs_syncobj_import_sync_file(ws->dev, syncobj, fd);
1637 }
1638
1639 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
1640 {
1641 ws->base.ctx_create = radv_amdgpu_ctx_create;
1642 ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
1643 ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
1644 ws->base.cs_create = radv_amdgpu_cs_create;
1645 ws->base.cs_destroy = radv_amdgpu_cs_destroy;
1646 ws->base.cs_grow = radv_amdgpu_cs_grow;
1647 ws->base.cs_finalize = radv_amdgpu_cs_finalize;
1648 ws->base.cs_reset = radv_amdgpu_cs_reset;
1649 ws->base.cs_add_buffer = radv_amdgpu_cs_add_buffer;
1650 ws->base.cs_execute_secondary = radv_amdgpu_cs_execute_secondary;
1651 ws->base.cs_submit = radv_amdgpu_winsys_cs_submit;
1652 ws->base.cs_dump = radv_amdgpu_winsys_cs_dump;
1653 ws->base.create_fence = radv_amdgpu_create_fence;
1654 ws->base.destroy_fence = radv_amdgpu_destroy_fence;
1655 ws->base.reset_fence = radv_amdgpu_reset_fence;
1656 ws->base.signal_fence = radv_amdgpu_signal_fence;
1657 ws->base.is_fence_waitable = radv_amdgpu_is_fence_waitable;
1658 ws->base.create_sem = radv_amdgpu_create_sem;
1659 ws->base.destroy_sem = radv_amdgpu_destroy_sem;
1660 ws->base.create_syncobj = radv_amdgpu_create_syncobj;
1661 ws->base.destroy_syncobj = radv_amdgpu_destroy_syncobj;
1662 ws->base.reset_syncobj = radv_amdgpu_reset_syncobj;
1663 ws->base.signal_syncobj = radv_amdgpu_signal_syncobj;
1664 ws->base.wait_syncobj = radv_amdgpu_wait_syncobj;
1665 ws->base.export_syncobj = radv_amdgpu_export_syncobj;
1666 ws->base.import_syncobj = radv_amdgpu_import_syncobj;
1667 ws->base.export_syncobj_to_sync_file = radv_amdgpu_export_syncobj_to_sync_file;
1668 ws->base.import_syncobj_from_sync_file = radv_amdgpu_import_syncobj_from_sync_file;
1669 ws->base.fence_wait = radv_amdgpu_fence_wait;
1670 ws->base.fences_wait = radv_amdgpu_fences_wait;
1671 }