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radv/winsys: Deal with realloc failures in BO lists.
[mesa.git] / src / amd / vulkan / winsys / amdgpu / radv_amdgpu_cs.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdlib.h>
26 #include <amdgpu.h>
27 #include "drm-uapi/amdgpu_drm.h"
28 #include <assert.h>
29 #include <pthread.h>
30 #include <errno.h>
31
32 #include "util/u_memory.h"
33 #include "ac_debug.h"
34 #include "radv_radeon_winsys.h"
35 #include "radv_amdgpu_cs.h"
36 #include "radv_amdgpu_bo.h"
37 #include "sid.h"
38
39
40 enum {
41 VIRTUAL_BUFFER_HASH_TABLE_SIZE = 1024
42 };
43
44 struct radv_amdgpu_cs {
45 struct radeon_cmdbuf base;
46 struct radv_amdgpu_winsys *ws;
47
48 struct amdgpu_cs_ib_info ib;
49
50 struct radeon_winsys_bo *ib_buffer;
51 uint8_t *ib_mapped;
52 unsigned max_num_buffers;
53 unsigned num_buffers;
54 struct drm_amdgpu_bo_list_entry *handles;
55
56 struct radeon_winsys_bo **old_ib_buffers;
57 unsigned num_old_ib_buffers;
58 unsigned max_num_old_ib_buffers;
59 unsigned *ib_size_ptr;
60 bool failed;
61 bool is_chained;
62
63 int buffer_hash_table[1024];
64 unsigned hw_ip;
65
66 unsigned num_virtual_buffers;
67 unsigned max_num_virtual_buffers;
68 struct radeon_winsys_bo **virtual_buffers;
69 int *virtual_buffer_hash_table;
70
71 /* For chips that don't support chaining. */
72 struct radeon_cmdbuf *old_cs_buffers;
73 unsigned num_old_cs_buffers;
74 };
75
76 static inline struct radv_amdgpu_cs *
77 radv_amdgpu_cs(struct radeon_cmdbuf *base)
78 {
79 return (struct radv_amdgpu_cs*)base;
80 }
81
82 static int ring_to_hw_ip(enum ring_type ring)
83 {
84 switch (ring) {
85 case RING_GFX:
86 return AMDGPU_HW_IP_GFX;
87 case RING_DMA:
88 return AMDGPU_HW_IP_DMA;
89 case RING_COMPUTE:
90 return AMDGPU_HW_IP_COMPUTE;
91 default:
92 unreachable("unsupported ring");
93 }
94 }
95
96 struct radv_amdgpu_cs_request {
97 /** Specify flags with additional information */
98 uint64_t flags;
99
100 /** Specify HW IP block type to which to send the IB. */
101 unsigned ip_type;
102
103 /** IP instance index if there are several IPs of the same type. */
104 unsigned ip_instance;
105
106 /**
107 * Specify ring index of the IP. We could have several rings
108 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
109 */
110 uint32_t ring;
111
112 /**
113 * List handle with resources used by this request. This is a raw
114 * bo list handle used by the kernel.
115 */
116 uint32_t resources;
117
118 /**
119 * Number of dependencies this Command submission needs to
120 * wait for before starting execution.
121 */
122 uint32_t number_of_dependencies;
123
124 /**
125 * Array of dependencies which need to be met before
126 * execution can start.
127 */
128 struct amdgpu_cs_fence *dependencies;
129
130 /** Number of IBs to submit in the field ibs. */
131 uint32_t number_of_ibs;
132
133 /**
134 * IBs to submit. Those IBs will be submit together as single entity
135 */
136 struct amdgpu_cs_ib_info *ibs;
137
138 /**
139 * The returned sequence number for the command submission
140 */
141 uint64_t seq_no;
142
143 /**
144 * The fence information
145 */
146 struct amdgpu_cs_fence_info fence_info;
147 };
148
149
150 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
151 uint32_t ip_type,
152 uint32_t ring,
153 struct radv_winsys_sem_info *sem_info);
154 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
155 struct radv_amdgpu_cs_request *request,
156 struct radv_winsys_sem_info *sem_info);
157
158 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx,
159 struct radv_amdgpu_fence *fence,
160 struct radv_amdgpu_cs_request *req)
161 {
162 fence->fence.context = ctx->ctx;
163 fence->fence.ip_type = req->ip_type;
164 fence->fence.ip_instance = req->ip_instance;
165 fence->fence.ring = req->ring;
166 fence->fence.fence = req->seq_no;
167 fence->user_ptr = (volatile uint64_t*)(ctx->fence_map + req->ip_type * MAX_RINGS_PER_TYPE + req->ring);
168 }
169
170 static struct radeon_winsys_fence *radv_amdgpu_create_fence()
171 {
172 struct radv_amdgpu_fence *fence = calloc(1, sizeof(struct radv_amdgpu_fence));
173 fence->fence.fence = UINT64_MAX;
174 return (struct radeon_winsys_fence*)fence;
175 }
176
177 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence *_fence)
178 {
179 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
180 free(fence);
181 }
182
183 static void radv_amdgpu_reset_fence(struct radeon_winsys_fence *_fence)
184 {
185 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
186 fence->fence.fence = UINT64_MAX;
187 }
188
189 static void radv_amdgpu_signal_fence(struct radeon_winsys_fence *_fence)
190 {
191 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
192 fence->fence.fence = 0;
193 }
194
195 static bool radv_amdgpu_is_fence_waitable(struct radeon_winsys_fence *_fence)
196 {
197 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
198 return fence->fence.fence < UINT64_MAX;
199 }
200
201 static bool radv_amdgpu_fence_wait(struct radeon_winsys *_ws,
202 struct radeon_winsys_fence *_fence,
203 bool absolute,
204 uint64_t timeout)
205 {
206 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
207 unsigned flags = absolute ? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE : 0;
208 int r;
209 uint32_t expired = 0;
210
211 /* Special casing 0 and UINT64_MAX so that they work without user_ptr/fence.ctx */
212 if (fence->fence.fence == UINT64_MAX)
213 return false;
214
215 if (fence->fence.fence == 0)
216 return true;
217
218 if (fence->user_ptr) {
219 if (*fence->user_ptr >= fence->fence.fence)
220 return true;
221 if (!absolute && !timeout)
222 return false;
223 }
224
225 /* Now use the libdrm query. */
226 r = amdgpu_cs_query_fence_status(&fence->fence,
227 timeout,
228 flags,
229 &expired);
230
231 if (r) {
232 fprintf(stderr, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
233 return false;
234 }
235
236 if (expired)
237 return true;
238
239 return false;
240 }
241
242
243 static bool radv_amdgpu_fences_wait(struct radeon_winsys *_ws,
244 struct radeon_winsys_fence *const *_fences,
245 uint32_t fence_count,
246 bool wait_all,
247 uint64_t timeout)
248 {
249 struct amdgpu_cs_fence *fences = malloc(sizeof(struct amdgpu_cs_fence) * fence_count);
250 int r;
251 uint32_t expired = 0, first = 0;
252
253 if (!fences)
254 return false;
255
256 for (uint32_t i = 0; i < fence_count; ++i)
257 fences[i] = ((struct radv_amdgpu_fence *)_fences[i])->fence;
258
259 /* Now use the libdrm query. */
260 r = amdgpu_cs_wait_fences(fences, fence_count, wait_all,
261 timeout, &expired, &first);
262
263 free(fences);
264 if (r) {
265 fprintf(stderr, "amdgpu: amdgpu_cs_wait_fences failed.\n");
266 return false;
267 }
268
269 if (expired)
270 return true;
271
272 return false;
273 }
274
275 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
276 {
277 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs);
278
279 if (cs->ib_buffer)
280 cs->ws->base.buffer_destroy(cs->ib_buffer);
281 else
282 free(cs->base.buf);
283
284 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
285 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
286
287 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
288 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
289 free(rcs->buf);
290 }
291
292 free(cs->old_cs_buffers);
293 free(cs->old_ib_buffers);
294 free(cs->virtual_buffers);
295 free(cs->virtual_buffer_hash_table);
296 free(cs->handles);
297 free(cs);
298 }
299
300 static void radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
301 enum ring_type ring_type)
302 {
303 for (int i = 0; i < ARRAY_SIZE(cs->buffer_hash_table); ++i)
304 cs->buffer_hash_table[i] = -1;
305
306 cs->hw_ip = ring_to_hw_ip(ring_type);
307 }
308
309 static struct radeon_cmdbuf *
310 radv_amdgpu_cs_create(struct radeon_winsys *ws,
311 enum ring_type ring_type)
312 {
313 struct radv_amdgpu_cs *cs;
314 uint32_t ib_size = 20 * 1024 * 4;
315 cs = calloc(1, sizeof(struct radv_amdgpu_cs));
316 if (!cs)
317 return NULL;
318
319 cs->ws = radv_amdgpu_winsys(ws);
320 radv_amdgpu_init_cs(cs, ring_type);
321
322 if (cs->ws->use_ib_bos) {
323 cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
324 RADEON_DOMAIN_GTT,
325 RADEON_FLAG_CPU_ACCESS |
326 RADEON_FLAG_NO_INTERPROCESS_SHARING |
327 RADEON_FLAG_READ_ONLY,
328 RADV_BO_PRIORITY_CS);
329 if (!cs->ib_buffer) {
330 free(cs);
331 return NULL;
332 }
333
334 cs->ib_mapped = ws->buffer_map(cs->ib_buffer);
335 if (!cs->ib_mapped) {
336 ws->buffer_destroy(cs->ib_buffer);
337 free(cs);
338 return NULL;
339 }
340
341 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
342 cs->base.buf = (uint32_t *)cs->ib_mapped;
343 cs->base.max_dw = ib_size / 4 - 4;
344 cs->ib_size_ptr = &cs->ib.size;
345 cs->ib.size = 0;
346
347 ws->cs_add_buffer(&cs->base, cs->ib_buffer);
348 } else {
349 cs->base.buf = malloc(16384);
350 cs->base.max_dw = 4096;
351 if (!cs->base.buf) {
352 free(cs);
353 return NULL;
354 }
355 }
356
357 return &cs->base;
358 }
359
360 static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
361 {
362 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
363
364 if (cs->failed) {
365 cs->base.cdw = 0;
366 return;
367 }
368
369 if (!cs->ws->use_ib_bos) {
370 const uint64_t limit_dws = 0xffff8;
371 uint64_t ib_dws = MAX2(cs->base.cdw + min_size,
372 MIN2(cs->base.max_dw * 2, limit_dws));
373
374 /* The total ib size cannot exceed limit_dws dwords. */
375 if (ib_dws > limit_dws)
376 {
377 /* The maximum size in dwords has been reached,
378 * try to allocate a new one.
379 */
380 cs->old_cs_buffers =
381 realloc(cs->old_cs_buffers,
382 (cs->num_old_cs_buffers + 1) * sizeof(*cs->old_cs_buffers));
383 if (!cs->old_cs_buffers) {
384 cs->failed = true;
385 cs->base.cdw = 0;
386 return;
387 }
388
389 /* Store the current one for submitting it later. */
390 cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw;
391 cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw = cs->base.max_dw;
392 cs->old_cs_buffers[cs->num_old_cs_buffers].buf = cs->base.buf;
393 cs->num_old_cs_buffers++;
394
395 /* Reset the cs, it will be re-allocated below. */
396 cs->base.cdw = 0;
397 cs->base.buf = NULL;
398
399 /* Re-compute the number of dwords to allocate. */
400 ib_dws = MAX2(cs->base.cdw + min_size,
401 MIN2(cs->base.max_dw * 2, limit_dws));
402 if (ib_dws > limit_dws) {
403 fprintf(stderr, "amdgpu: Too high number of "
404 "dwords to allocate\n");
405 cs->failed = true;
406 return;
407 }
408 }
409
410 uint32_t *new_buf = realloc(cs->base.buf, ib_dws * 4);
411 if (new_buf) {
412 cs->base.buf = new_buf;
413 cs->base.max_dw = ib_dws;
414 } else {
415 cs->failed = true;
416 cs->base.cdw = 0;
417 }
418 return;
419 }
420
421 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2);
422
423 /* max that fits in the chain size field. */
424 ib_size = MIN2(ib_size, 0xfffff);
425
426 while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
427 radeon_emit(&cs->base, 0xffff1000);
428
429 *cs->ib_size_ptr |= cs->base.cdw + 4;
430
431 if (cs->num_old_ib_buffers == cs->max_num_old_ib_buffers) {
432 cs->max_num_old_ib_buffers = MAX2(1, cs->max_num_old_ib_buffers * 2);
433 cs->old_ib_buffers = realloc(cs->old_ib_buffers,
434 cs->max_num_old_ib_buffers * sizeof(void*));
435 }
436
437 cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
438
439 cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
440 RADEON_DOMAIN_GTT,
441 RADEON_FLAG_CPU_ACCESS |
442 RADEON_FLAG_NO_INTERPROCESS_SHARING |
443 RADEON_FLAG_READ_ONLY,
444 RADV_BO_PRIORITY_CS);
445
446 if (!cs->ib_buffer) {
447 cs->base.cdw = 0;
448 cs->failed = true;
449 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
450 }
451
452 cs->ib_mapped = cs->ws->base.buffer_map(cs->ib_buffer);
453 if (!cs->ib_mapped) {
454 cs->ws->base.buffer_destroy(cs->ib_buffer);
455 cs->base.cdw = 0;
456 cs->failed = true;
457 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
458 }
459
460 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
461
462 radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
463 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va);
464 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va >> 32);
465 radeon_emit(&cs->base, S_3F2_CHAIN(1) | S_3F2_VALID(1));
466
467 cs->ib_size_ptr = cs->base.buf + cs->base.cdw - 1;
468
469 cs->base.buf = (uint32_t *)cs->ib_mapped;
470 cs->base.cdw = 0;
471 cs->base.max_dw = ib_size / 4 - 4;
472
473 }
474
475 static bool radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
476 {
477 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
478
479 if (cs->ws->use_ib_bos) {
480 while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
481 radeon_emit(&cs->base, 0xffff1000);
482
483 *cs->ib_size_ptr |= cs->base.cdw;
484
485 cs->is_chained = false;
486 }
487
488 return !cs->failed;
489 }
490
491 static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
492 {
493 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
494 cs->base.cdw = 0;
495 cs->failed = false;
496
497 for (unsigned i = 0; i < cs->num_buffers; ++i) {
498 unsigned hash = cs->handles[i].bo_handle &
499 (ARRAY_SIZE(cs->buffer_hash_table) - 1);
500 cs->buffer_hash_table[hash] = -1;
501 }
502
503 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
504 unsigned hash = ((uintptr_t)cs->virtual_buffers[i] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
505 cs->virtual_buffer_hash_table[hash] = -1;
506 }
507
508 cs->num_buffers = 0;
509 cs->num_virtual_buffers = 0;
510
511 if (cs->ws->use_ib_bos) {
512 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
513
514 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
515 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
516
517 cs->num_old_ib_buffers = 0;
518 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
519 cs->ib_size_ptr = &cs->ib.size;
520 cs->ib.size = 0;
521 } else {
522 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
523 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
524 free(rcs->buf);
525 }
526
527 free(cs->old_cs_buffers);
528 cs->old_cs_buffers = NULL;
529 cs->num_old_cs_buffers = 0;
530 }
531 }
532
533 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs *cs,
534 uint32_t bo)
535 {
536 unsigned hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
537 int index = cs->buffer_hash_table[hash];
538
539 if (index == -1)
540 return -1;
541
542 if (cs->handles[index].bo_handle == bo)
543 return index;
544
545 for (unsigned i = 0; i < cs->num_buffers; ++i) {
546 if (cs->handles[i].bo_handle == bo) {
547 cs->buffer_hash_table[hash] = i;
548 return i;
549 }
550 }
551
552 return -1;
553 }
554
555 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
556 uint32_t bo, uint8_t priority)
557 {
558 unsigned hash;
559 int index = radv_amdgpu_cs_find_buffer(cs, bo);
560
561 if (index != -1 || cs->failed)
562 return;
563
564 if (cs->num_buffers == cs->max_num_buffers) {
565 unsigned new_count = MAX2(1, cs->max_num_buffers * 2);
566 struct drm_amdgpu_bo_list_entry *new_entries =
567 realloc(cs->handles, new_count * sizeof(struct drm_amdgpu_bo_list_entry));
568 if (new_entries) {
569 cs->max_num_buffers = new_count;
570 cs->handles = new_entries;
571 } else {
572 cs->failed = true;
573 return;
574 }
575 }
576
577 cs->handles[cs->num_buffers].bo_handle = bo;
578 cs->handles[cs->num_buffers].bo_priority = priority;
579
580 hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
581 cs->buffer_hash_table[hash] = cs->num_buffers;
582
583 ++cs->num_buffers;
584 }
585
586 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
587 struct radeon_winsys_bo *bo)
588 {
589 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
590 unsigned hash = ((uintptr_t)bo >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
591
592
593 if (!cs->virtual_buffer_hash_table) {
594 cs->virtual_buffer_hash_table = malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE * sizeof(int));
595 for (int i = 0; i < VIRTUAL_BUFFER_HASH_TABLE_SIZE; ++i)
596 cs->virtual_buffer_hash_table[i] = -1;
597 }
598
599 if (cs->virtual_buffer_hash_table[hash] >= 0) {
600 int idx = cs->virtual_buffer_hash_table[hash];
601 if (cs->virtual_buffers[idx] == bo) {
602 return;
603 }
604 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
605 if (cs->virtual_buffers[i] == bo) {
606 cs->virtual_buffer_hash_table[hash] = i;
607 return;
608 }
609 }
610 }
611
612 if(cs->max_num_virtual_buffers <= cs->num_virtual_buffers) {
613 cs->max_num_virtual_buffers = MAX2(2, cs->max_num_virtual_buffers * 2);
614 cs->virtual_buffers = realloc(cs->virtual_buffers, sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * cs->max_num_virtual_buffers);
615 }
616
617 cs->virtual_buffers[cs->num_virtual_buffers] = bo;
618
619 cs->virtual_buffer_hash_table[hash] = cs->num_virtual_buffers;
620 ++cs->num_virtual_buffers;
621
622 }
623
624 static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf *_cs,
625 struct radeon_winsys_bo *_bo)
626 {
627 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
628 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
629
630 if (bo->is_virtual) {
631 radv_amdgpu_cs_add_virtual_buffer(_cs, _bo);
632 return;
633 }
634
635 if (bo->base.is_local)
636 return;
637
638 radv_amdgpu_cs_add_buffer_internal(cs, bo->bo_handle, bo->priority);
639 }
640
641 static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent,
642 struct radeon_cmdbuf *_child)
643 {
644 struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
645 struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
646
647 for (unsigned i = 0; i < child->num_buffers; ++i) {
648 radv_amdgpu_cs_add_buffer_internal(parent,
649 child->handles[i].bo_handle,
650 child->handles[i].bo_priority);
651 }
652
653 for (unsigned i = 0; i < child->num_virtual_buffers; ++i) {
654 radv_amdgpu_cs_add_buffer(&parent->base, child->virtual_buffers[i]);
655 }
656
657 if (parent->ws->use_ib_bos) {
658 if (parent->base.cdw + 4 > parent->base.max_dw)
659 radv_amdgpu_cs_grow(&parent->base, 4);
660
661 radeon_emit(&parent->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
662 radeon_emit(&parent->base, child->ib.ib_mc_address);
663 radeon_emit(&parent->base, child->ib.ib_mc_address >> 32);
664 radeon_emit(&parent->base, child->ib.size);
665 } else {
666 if (parent->base.cdw + child->base.cdw > parent->base.max_dw)
667 radv_amdgpu_cs_grow(&parent->base, child->base.cdw);
668
669 memcpy(parent->base.buf + parent->base.cdw, child->base.buf, 4 * child->base.cdw);
670 parent->base.cdw += child->base.cdw;
671 }
672 }
673
674 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
675 struct radeon_cmdbuf **cs_array,
676 unsigned count,
677 struct radv_amdgpu_winsys_bo **extra_bo_array,
678 unsigned num_extra_bo,
679 struct radeon_cmdbuf *extra_cs,
680 const struct radv_winsys_bo_list *radv_bo_list,
681 uint32_t *bo_list)
682 {
683 int r = 0;
684
685 if (ws->debug_all_bos) {
686 struct radv_amdgpu_winsys_bo *bo;
687 struct drm_amdgpu_bo_list_entry *handles;
688 unsigned num = 0;
689
690 pthread_mutex_lock(&ws->global_bo_list_lock);
691
692 handles = malloc(sizeof(handles[0]) * ws->num_buffers);
693 if (!handles) {
694 pthread_mutex_unlock(&ws->global_bo_list_lock);
695 return -ENOMEM;
696 }
697
698 LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
699 assert(num < ws->num_buffers);
700 handles[num].bo_handle = bo->bo_handle;
701 handles[num].bo_priority = bo->priority;
702 num++;
703 }
704
705 r = amdgpu_bo_list_create_raw(ws->dev, ws->num_buffers,
706 handles, bo_list);
707 free(handles);
708 pthread_mutex_unlock(&ws->global_bo_list_lock);
709 } else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list &&
710 !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
711 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
712 if (cs->num_buffers == 0) {
713 *bo_list = 0;
714 return 0;
715 }
716 r = amdgpu_bo_list_create_raw(ws->dev, cs->num_buffers, cs->handles,
717 bo_list);
718 } else {
719 unsigned total_buffer_count = num_extra_bo;
720 unsigned unique_bo_count = num_extra_bo;
721 for (unsigned i = 0; i < count; ++i) {
722 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[i];
723 total_buffer_count += cs->num_buffers;
724 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j)
725 total_buffer_count += radv_amdgpu_winsys_bo(cs->virtual_buffers[j])->bo_count;
726 }
727
728 if (extra_cs) {
729 total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
730 }
731
732 if (radv_bo_list) {
733 total_buffer_count += radv_bo_list->count;
734 }
735
736 if (total_buffer_count == 0) {
737 *bo_list = 0;
738 return 0;
739 }
740 struct drm_amdgpu_bo_list_entry *handles = malloc(sizeof(struct drm_amdgpu_bo_list_entry) * total_buffer_count);
741 if (!handles)
742 return -ENOMEM;
743
744 for (unsigned i = 0; i < num_extra_bo; i++) {
745 handles[i].bo_handle = extra_bo_array[i]->bo_handle;
746 handles[i].bo_priority = extra_bo_array[i]->priority;
747 }
748
749 for (unsigned i = 0; i < count + !!extra_cs; ++i) {
750 struct radv_amdgpu_cs *cs;
751
752 if (i == count)
753 cs = (struct radv_amdgpu_cs*)extra_cs;
754 else
755 cs = (struct radv_amdgpu_cs*)cs_array[i];
756
757 if (!cs->num_buffers)
758 continue;
759
760 if (unique_bo_count == 0 && !cs->num_virtual_buffers) {
761 memcpy(handles, cs->handles, cs->num_buffers * sizeof(struct drm_amdgpu_bo_list_entry));
762 unique_bo_count = cs->num_buffers;
763 continue;
764 }
765 int unique_bo_so_far = unique_bo_count;
766 for (unsigned j = 0; j < cs->num_buffers; ++j) {
767 bool found = false;
768 for (unsigned k = 0; k < unique_bo_so_far; ++k) {
769 if (handles[k].bo_handle == cs->handles[j].bo_handle) {
770 found = true;
771 break;
772 }
773 }
774 if (!found) {
775 handles[unique_bo_count] = cs->handles[j];
776 ++unique_bo_count;
777 }
778 }
779 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j) {
780 struct radv_amdgpu_winsys_bo *virtual_bo = radv_amdgpu_winsys_bo(cs->virtual_buffers[j]);
781 for(unsigned k = 0; k < virtual_bo->bo_count; ++k) {
782 struct radv_amdgpu_winsys_bo *bo = virtual_bo->bos[k];
783 bool found = false;
784 for (unsigned m = 0; m < unique_bo_count; ++m) {
785 if (handles[m].bo_handle == bo->bo_handle) {
786 found = true;
787 break;
788 }
789 }
790 if (!found) {
791 handles[unique_bo_count].bo_handle = bo->bo_handle;
792 handles[unique_bo_count].bo_priority = bo->priority;
793 ++unique_bo_count;
794 }
795 }
796 }
797 }
798
799 if (radv_bo_list) {
800 unsigned unique_bo_so_far = unique_bo_count;
801 for (unsigned i = 0; i < radv_bo_list->count; ++i) {
802 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(radv_bo_list->bos[i]);
803 bool found = false;
804 for (unsigned j = 0; j < unique_bo_so_far; ++j) {
805 if (bo->bo_handle == handles[j].bo_handle) {
806 found = true;
807 break;
808 }
809 }
810 if (!found) {
811 handles[unique_bo_count].bo_handle = bo->bo_handle;
812 handles[unique_bo_count].bo_priority = bo->priority;
813 ++unique_bo_count;
814 }
815 }
816 }
817
818 if (unique_bo_count > 0) {
819 r = amdgpu_bo_list_create_raw(ws->dev, unique_bo_count, handles,
820 bo_list);
821 } else {
822 *bo_list = 0;
823 }
824
825 free(handles);
826 }
827
828 return r;
829 }
830
831 static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_ctx *ctx, int ip_type, int ring)
832 {
833 struct amdgpu_cs_fence_info ret = {0};
834 if (ctx->fence_map) {
835 ret.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
836 ret.offset = (ip_type * MAX_RINGS_PER_TYPE + ring) * sizeof(uint64_t);
837 }
838 return ret;
839 }
840
841 static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
842 struct radv_amdgpu_cs_request *request)
843 {
844 radv_amdgpu_request_to_fence(ctx,
845 &ctx->last_submission[request->ip_type][request->ring],
846 request);
847 }
848
849 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
850 int queue_idx,
851 struct radv_winsys_sem_info *sem_info,
852 const struct radv_winsys_bo_list *radv_bo_list,
853 struct radeon_cmdbuf **cs_array,
854 unsigned cs_count,
855 struct radeon_cmdbuf *initial_preamble_cs,
856 struct radeon_cmdbuf *continue_preamble_cs,
857 struct radeon_winsys_fence *_fence)
858 {
859 int r;
860 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
861 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
862 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
863 uint32_t bo_list;
864 struct radv_amdgpu_cs_request request = {0};
865 struct amdgpu_cs_ib_info ibs[2];
866 unsigned number_of_ibs = 1;
867
868 for (unsigned i = cs_count; i--;) {
869 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
870
871 if (cs->is_chained) {
872 *cs->ib_size_ptr -= 4;
873 cs->is_chained = false;
874 }
875
876 if (i + 1 < cs_count) {
877 struct radv_amdgpu_cs *next = radv_amdgpu_cs(cs_array[i + 1]);
878 assert(cs->base.cdw + 4 <= cs->base.max_dw);
879
880 cs->is_chained = true;
881 *cs->ib_size_ptr += 4;
882
883 cs->base.buf[cs->base.cdw + 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
884 cs->base.buf[cs->base.cdw + 1] = next->ib.ib_mc_address;
885 cs->base.buf[cs->base.cdw + 2] = next->ib.ib_mc_address >> 32;
886 cs->base.buf[cs->base.cdw + 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next->ib.size;
887 }
888 }
889
890 /* Create a buffer object list. */
891 r = radv_amdgpu_create_bo_list(cs0->ws, cs_array, cs_count, NULL, 0,
892 initial_preamble_cs, radv_bo_list,
893 &bo_list);
894 if (r) {
895 fprintf(stderr, "amdgpu: buffer list creation failed for the "
896 "chained submission(%d)\n", r);
897 return r;
898 }
899
900 /* Configure the CS request. */
901 if (initial_preamble_cs) {
902 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
903 ibs[1] = cs0->ib;
904 number_of_ibs++;
905 } else {
906 ibs[0] = cs0->ib;
907 }
908
909 request.ip_type = cs0->hw_ip;
910 request.ring = queue_idx;
911 request.number_of_ibs = number_of_ibs;
912 request.ibs = ibs;
913 request.resources = bo_list;
914 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
915
916 /* Submit the CS. */
917 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
918 if (r) {
919 if (r == -ENOMEM)
920 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
921 else
922 fprintf(stderr, "amdgpu: The CS has been rejected, "
923 "see dmesg for more information.\n");
924 }
925
926 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
927
928 if (r)
929 return r;
930
931 if (fence)
932 radv_amdgpu_request_to_fence(ctx, fence, &request);
933
934 radv_assign_last_submit(ctx, &request);
935
936 return 0;
937 }
938
939 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
940 int queue_idx,
941 struct radv_winsys_sem_info *sem_info,
942 const struct radv_winsys_bo_list *radv_bo_list,
943 struct radeon_cmdbuf **cs_array,
944 unsigned cs_count,
945 struct radeon_cmdbuf *initial_preamble_cs,
946 struct radeon_cmdbuf *continue_preamble_cs,
947 struct radeon_winsys_fence *_fence)
948 {
949 int r;
950 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
951 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
952 uint32_t bo_list;
953 struct radv_amdgpu_cs_request request = {};
954 struct amdgpu_cs_ib_info *ibs;
955 struct radv_amdgpu_cs *cs0;
956 unsigned number_of_ibs;
957
958 assert(cs_count);
959 cs0 = radv_amdgpu_cs(cs_array[0]);
960
961 /* Compute the number of IBs for this submit. */
962 number_of_ibs = cs_count + !!initial_preamble_cs;
963
964 /* Create a buffer object list. */
965 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[0], cs_count, NULL, 0,
966 initial_preamble_cs, radv_bo_list,
967 &bo_list);
968 if (r) {
969 fprintf(stderr, "amdgpu: buffer list creation failed "
970 "for the fallback submission (%d)\n", r);
971 return r;
972 }
973
974 ibs = malloc(number_of_ibs * sizeof(*ibs));
975 if (!ibs) {
976 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
977 return -ENOMEM;
978 }
979
980 /* Configure the CS request. */
981 if (initial_preamble_cs)
982 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
983
984 for (unsigned i = 0; i < cs_count; i++) {
985 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
986
987 ibs[i + !!initial_preamble_cs] = cs->ib;
988
989 if (cs->is_chained) {
990 *cs->ib_size_ptr -= 4;
991 cs->is_chained = false;
992 }
993 }
994
995 request.ip_type = cs0->hw_ip;
996 request.ring = queue_idx;
997 request.resources = bo_list;
998 request.number_of_ibs = number_of_ibs;
999 request.ibs = ibs;
1000 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
1001
1002 /* Submit the CS. */
1003 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
1004 if (r) {
1005 if (r == -ENOMEM)
1006 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1007 else
1008 fprintf(stderr, "amdgpu: The CS has been rejected, "
1009 "see dmesg for more information.\n");
1010 }
1011
1012 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
1013 free(ibs);
1014
1015 if (r)
1016 return r;
1017
1018 if (fence)
1019 radv_amdgpu_request_to_fence(ctx, fence, &request);
1020
1021 radv_assign_last_submit(ctx, &request);
1022
1023 return 0;
1024 }
1025
1026 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
1027 int queue_idx,
1028 struct radv_winsys_sem_info *sem_info,
1029 const struct radv_winsys_bo_list *radv_bo_list,
1030 struct radeon_cmdbuf **cs_array,
1031 unsigned cs_count,
1032 struct radeon_cmdbuf *initial_preamble_cs,
1033 struct radeon_cmdbuf *continue_preamble_cs,
1034 struct radeon_winsys_fence *_fence)
1035 {
1036 int r;
1037 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1038 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
1039 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
1040 struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
1041 uint32_t bo_list;
1042 struct radv_amdgpu_cs_request request;
1043 uint32_t pad_word = 0xffff1000U;
1044 bool emit_signal_sem = sem_info->cs_emit_signal;
1045
1046 if (radv_amdgpu_winsys(ws)->info.chip_class == GFX6)
1047 pad_word = 0x80000000;
1048
1049 assert(cs_count);
1050
1051 for (unsigned i = 0; i < cs_count;) {
1052 struct amdgpu_cs_ib_info *ibs;
1053 struct radeon_winsys_bo **bos;
1054 struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
1055 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
1056 unsigned number_of_ibs;
1057 uint32_t *ptr;
1058 unsigned cnt = 0;
1059 unsigned size = 0;
1060 unsigned pad_words = 0;
1061
1062 /* Compute the number of IBs for this submit. */
1063 number_of_ibs = cs->num_old_cs_buffers + 1;
1064
1065 ibs = malloc(number_of_ibs * sizeof(*ibs));
1066 if (!ibs)
1067 return -ENOMEM;
1068
1069 bos = malloc(number_of_ibs * sizeof(*bos));
1070 if (!bos) {
1071 free(ibs);
1072 return -ENOMEM;
1073 }
1074
1075 if (number_of_ibs > 1) {
1076 /* Special path when the maximum size in dwords has
1077 * been reached because we need to handle more than one
1078 * IB per submit.
1079 */
1080 struct radeon_cmdbuf **new_cs_array;
1081 unsigned idx = 0;
1082
1083 new_cs_array = malloc(cs->num_old_cs_buffers *
1084 sizeof(*new_cs_array));
1085 assert(new_cs_array);
1086
1087 for (unsigned j = 0; j < cs->num_old_cs_buffers; j++)
1088 new_cs_array[idx++] = &cs->old_cs_buffers[j];
1089 new_cs_array[idx++] = cs_array[i];
1090
1091 for (unsigned j = 0; j < number_of_ibs; j++) {
1092 struct radeon_cmdbuf *rcs = new_cs_array[j];
1093 bool needs_preamble = preamble_cs && j == 0;
1094 unsigned size = 0;
1095
1096 if (needs_preamble)
1097 size += preamble_cs->cdw;
1098 size += rcs->cdw;
1099
1100 assert(size < 0xffff8);
1101
1102 while (!size || (size & 7)) {
1103 size++;
1104 pad_words++;
1105 }
1106
1107 bos[j] = ws->buffer_create(ws, 4 * size, 4096,
1108 RADEON_DOMAIN_GTT,
1109 RADEON_FLAG_CPU_ACCESS |
1110 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1111 RADEON_FLAG_READ_ONLY,
1112 RADV_BO_PRIORITY_CS);
1113 ptr = ws->buffer_map(bos[j]);
1114
1115 if (needs_preamble) {
1116 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1117 ptr += preamble_cs->cdw;
1118 }
1119
1120 memcpy(ptr, rcs->buf, 4 * rcs->cdw);
1121 ptr += rcs->cdw;
1122
1123 for (unsigned k = 0; k < pad_words; ++k)
1124 *ptr++ = pad_word;
1125
1126 ibs[j].size = size;
1127 ibs[j].ib_mc_address = radv_buffer_get_va(bos[j]);
1128 ibs[j].flags = 0;
1129 }
1130
1131 cnt++;
1132 free(new_cs_array);
1133 } else {
1134 if (preamble_cs)
1135 size += preamble_cs->cdw;
1136
1137 while (i + cnt < cs_count && 0xffff8 - size >= radv_amdgpu_cs(cs_array[i + cnt])->base.cdw) {
1138 size += radv_amdgpu_cs(cs_array[i + cnt])->base.cdw;
1139 ++cnt;
1140 }
1141
1142 while (!size || (size & 7)) {
1143 size++;
1144 pad_words++;
1145 }
1146 assert(cnt);
1147
1148 bos[0] = ws->buffer_create(ws, 4 * size, 4096,
1149 RADEON_DOMAIN_GTT,
1150 RADEON_FLAG_CPU_ACCESS |
1151 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1152 RADEON_FLAG_READ_ONLY,
1153 RADV_BO_PRIORITY_CS);
1154 ptr = ws->buffer_map(bos[0]);
1155
1156 if (preamble_cs) {
1157 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1158 ptr += preamble_cs->cdw;
1159 }
1160
1161 for (unsigned j = 0; j < cnt; ++j) {
1162 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + j]);
1163 memcpy(ptr, cs->base.buf, 4 * cs->base.cdw);
1164 ptr += cs->base.cdw;
1165
1166 }
1167
1168 for (unsigned j = 0; j < pad_words; ++j)
1169 *ptr++ = pad_word;
1170
1171 ibs[0].size = size;
1172 ibs[0].ib_mc_address = radv_buffer_get_va(bos[0]);
1173 ibs[0].flags = 0;
1174 }
1175
1176 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt,
1177 (struct radv_amdgpu_winsys_bo **)bos,
1178 number_of_ibs, preamble_cs,
1179 radv_bo_list, &bo_list);
1180 if (r) {
1181 fprintf(stderr, "amdgpu: buffer list creation failed "
1182 "for the sysmem submission (%d)\n", r);
1183 free(ibs);
1184 free(bos);
1185 return r;
1186 }
1187
1188 memset(&request, 0, sizeof(request));
1189
1190 request.ip_type = cs0->hw_ip;
1191 request.ring = queue_idx;
1192 request.resources = bo_list;
1193 request.number_of_ibs = number_of_ibs;
1194 request.ibs = ibs;
1195 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
1196
1197 sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
1198 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
1199 if (r) {
1200 if (r == -ENOMEM)
1201 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1202 else
1203 fprintf(stderr, "amdgpu: The CS has been rejected, "
1204 "see dmesg for more information.\n");
1205 }
1206
1207 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
1208
1209 for (unsigned j = 0; j < number_of_ibs; j++) {
1210 ws->buffer_destroy(bos[j]);
1211 }
1212
1213 free(ibs);
1214 free(bos);
1215
1216 if (r)
1217 return r;
1218
1219 i += cnt;
1220 }
1221 if (fence)
1222 radv_amdgpu_request_to_fence(ctx, fence, &request);
1223
1224 radv_assign_last_submit(ctx, &request);
1225
1226 return 0;
1227 }
1228
1229 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
1230 int queue_idx,
1231 struct radeon_cmdbuf **cs_array,
1232 unsigned cs_count,
1233 struct radeon_cmdbuf *initial_preamble_cs,
1234 struct radeon_cmdbuf *continue_preamble_cs,
1235 struct radv_winsys_sem_info *sem_info,
1236 const struct radv_winsys_bo_list *bo_list,
1237 bool can_patch,
1238 struct radeon_winsys_fence *_fence)
1239 {
1240 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
1241 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1242 int ret;
1243
1244 assert(sem_info);
1245 if (!cs->ws->use_ib_bos) {
1246 ret = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, bo_list, cs_array,
1247 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1248 } else if (can_patch) {
1249 ret = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, bo_list, cs_array,
1250 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1251 } else {
1252 ret = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, bo_list, cs_array,
1253 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1254 }
1255
1256 radv_amdgpu_signal_sems(ctx, cs->hw_ip, queue_idx, sem_info);
1257 return ret;
1258 }
1259
1260 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
1261 {
1262 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1263 void *ret = NULL;
1264
1265 if (!cs->ib_buffer)
1266 return NULL;
1267 for (unsigned i = 0; i <= cs->num_old_ib_buffers; ++i) {
1268 struct radv_amdgpu_winsys_bo *bo;
1269
1270 bo = (struct radv_amdgpu_winsys_bo*)
1271 (i == cs->num_old_ib_buffers ? cs->ib_buffer : cs->old_ib_buffers[i]);
1272 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1273 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0)
1274 return (char *)ret + (addr - bo->base.va);
1275 }
1276 }
1277 if(cs->ws->debug_all_bos) {
1278 pthread_mutex_lock(&cs->ws->global_bo_list_lock);
1279 list_for_each_entry(struct radv_amdgpu_winsys_bo, bo,
1280 &cs->ws->global_bo_list, global_list_item) {
1281 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1282 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0) {
1283 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1284 return (char *)ret + (addr - bo->base.va);
1285 }
1286 }
1287 }
1288 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1289 }
1290 return ret;
1291 }
1292
1293 static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs,
1294 FILE* file,
1295 const int *trace_ids, int trace_id_count)
1296 {
1297 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1298 void *ib = cs->base.buf;
1299 int num_dw = cs->base.cdw;
1300
1301 if (cs->ws->use_ib_bos) {
1302 ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
1303 num_dw = cs->ib.size;
1304 }
1305 assert(ib);
1306 ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB",
1307 cs->ws->info.chip_class, radv_amdgpu_winsys_get_cpu_addr, cs);
1308 }
1309
1310 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority)
1311 {
1312 switch (radv_priority) {
1313 case RADEON_CTX_PRIORITY_REALTIME:
1314 return AMDGPU_CTX_PRIORITY_VERY_HIGH;
1315 case RADEON_CTX_PRIORITY_HIGH:
1316 return AMDGPU_CTX_PRIORITY_HIGH;
1317 case RADEON_CTX_PRIORITY_MEDIUM:
1318 return AMDGPU_CTX_PRIORITY_NORMAL;
1319 case RADEON_CTX_PRIORITY_LOW:
1320 return AMDGPU_CTX_PRIORITY_LOW;
1321 default:
1322 unreachable("Invalid context priority");
1323 }
1324 }
1325
1326 static VkResult radv_amdgpu_ctx_create(struct radeon_winsys *_ws,
1327 enum radeon_ctx_priority priority,
1328 struct radeon_winsys_ctx **rctx)
1329 {
1330 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1331 struct radv_amdgpu_ctx *ctx = CALLOC_STRUCT(radv_amdgpu_ctx);
1332 uint32_t amdgpu_priority = radv_to_amdgpu_priority(priority);
1333 VkResult result;
1334 int r;
1335
1336 if (!ctx)
1337 return VK_ERROR_OUT_OF_HOST_MEMORY;
1338
1339 r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
1340 if (r && r == -EACCES) {
1341 result = VK_ERROR_NOT_PERMITTED_EXT;
1342 goto error_create;
1343 } else if (r) {
1344 fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r);
1345 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1346 goto error_create;
1347 }
1348 ctx->ws = ws;
1349
1350 assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
1351 ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
1352 RADEON_DOMAIN_GTT,
1353 RADEON_FLAG_CPU_ACCESS |
1354 RADEON_FLAG_NO_INTERPROCESS_SHARING,
1355 RADV_BO_PRIORITY_CS);
1356 if (ctx->fence_bo)
1357 ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
1358 if (ctx->fence_map)
1359 memset(ctx->fence_map, 0, 4096);
1360
1361 *rctx = (struct radeon_winsys_ctx *)ctx;
1362 return VK_SUCCESS;
1363 error_create:
1364 FREE(ctx);
1365 return result;
1366 }
1367
1368 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
1369 {
1370 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1371 ctx->ws->base.buffer_destroy(ctx->fence_bo);
1372 amdgpu_cs_ctx_free(ctx->ctx);
1373 FREE(ctx);
1374 }
1375
1376 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
1377 enum ring_type ring_type, int ring_index)
1378 {
1379 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1380 int ip_type = ring_to_hw_ip(ring_type);
1381
1382 if (ctx->last_submission[ip_type][ring_index].fence.fence) {
1383 uint32_t expired;
1384 int ret = amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index].fence,
1385 1000000000ull, 0, &expired);
1386
1387 if (ret || !expired)
1388 return false;
1389 }
1390
1391 return true;
1392 }
1393
1394 static struct radeon_winsys_sem *radv_amdgpu_create_sem(struct radeon_winsys *_ws)
1395 {
1396 struct amdgpu_cs_fence *sem = CALLOC_STRUCT(amdgpu_cs_fence);
1397 if (!sem)
1398 return NULL;
1399
1400 return (struct radeon_winsys_sem *)sem;
1401 }
1402
1403 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem *_sem)
1404 {
1405 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)_sem;
1406 FREE(sem);
1407 }
1408
1409 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
1410 uint32_t ip_type,
1411 uint32_t ring,
1412 struct radv_winsys_sem_info *sem_info)
1413 {
1414 for (unsigned i = 0; i < sem_info->signal.sem_count; i++) {
1415 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)(sem_info->signal.sem)[i];
1416
1417 if (sem->context)
1418 return -EINVAL;
1419
1420 *sem = ctx->last_submission[ip_type][ring].fence;
1421 }
1422 return 0;
1423 }
1424
1425 static struct drm_amdgpu_cs_chunk_sem *radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts *counts,
1426 struct drm_amdgpu_cs_chunk *chunk, int chunk_id)
1427 {
1428 struct drm_amdgpu_cs_chunk_sem *syncobj = malloc(sizeof(struct drm_amdgpu_cs_chunk_sem) * counts->syncobj_count);
1429 if (!syncobj)
1430 return NULL;
1431
1432 for (unsigned i = 0; i < counts->syncobj_count; i++) {
1433 struct drm_amdgpu_cs_chunk_sem *sem = &syncobj[i];
1434 sem->handle = counts->syncobj[i];
1435 }
1436
1437 chunk->chunk_id = chunk_id;
1438 chunk->length_dw = sizeof(struct drm_amdgpu_cs_chunk_sem) / 4 * counts->syncobj_count;
1439 chunk->chunk_data = (uint64_t)(uintptr_t)syncobj;
1440 return syncobj;
1441 }
1442
1443 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
1444 struct radv_amdgpu_cs_request *request,
1445 struct radv_winsys_sem_info *sem_info)
1446 {
1447 int r;
1448 int num_chunks;
1449 int size;
1450 bool user_fence;
1451 struct drm_amdgpu_cs_chunk *chunks;
1452 struct drm_amdgpu_cs_chunk_data *chunk_data;
1453 struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
1454 struct drm_amdgpu_cs_chunk_sem *wait_syncobj = NULL, *signal_syncobj = NULL;
1455 int i;
1456 struct amdgpu_cs_fence *sem;
1457
1458 user_fence = (request->fence_info.handle != NULL);
1459 size = request->number_of_ibs + (user_fence ? 2 : 1) + 3;
1460
1461 chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
1462
1463 size = request->number_of_ibs + (user_fence ? 1 : 0);
1464
1465 chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
1466
1467 num_chunks = request->number_of_ibs;
1468 for (i = 0; i < request->number_of_ibs; i++) {
1469 struct amdgpu_cs_ib_info *ib;
1470 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
1471 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
1472 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1473
1474 ib = &request->ibs[i];
1475
1476 chunk_data[i].ib_data._pad = 0;
1477 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
1478 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
1479 chunk_data[i].ib_data.ip_type = request->ip_type;
1480 chunk_data[i].ib_data.ip_instance = request->ip_instance;
1481 chunk_data[i].ib_data.ring = request->ring;
1482 chunk_data[i].ib_data.flags = ib->flags;
1483 }
1484
1485 if (user_fence) {
1486 i = num_chunks++;
1487
1488 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
1489 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
1490 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1491
1492 amdgpu_cs_chunk_fence_info_to_data(&request->fence_info,
1493 &chunk_data[i]);
1494 }
1495
1496 if (sem_info->wait.syncobj_count && sem_info->cs_emit_wait) {
1497 wait_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->wait,
1498 &chunks[num_chunks],
1499 AMDGPU_CHUNK_ID_SYNCOBJ_IN);
1500 if (!wait_syncobj) {
1501 r = -ENOMEM;
1502 goto error_out;
1503 }
1504 num_chunks++;
1505
1506 if (sem_info->wait.sem_count == 0)
1507 sem_info->cs_emit_wait = false;
1508
1509 }
1510
1511 if (sem_info->wait.sem_count && sem_info->cs_emit_wait) {
1512 sem_dependencies = alloca(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_info->wait.sem_count);
1513 int sem_count = 0;
1514
1515 for (unsigned j = 0; j < sem_info->wait.sem_count; j++) {
1516 sem = (struct amdgpu_cs_fence *)sem_info->wait.sem[j];
1517 if (!sem->context)
1518 continue;
1519 struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
1520
1521 amdgpu_cs_chunk_fence_to_dep(sem, dep);
1522
1523 sem->context = NULL;
1524 }
1525 i = num_chunks++;
1526
1527 /* dependencies chunk */
1528 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
1529 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
1530 chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
1531
1532 sem_info->cs_emit_wait = false;
1533 }
1534
1535 if (sem_info->signal.syncobj_count && sem_info->cs_emit_signal) {
1536 signal_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->signal,
1537 &chunks[num_chunks],
1538 AMDGPU_CHUNK_ID_SYNCOBJ_OUT);
1539 if (!signal_syncobj) {
1540 r = -ENOMEM;
1541 goto error_out;
1542 }
1543 num_chunks++;
1544 }
1545
1546 r = amdgpu_cs_submit_raw2(ctx->ws->dev,
1547 ctx->ctx,
1548 request->resources,
1549 num_chunks,
1550 chunks,
1551 &request->seq_no);
1552 error_out:
1553 free(wait_syncobj);
1554 free(signal_syncobj);
1555 return r;
1556 }
1557
1558 static int radv_amdgpu_create_syncobj(struct radeon_winsys *_ws,
1559 uint32_t *handle)
1560 {
1561 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1562 return amdgpu_cs_create_syncobj(ws->dev, handle);
1563 }
1564
1565 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys *_ws,
1566 uint32_t handle)
1567 {
1568 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1569 amdgpu_cs_destroy_syncobj(ws->dev, handle);
1570 }
1571
1572 static void radv_amdgpu_reset_syncobj(struct radeon_winsys *_ws,
1573 uint32_t handle)
1574 {
1575 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1576 amdgpu_cs_syncobj_reset(ws->dev, &handle, 1);
1577 }
1578
1579 static void radv_amdgpu_signal_syncobj(struct radeon_winsys *_ws,
1580 uint32_t handle)
1581 {
1582 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1583 amdgpu_cs_syncobj_signal(ws->dev, &handle, 1);
1584 }
1585
1586 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys *_ws, const uint32_t *handles,
1587 uint32_t handle_count, bool wait_all, uint64_t timeout)
1588 {
1589 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1590 uint32_t tmp;
1591
1592 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1593 timeout = MIN2(timeout, INT64_MAX);
1594
1595 int ret = amdgpu_cs_syncobj_wait(ws->dev, (uint32_t*)handles, handle_count, timeout,
1596 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT |
1597 (wait_all ? DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL : 0),
1598 &tmp);
1599 if (ret == 0) {
1600 return true;
1601 } else if (ret == -ETIME) {
1602 return false;
1603 } else {
1604 fprintf(stderr, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno);
1605 return false;
1606 }
1607 }
1608
1609 static int radv_amdgpu_export_syncobj(struct radeon_winsys *_ws,
1610 uint32_t syncobj,
1611 int *fd)
1612 {
1613 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1614
1615 return amdgpu_cs_export_syncobj(ws->dev, syncobj, fd);
1616 }
1617
1618 static int radv_amdgpu_import_syncobj(struct radeon_winsys *_ws,
1619 int fd,
1620 uint32_t *syncobj)
1621 {
1622 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1623
1624 return amdgpu_cs_import_syncobj(ws->dev, fd, syncobj);
1625 }
1626
1627
1628 static int radv_amdgpu_export_syncobj_to_sync_file(struct radeon_winsys *_ws,
1629 uint32_t syncobj,
1630 int *fd)
1631 {
1632 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1633
1634 return amdgpu_cs_syncobj_export_sync_file(ws->dev, syncobj, fd);
1635 }
1636
1637 static int radv_amdgpu_import_syncobj_from_sync_file(struct radeon_winsys *_ws,
1638 uint32_t syncobj,
1639 int fd)
1640 {
1641 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1642
1643 return amdgpu_cs_syncobj_import_sync_file(ws->dev, syncobj, fd);
1644 }
1645
1646 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
1647 {
1648 ws->base.ctx_create = radv_amdgpu_ctx_create;
1649 ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
1650 ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
1651 ws->base.cs_create = radv_amdgpu_cs_create;
1652 ws->base.cs_destroy = radv_amdgpu_cs_destroy;
1653 ws->base.cs_grow = radv_amdgpu_cs_grow;
1654 ws->base.cs_finalize = radv_amdgpu_cs_finalize;
1655 ws->base.cs_reset = radv_amdgpu_cs_reset;
1656 ws->base.cs_add_buffer = radv_amdgpu_cs_add_buffer;
1657 ws->base.cs_execute_secondary = radv_amdgpu_cs_execute_secondary;
1658 ws->base.cs_submit = radv_amdgpu_winsys_cs_submit;
1659 ws->base.cs_dump = radv_amdgpu_winsys_cs_dump;
1660 ws->base.create_fence = radv_amdgpu_create_fence;
1661 ws->base.destroy_fence = radv_amdgpu_destroy_fence;
1662 ws->base.reset_fence = radv_amdgpu_reset_fence;
1663 ws->base.signal_fence = radv_amdgpu_signal_fence;
1664 ws->base.is_fence_waitable = radv_amdgpu_is_fence_waitable;
1665 ws->base.create_sem = radv_amdgpu_create_sem;
1666 ws->base.destroy_sem = radv_amdgpu_destroy_sem;
1667 ws->base.create_syncobj = radv_amdgpu_create_syncobj;
1668 ws->base.destroy_syncobj = radv_amdgpu_destroy_syncobj;
1669 ws->base.reset_syncobj = radv_amdgpu_reset_syncobj;
1670 ws->base.signal_syncobj = radv_amdgpu_signal_syncobj;
1671 ws->base.wait_syncobj = radv_amdgpu_wait_syncobj;
1672 ws->base.export_syncobj = radv_amdgpu_export_syncobj;
1673 ws->base.import_syncobj = radv_amdgpu_import_syncobj;
1674 ws->base.export_syncobj_to_sync_file = radv_amdgpu_export_syncobj_to_sync_file;
1675 ws->base.import_syncobj_from_sync_file = radv_amdgpu_import_syncobj_from_sync_file;
1676 ws->base.fence_wait = radv_amdgpu_fence_wait;
1677 ws->base.fences_wait = radv_amdgpu_fences_wait;
1678 }