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radv/winsys: pass the buffer list via the CS ioctl for less CPU overhead
[mesa.git] / src / amd / vulkan / winsys / amdgpu / radv_amdgpu_cs.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdlib.h>
26 #include <amdgpu.h>
27 #include "drm-uapi/amdgpu_drm.h"
28 #include <assert.h>
29 #include <pthread.h>
30 #include <errno.h>
31
32 #include "util/u_memory.h"
33 #include "ac_debug.h"
34 #include "radv_radeon_winsys.h"
35 #include "radv_amdgpu_cs.h"
36 #include "radv_amdgpu_bo.h"
37 #include "sid.h"
38
39
40 enum {
41 VIRTUAL_BUFFER_HASH_TABLE_SIZE = 1024
42 };
43
44 struct radv_amdgpu_cs {
45 struct radeon_cmdbuf base;
46 struct radv_amdgpu_winsys *ws;
47
48 struct amdgpu_cs_ib_info ib;
49
50 struct radeon_winsys_bo *ib_buffer;
51 uint8_t *ib_mapped;
52 unsigned max_num_buffers;
53 unsigned num_buffers;
54 struct drm_amdgpu_bo_list_entry *handles;
55
56 struct radeon_winsys_bo **old_ib_buffers;
57 unsigned num_old_ib_buffers;
58 unsigned max_num_old_ib_buffers;
59 unsigned *ib_size_ptr;
60 VkResult status;
61 bool is_chained;
62
63 int buffer_hash_table[1024];
64 unsigned hw_ip;
65
66 unsigned num_virtual_buffers;
67 unsigned max_num_virtual_buffers;
68 struct radeon_winsys_bo **virtual_buffers;
69 int *virtual_buffer_hash_table;
70
71 /* For chips that don't support chaining. */
72 struct radeon_cmdbuf *old_cs_buffers;
73 unsigned num_old_cs_buffers;
74 };
75
76 static inline struct radv_amdgpu_cs *
77 radv_amdgpu_cs(struct radeon_cmdbuf *base)
78 {
79 return (struct radv_amdgpu_cs*)base;
80 }
81
82 static int ring_to_hw_ip(enum ring_type ring)
83 {
84 switch (ring) {
85 case RING_GFX:
86 return AMDGPU_HW_IP_GFX;
87 case RING_DMA:
88 return AMDGPU_HW_IP_DMA;
89 case RING_COMPUTE:
90 return AMDGPU_HW_IP_COMPUTE;
91 default:
92 unreachable("unsupported ring");
93 }
94 }
95
96 struct radv_amdgpu_cs_request {
97 /** Specify flags with additional information */
98 uint64_t flags;
99
100 /** Specify HW IP block type to which to send the IB. */
101 unsigned ip_type;
102
103 /** IP instance index if there are several IPs of the same type. */
104 unsigned ip_instance;
105
106 /**
107 * Specify ring index of the IP. We could have several rings
108 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
109 */
110 uint32_t ring;
111
112 /**
113 * BO list handles used by this request.
114 */
115 struct drm_amdgpu_bo_list_entry *handles;
116 uint32_t num_handles;
117
118 /**
119 * Number of dependencies this Command submission needs to
120 * wait for before starting execution.
121 */
122 uint32_t number_of_dependencies;
123
124 /**
125 * Array of dependencies which need to be met before
126 * execution can start.
127 */
128 struct amdgpu_cs_fence *dependencies;
129
130 /** Number of IBs to submit in the field ibs. */
131 uint32_t number_of_ibs;
132
133 /**
134 * IBs to submit. Those IBs will be submit together as single entity
135 */
136 struct amdgpu_cs_ib_info *ibs;
137
138 /**
139 * The returned sequence number for the command submission
140 */
141 uint64_t seq_no;
142
143 /**
144 * The fence information
145 */
146 struct amdgpu_cs_fence_info fence_info;
147 };
148
149
150 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
151 uint32_t ip_type,
152 uint32_t ring,
153 struct radv_winsys_sem_info *sem_info);
154 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
155 struct radv_amdgpu_cs_request *request,
156 struct radv_winsys_sem_info *sem_info);
157
158 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx,
159 struct radv_amdgpu_fence *fence,
160 struct radv_amdgpu_cs_request *req)
161 {
162 fence->fence.context = ctx->ctx;
163 fence->fence.ip_type = req->ip_type;
164 fence->fence.ip_instance = req->ip_instance;
165 fence->fence.ring = req->ring;
166 fence->fence.fence = req->seq_no;
167 fence->user_ptr = (volatile uint64_t*)(ctx->fence_map + req->ip_type * MAX_RINGS_PER_TYPE + req->ring);
168 }
169
170 static struct radeon_winsys_fence *radv_amdgpu_create_fence()
171 {
172 struct radv_amdgpu_fence *fence = calloc(1, sizeof(struct radv_amdgpu_fence));
173 fence->fence.fence = UINT64_MAX;
174 return (struct radeon_winsys_fence*)fence;
175 }
176
177 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence *_fence)
178 {
179 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
180 free(fence);
181 }
182
183 static void radv_amdgpu_reset_fence(struct radeon_winsys_fence *_fence)
184 {
185 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
186 fence->fence.fence = UINT64_MAX;
187 }
188
189 static void radv_amdgpu_signal_fence(struct radeon_winsys_fence *_fence)
190 {
191 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
192 fence->fence.fence = 0;
193 }
194
195 static bool radv_amdgpu_is_fence_waitable(struct radeon_winsys_fence *_fence)
196 {
197 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
198 return fence->fence.fence < UINT64_MAX;
199 }
200
201 static bool radv_amdgpu_fence_wait(struct radeon_winsys *_ws,
202 struct radeon_winsys_fence *_fence,
203 bool absolute,
204 uint64_t timeout)
205 {
206 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
207 unsigned flags = absolute ? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE : 0;
208 int r;
209 uint32_t expired = 0;
210
211 /* Special casing 0 and UINT64_MAX so that they work without user_ptr/fence.ctx */
212 if (fence->fence.fence == UINT64_MAX)
213 return false;
214
215 if (fence->fence.fence == 0)
216 return true;
217
218 if (fence->user_ptr) {
219 if (*fence->user_ptr >= fence->fence.fence)
220 return true;
221 if (!absolute && !timeout)
222 return false;
223 }
224
225 /* Now use the libdrm query. */
226 r = amdgpu_cs_query_fence_status(&fence->fence,
227 timeout,
228 flags,
229 &expired);
230
231 if (r) {
232 fprintf(stderr, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
233 return false;
234 }
235
236 if (expired)
237 return true;
238
239 return false;
240 }
241
242
243 static bool radv_amdgpu_fences_wait(struct radeon_winsys *_ws,
244 struct radeon_winsys_fence *const *_fences,
245 uint32_t fence_count,
246 bool wait_all,
247 uint64_t timeout)
248 {
249 struct amdgpu_cs_fence *fences = malloc(sizeof(struct amdgpu_cs_fence) * fence_count);
250 int r;
251 uint32_t expired = 0, first = 0;
252
253 if (!fences)
254 return false;
255
256 for (uint32_t i = 0; i < fence_count; ++i)
257 fences[i] = ((struct radv_amdgpu_fence *)_fences[i])->fence;
258
259 /* Now use the libdrm query. */
260 r = amdgpu_cs_wait_fences(fences, fence_count, wait_all,
261 timeout, &expired, &first);
262
263 free(fences);
264 if (r) {
265 fprintf(stderr, "amdgpu: amdgpu_cs_wait_fences failed.\n");
266 return false;
267 }
268
269 if (expired)
270 return true;
271
272 return false;
273 }
274
275 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
276 {
277 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs);
278
279 if (cs->ib_buffer)
280 cs->ws->base.buffer_destroy(cs->ib_buffer);
281 else
282 free(cs->base.buf);
283
284 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
285 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
286
287 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
288 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
289 free(rcs->buf);
290 }
291
292 free(cs->old_cs_buffers);
293 free(cs->old_ib_buffers);
294 free(cs->virtual_buffers);
295 free(cs->virtual_buffer_hash_table);
296 free(cs->handles);
297 free(cs);
298 }
299
300 static void radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
301 enum ring_type ring_type)
302 {
303 for (int i = 0; i < ARRAY_SIZE(cs->buffer_hash_table); ++i)
304 cs->buffer_hash_table[i] = -1;
305
306 cs->hw_ip = ring_to_hw_ip(ring_type);
307 }
308
309 static struct radeon_cmdbuf *
310 radv_amdgpu_cs_create(struct radeon_winsys *ws,
311 enum ring_type ring_type)
312 {
313 struct radv_amdgpu_cs *cs;
314 uint32_t ib_size = 20 * 1024 * 4;
315 cs = calloc(1, sizeof(struct radv_amdgpu_cs));
316 if (!cs)
317 return NULL;
318
319 cs->ws = radv_amdgpu_winsys(ws);
320 radv_amdgpu_init_cs(cs, ring_type);
321
322 if (cs->ws->use_ib_bos) {
323 cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
324 RADEON_DOMAIN_GTT,
325 RADEON_FLAG_CPU_ACCESS |
326 RADEON_FLAG_NO_INTERPROCESS_SHARING |
327 RADEON_FLAG_READ_ONLY,
328 RADV_BO_PRIORITY_CS);
329 if (!cs->ib_buffer) {
330 free(cs);
331 return NULL;
332 }
333
334 cs->ib_mapped = ws->buffer_map(cs->ib_buffer);
335 if (!cs->ib_mapped) {
336 ws->buffer_destroy(cs->ib_buffer);
337 free(cs);
338 return NULL;
339 }
340
341 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
342 cs->base.buf = (uint32_t *)cs->ib_mapped;
343 cs->base.max_dw = ib_size / 4 - 4;
344 cs->ib_size_ptr = &cs->ib.size;
345 cs->ib.size = 0;
346
347 ws->cs_add_buffer(&cs->base, cs->ib_buffer);
348 } else {
349 cs->base.buf = malloc(16384);
350 cs->base.max_dw = 4096;
351 if (!cs->base.buf) {
352 free(cs);
353 return NULL;
354 }
355 }
356
357 return &cs->base;
358 }
359
360 static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
361 {
362 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
363
364 if (cs->status != VK_SUCCESS) {
365 cs->base.cdw = 0;
366 return;
367 }
368
369 if (!cs->ws->use_ib_bos) {
370 const uint64_t limit_dws = 0xffff8;
371 uint64_t ib_dws = MAX2(cs->base.cdw + min_size,
372 MIN2(cs->base.max_dw * 2, limit_dws));
373
374 /* The total ib size cannot exceed limit_dws dwords. */
375 if (ib_dws > limit_dws)
376 {
377 /* The maximum size in dwords has been reached,
378 * try to allocate a new one.
379 */
380 cs->old_cs_buffers =
381 realloc(cs->old_cs_buffers,
382 (cs->num_old_cs_buffers + 1) * sizeof(*cs->old_cs_buffers));
383 if (!cs->old_cs_buffers) {
384 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
385 cs->base.cdw = 0;
386 return;
387 }
388
389 /* Store the current one for submitting it later. */
390 cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw;
391 cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw = cs->base.max_dw;
392 cs->old_cs_buffers[cs->num_old_cs_buffers].buf = cs->base.buf;
393 cs->num_old_cs_buffers++;
394
395 /* Reset the cs, it will be re-allocated below. */
396 cs->base.cdw = 0;
397 cs->base.buf = NULL;
398
399 /* Re-compute the number of dwords to allocate. */
400 ib_dws = MAX2(cs->base.cdw + min_size,
401 MIN2(cs->base.max_dw * 2, limit_dws));
402 if (ib_dws > limit_dws) {
403 fprintf(stderr, "amdgpu: Too high number of "
404 "dwords to allocate\n");
405 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
406 return;
407 }
408 }
409
410 uint32_t *new_buf = realloc(cs->base.buf, ib_dws * 4);
411 if (new_buf) {
412 cs->base.buf = new_buf;
413 cs->base.max_dw = ib_dws;
414 } else {
415 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
416 cs->base.cdw = 0;
417 }
418 return;
419 }
420
421 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2);
422
423 /* max that fits in the chain size field. */
424 ib_size = MIN2(ib_size, 0xfffff);
425
426 while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
427 radeon_emit(&cs->base, PKT3_NOP_PAD);
428
429 *cs->ib_size_ptr |= cs->base.cdw + 4;
430
431 if (cs->num_old_ib_buffers == cs->max_num_old_ib_buffers) {
432 cs->max_num_old_ib_buffers = MAX2(1, cs->max_num_old_ib_buffers * 2);
433 cs->old_ib_buffers = realloc(cs->old_ib_buffers,
434 cs->max_num_old_ib_buffers * sizeof(void*));
435 }
436
437 cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
438
439 cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
440 RADEON_DOMAIN_GTT,
441 RADEON_FLAG_CPU_ACCESS |
442 RADEON_FLAG_NO_INTERPROCESS_SHARING |
443 RADEON_FLAG_READ_ONLY,
444 RADV_BO_PRIORITY_CS);
445
446 if (!cs->ib_buffer) {
447 cs->base.cdw = 0;
448 cs->status = VK_ERROR_OUT_OF_DEVICE_MEMORY;
449 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
450 }
451
452 cs->ib_mapped = cs->ws->base.buffer_map(cs->ib_buffer);
453 if (!cs->ib_mapped) {
454 cs->ws->base.buffer_destroy(cs->ib_buffer);
455 cs->base.cdw = 0;
456
457 /* VK_ERROR_MEMORY_MAP_FAILED is not valid for vkEndCommandBuffer. */
458 cs->status = VK_ERROR_OUT_OF_DEVICE_MEMORY;
459 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
460 }
461
462 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
463
464 radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
465 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va);
466 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va >> 32);
467 radeon_emit(&cs->base, S_3F2_CHAIN(1) | S_3F2_VALID(1));
468
469 cs->ib_size_ptr = cs->base.buf + cs->base.cdw - 1;
470
471 cs->base.buf = (uint32_t *)cs->ib_mapped;
472 cs->base.cdw = 0;
473 cs->base.max_dw = ib_size / 4 - 4;
474
475 }
476
477 static VkResult radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
478 {
479 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
480
481 if (cs->ws->use_ib_bos) {
482 while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
483 radeon_emit(&cs->base, PKT3_NOP_PAD);
484
485 *cs->ib_size_ptr |= cs->base.cdw;
486
487 cs->is_chained = false;
488 }
489
490 return cs->status;
491 }
492
493 static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
494 {
495 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
496 cs->base.cdw = 0;
497 cs->status = VK_SUCCESS;
498
499 for (unsigned i = 0; i < cs->num_buffers; ++i) {
500 unsigned hash = cs->handles[i].bo_handle &
501 (ARRAY_SIZE(cs->buffer_hash_table) - 1);
502 cs->buffer_hash_table[hash] = -1;
503 }
504
505 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
506 unsigned hash = ((uintptr_t)cs->virtual_buffers[i] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
507 cs->virtual_buffer_hash_table[hash] = -1;
508 }
509
510 cs->num_buffers = 0;
511 cs->num_virtual_buffers = 0;
512
513 if (cs->ws->use_ib_bos) {
514 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
515
516 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
517 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
518
519 cs->num_old_ib_buffers = 0;
520 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
521 cs->ib_size_ptr = &cs->ib.size;
522 cs->ib.size = 0;
523 } else {
524 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
525 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
526 free(rcs->buf);
527 }
528
529 free(cs->old_cs_buffers);
530 cs->old_cs_buffers = NULL;
531 cs->num_old_cs_buffers = 0;
532 }
533 }
534
535 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs *cs,
536 uint32_t bo)
537 {
538 unsigned hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
539 int index = cs->buffer_hash_table[hash];
540
541 if (index == -1)
542 return -1;
543
544 if (cs->handles[index].bo_handle == bo)
545 return index;
546
547 for (unsigned i = 0; i < cs->num_buffers; ++i) {
548 if (cs->handles[i].bo_handle == bo) {
549 cs->buffer_hash_table[hash] = i;
550 return i;
551 }
552 }
553
554 return -1;
555 }
556
557 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
558 uint32_t bo, uint8_t priority)
559 {
560 unsigned hash;
561 int index = radv_amdgpu_cs_find_buffer(cs, bo);
562
563 if (index != -1 || cs->status != VK_SUCCESS)
564 return;
565
566 if (cs->num_buffers == cs->max_num_buffers) {
567 unsigned new_count = MAX2(1, cs->max_num_buffers * 2);
568 struct drm_amdgpu_bo_list_entry *new_entries =
569 realloc(cs->handles, new_count * sizeof(struct drm_amdgpu_bo_list_entry));
570 if (new_entries) {
571 cs->max_num_buffers = new_count;
572 cs->handles = new_entries;
573 } else {
574 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
575 return;
576 }
577 }
578
579 cs->handles[cs->num_buffers].bo_handle = bo;
580 cs->handles[cs->num_buffers].bo_priority = priority;
581
582 hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
583 cs->buffer_hash_table[hash] = cs->num_buffers;
584
585 ++cs->num_buffers;
586 }
587
588 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
589 struct radeon_winsys_bo *bo)
590 {
591 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
592 unsigned hash = ((uintptr_t)bo >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
593
594
595 if (!cs->virtual_buffer_hash_table) {
596 cs->virtual_buffer_hash_table = malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE * sizeof(int));
597 for (int i = 0; i < VIRTUAL_BUFFER_HASH_TABLE_SIZE; ++i)
598 cs->virtual_buffer_hash_table[i] = -1;
599 }
600
601 if (cs->virtual_buffer_hash_table[hash] >= 0) {
602 int idx = cs->virtual_buffer_hash_table[hash];
603 if (cs->virtual_buffers[idx] == bo) {
604 return;
605 }
606 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
607 if (cs->virtual_buffers[i] == bo) {
608 cs->virtual_buffer_hash_table[hash] = i;
609 return;
610 }
611 }
612 }
613
614 if(cs->max_num_virtual_buffers <= cs->num_virtual_buffers) {
615 cs->max_num_virtual_buffers = MAX2(2, cs->max_num_virtual_buffers * 2);
616 cs->virtual_buffers = realloc(cs->virtual_buffers, sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * cs->max_num_virtual_buffers);
617 }
618
619 cs->virtual_buffers[cs->num_virtual_buffers] = bo;
620
621 cs->virtual_buffer_hash_table[hash] = cs->num_virtual_buffers;
622 ++cs->num_virtual_buffers;
623
624 }
625
626 static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf *_cs,
627 struct radeon_winsys_bo *_bo)
628 {
629 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
630 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
631
632 if (bo->is_virtual) {
633 radv_amdgpu_cs_add_virtual_buffer(_cs, _bo);
634 return;
635 }
636
637 if (bo->base.is_local)
638 return;
639
640 radv_amdgpu_cs_add_buffer_internal(cs, bo->bo_handle, bo->priority);
641 }
642
643 static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent,
644 struct radeon_cmdbuf *_child)
645 {
646 struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
647 struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
648
649 for (unsigned i = 0; i < child->num_buffers; ++i) {
650 radv_amdgpu_cs_add_buffer_internal(parent,
651 child->handles[i].bo_handle,
652 child->handles[i].bo_priority);
653 }
654
655 for (unsigned i = 0; i < child->num_virtual_buffers; ++i) {
656 radv_amdgpu_cs_add_buffer(&parent->base, child->virtual_buffers[i]);
657 }
658
659 if (parent->ws->use_ib_bos) {
660 if (parent->base.cdw + 4 > parent->base.max_dw)
661 radv_amdgpu_cs_grow(&parent->base, 4);
662
663 radeon_emit(&parent->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
664 radeon_emit(&parent->base, child->ib.ib_mc_address);
665 radeon_emit(&parent->base, child->ib.ib_mc_address >> 32);
666 radeon_emit(&parent->base, child->ib.size);
667 } else {
668 if (parent->base.cdw + child->base.cdw > parent->base.max_dw)
669 radv_amdgpu_cs_grow(&parent->base, child->base.cdw);
670
671 memcpy(parent->base.buf + parent->base.cdw, child->base.buf, 4 * child->base.cdw);
672 parent->base.cdw += child->base.cdw;
673 }
674 }
675
676 static int
677 radv_amdgpu_get_bo_list(struct radv_amdgpu_winsys *ws,
678 struct radeon_cmdbuf **cs_array,
679 unsigned count,
680 struct radv_amdgpu_winsys_bo **extra_bo_array,
681 unsigned num_extra_bo,
682 struct radeon_cmdbuf *extra_cs,
683 const struct radv_winsys_bo_list *radv_bo_list,
684 unsigned *rnum_handles,
685 struct drm_amdgpu_bo_list_entry **rhandles)
686 {
687 struct drm_amdgpu_bo_list_entry *handles = NULL;
688 unsigned num_handles = 0;
689 int r = 0;
690
691 if (ws->debug_all_bos) {
692 struct radv_amdgpu_winsys_bo *bo;
693
694 pthread_mutex_lock(&ws->global_bo_list_lock);
695
696 handles = malloc(sizeof(handles[0]) * ws->num_buffers);
697 if (!handles) {
698 pthread_mutex_unlock(&ws->global_bo_list_lock);
699 return -ENOMEM;
700 }
701
702 LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
703 assert(num_handles < ws->num_buffers);
704 handles[num_handles].bo_handle = bo->bo_handle;
705 handles[num_handles].bo_priority = bo->priority;
706 num_handles++;
707 }
708
709 pthread_mutex_unlock(&ws->global_bo_list_lock);
710 } else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list &&
711 !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
712 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
713 if (cs->num_buffers == 0)
714 return 0;
715
716 handles = malloc(sizeof(handles[0]) * cs->num_buffers);
717 if (!handles)
718 return -ENOMEM;
719
720 memcpy(handles, cs->handles,
721 sizeof(handles[0]) * cs->num_buffers);
722 num_handles = cs->num_buffers;
723 } else {
724 unsigned total_buffer_count = num_extra_bo;
725 num_handles = num_extra_bo;
726 for (unsigned i = 0; i < count; ++i) {
727 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[i];
728 total_buffer_count += cs->num_buffers;
729 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j)
730 total_buffer_count += radv_amdgpu_winsys_bo(cs->virtual_buffers[j])->bo_count;
731 }
732
733 if (extra_cs) {
734 total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
735 }
736
737 if (radv_bo_list) {
738 total_buffer_count += radv_bo_list->count;
739 }
740
741 if (total_buffer_count == 0)
742 return 0;
743
744 handles = malloc(sizeof(handles[0]) * total_buffer_count);
745 if (!handles)
746 return -ENOMEM;
747
748 for (unsigned i = 0; i < num_extra_bo; i++) {
749 handles[i].bo_handle = extra_bo_array[i]->bo_handle;
750 handles[i].bo_priority = extra_bo_array[i]->priority;
751 }
752
753 for (unsigned i = 0; i < count + !!extra_cs; ++i) {
754 struct radv_amdgpu_cs *cs;
755
756 if (i == count)
757 cs = (struct radv_amdgpu_cs*)extra_cs;
758 else
759 cs = (struct radv_amdgpu_cs*)cs_array[i];
760
761 if (!cs->num_buffers)
762 continue;
763
764 if (num_handles == 0 && !cs->num_virtual_buffers) {
765 memcpy(handles, cs->handles, cs->num_buffers * sizeof(struct drm_amdgpu_bo_list_entry));
766 num_handles = cs->num_buffers;
767 continue;
768 }
769 int unique_bo_so_far = num_handles;
770 for (unsigned j = 0; j < cs->num_buffers; ++j) {
771 bool found = false;
772 for (unsigned k = 0; k < unique_bo_so_far; ++k) {
773 if (handles[k].bo_handle == cs->handles[j].bo_handle) {
774 found = true;
775 break;
776 }
777 }
778 if (!found) {
779 handles[num_handles] = cs->handles[j];
780 ++num_handles;
781 }
782 }
783 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j) {
784 struct radv_amdgpu_winsys_bo *virtual_bo = radv_amdgpu_winsys_bo(cs->virtual_buffers[j]);
785 for(unsigned k = 0; k < virtual_bo->bo_count; ++k) {
786 struct radv_amdgpu_winsys_bo *bo = virtual_bo->bos[k];
787 bool found = false;
788 for (unsigned m = 0; m < num_handles; ++m) {
789 if (handles[m].bo_handle == bo->bo_handle) {
790 found = true;
791 break;
792 }
793 }
794 if (!found) {
795 handles[num_handles].bo_handle = bo->bo_handle;
796 handles[num_handles].bo_priority = bo->priority;
797 ++num_handles;
798 }
799 }
800 }
801 }
802
803 if (radv_bo_list) {
804 unsigned unique_bo_so_far = num_handles;
805 for (unsigned i = 0; i < radv_bo_list->count; ++i) {
806 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(radv_bo_list->bos[i]);
807 bool found = false;
808 for (unsigned j = 0; j < unique_bo_so_far; ++j) {
809 if (bo->bo_handle == handles[j].bo_handle) {
810 found = true;
811 break;
812 }
813 }
814 if (!found) {
815 handles[num_handles].bo_handle = bo->bo_handle;
816 handles[num_handles].bo_priority = bo->priority;
817 ++num_handles;
818 }
819 }
820 }
821 }
822
823 *rhandles = handles;
824 *rnum_handles = num_handles;
825
826 return r;
827 }
828
829 static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_ctx *ctx, int ip_type, int ring)
830 {
831 struct amdgpu_cs_fence_info ret = {0};
832 if (ctx->fence_map) {
833 ret.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
834 ret.offset = (ip_type * MAX_RINGS_PER_TYPE + ring) * sizeof(uint64_t);
835 }
836 return ret;
837 }
838
839 static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
840 struct radv_amdgpu_cs_request *request)
841 {
842 radv_amdgpu_request_to_fence(ctx,
843 &ctx->last_submission[request->ip_type][request->ring],
844 request);
845 }
846
847 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
848 int queue_idx,
849 struct radv_winsys_sem_info *sem_info,
850 const struct radv_winsys_bo_list *radv_bo_list,
851 struct radeon_cmdbuf **cs_array,
852 unsigned cs_count,
853 struct radeon_cmdbuf *initial_preamble_cs,
854 struct radeon_cmdbuf *continue_preamble_cs,
855 struct radeon_winsys_fence *_fence)
856 {
857 int r;
858 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
859 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
860 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
861 struct drm_amdgpu_bo_list_entry *handles = NULL;
862 struct radv_amdgpu_cs_request request = {0};
863 struct amdgpu_cs_ib_info ibs[2];
864 unsigned number_of_ibs = 1;
865 unsigned num_handles = 0;
866
867 for (unsigned i = cs_count; i--;) {
868 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
869
870 if (cs->is_chained) {
871 *cs->ib_size_ptr -= 4;
872 cs->is_chained = false;
873 }
874
875 if (i + 1 < cs_count) {
876 struct radv_amdgpu_cs *next = radv_amdgpu_cs(cs_array[i + 1]);
877 assert(cs->base.cdw + 4 <= cs->base.max_dw);
878
879 cs->is_chained = true;
880 *cs->ib_size_ptr += 4;
881
882 cs->base.buf[cs->base.cdw + 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
883 cs->base.buf[cs->base.cdw + 1] = next->ib.ib_mc_address;
884 cs->base.buf[cs->base.cdw + 2] = next->ib.ib_mc_address >> 32;
885 cs->base.buf[cs->base.cdw + 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next->ib.size;
886 }
887 }
888
889 /* Get the BO list. */
890 r = radv_amdgpu_get_bo_list(cs0->ws, cs_array, cs_count, NULL, 0,
891 initial_preamble_cs, radv_bo_list,
892 &num_handles, &handles);
893 if (r)
894 return r;
895
896 /* Configure the CS request. */
897 if (initial_preamble_cs) {
898 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
899 ibs[1] = cs0->ib;
900 number_of_ibs++;
901 } else {
902 ibs[0] = cs0->ib;
903 }
904
905 request.ip_type = cs0->hw_ip;
906 request.ring = queue_idx;
907 request.number_of_ibs = number_of_ibs;
908 request.ibs = ibs;
909 request.handles = handles;
910 request.num_handles = num_handles;
911 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
912
913 /* Submit the CS. */
914 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
915 if (r) {
916 if (r == -ENOMEM)
917 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
918 else
919 fprintf(stderr, "amdgpu: The CS has been rejected, "
920 "see dmesg for more information.\n");
921 }
922
923 free(request.handles);
924
925 if (r)
926 return r;
927
928 if (fence)
929 radv_amdgpu_request_to_fence(ctx, fence, &request);
930
931 radv_assign_last_submit(ctx, &request);
932
933 return 0;
934 }
935
936 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
937 int queue_idx,
938 struct radv_winsys_sem_info *sem_info,
939 const struct radv_winsys_bo_list *radv_bo_list,
940 struct radeon_cmdbuf **cs_array,
941 unsigned cs_count,
942 struct radeon_cmdbuf *initial_preamble_cs,
943 struct radeon_cmdbuf *continue_preamble_cs,
944 struct radeon_winsys_fence *_fence)
945 {
946 int r;
947 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
948 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
949 struct drm_amdgpu_bo_list_entry *handles = NULL;
950 struct radv_amdgpu_cs_request request = {};
951 struct amdgpu_cs_ib_info *ibs;
952 struct radv_amdgpu_cs *cs0;
953 unsigned num_handles = 0;
954 unsigned number_of_ibs;
955
956 assert(cs_count);
957 cs0 = radv_amdgpu_cs(cs_array[0]);
958
959 /* Compute the number of IBs for this submit. */
960 number_of_ibs = cs_count + !!initial_preamble_cs;
961
962 /* Get the BO list. */
963 r = radv_amdgpu_get_bo_list(cs0->ws, &cs_array[0], cs_count, NULL, 0,
964 initial_preamble_cs, radv_bo_list,
965 &num_handles, &handles);
966 if (r)
967 return r;
968
969 ibs = malloc(number_of_ibs * sizeof(*ibs));
970 if (!ibs) {
971 free(request.handles);
972 return -ENOMEM;
973 }
974
975 /* Configure the CS request. */
976 if (initial_preamble_cs)
977 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
978
979 for (unsigned i = 0; i < cs_count; i++) {
980 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
981
982 ibs[i + !!initial_preamble_cs] = cs->ib;
983
984 if (cs->is_chained) {
985 *cs->ib_size_ptr -= 4;
986 cs->is_chained = false;
987 }
988 }
989
990 request.ip_type = cs0->hw_ip;
991 request.ring = queue_idx;
992 request.handles = handles;
993 request.num_handles = num_handles;
994 request.number_of_ibs = number_of_ibs;
995 request.ibs = ibs;
996 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
997
998 /* Submit the CS. */
999 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
1000 if (r) {
1001 if (r == -ENOMEM)
1002 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1003 else
1004 fprintf(stderr, "amdgpu: The CS has been rejected, "
1005 "see dmesg for more information.\n");
1006 }
1007
1008 free(request.handles);
1009 free(ibs);
1010
1011 if (r)
1012 return r;
1013
1014 if (fence)
1015 radv_amdgpu_request_to_fence(ctx, fence, &request);
1016
1017 radv_assign_last_submit(ctx, &request);
1018
1019 return 0;
1020 }
1021
1022 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
1023 int queue_idx,
1024 struct radv_winsys_sem_info *sem_info,
1025 const struct radv_winsys_bo_list *radv_bo_list,
1026 struct radeon_cmdbuf **cs_array,
1027 unsigned cs_count,
1028 struct radeon_cmdbuf *initial_preamble_cs,
1029 struct radeon_cmdbuf *continue_preamble_cs,
1030 struct radeon_winsys_fence *_fence)
1031 {
1032 int r;
1033 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1034 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
1035 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
1036 struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
1037 struct radv_amdgpu_cs_request request;
1038 uint32_t pad_word = PKT3_NOP_PAD;
1039 bool emit_signal_sem = sem_info->cs_emit_signal;
1040
1041 if (radv_amdgpu_winsys(ws)->info.chip_class == GFX6)
1042 pad_word = 0x80000000;
1043
1044 assert(cs_count);
1045
1046 for (unsigned i = 0; i < cs_count;) {
1047 struct amdgpu_cs_ib_info *ibs;
1048 struct radeon_winsys_bo **bos;
1049 struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
1050 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
1051 struct drm_amdgpu_bo_list_entry *handles = NULL;
1052 unsigned num_handles = 0;
1053 unsigned number_of_ibs;
1054 uint32_t *ptr;
1055 unsigned cnt = 0;
1056 unsigned size = 0;
1057 unsigned pad_words = 0;
1058
1059 /* Compute the number of IBs for this submit. */
1060 number_of_ibs = cs->num_old_cs_buffers + 1;
1061
1062 ibs = malloc(number_of_ibs * sizeof(*ibs));
1063 if (!ibs)
1064 return -ENOMEM;
1065
1066 bos = malloc(number_of_ibs * sizeof(*bos));
1067 if (!bos) {
1068 free(ibs);
1069 return -ENOMEM;
1070 }
1071
1072 if (number_of_ibs > 1) {
1073 /* Special path when the maximum size in dwords has
1074 * been reached because we need to handle more than one
1075 * IB per submit.
1076 */
1077 struct radeon_cmdbuf **new_cs_array;
1078 unsigned idx = 0;
1079
1080 new_cs_array = malloc(cs->num_old_cs_buffers *
1081 sizeof(*new_cs_array));
1082 assert(new_cs_array);
1083
1084 for (unsigned j = 0; j < cs->num_old_cs_buffers; j++)
1085 new_cs_array[idx++] = &cs->old_cs_buffers[j];
1086 new_cs_array[idx++] = cs_array[i];
1087
1088 for (unsigned j = 0; j < number_of_ibs; j++) {
1089 struct radeon_cmdbuf *rcs = new_cs_array[j];
1090 bool needs_preamble = preamble_cs && j == 0;
1091 unsigned size = 0;
1092
1093 if (needs_preamble)
1094 size += preamble_cs->cdw;
1095 size += rcs->cdw;
1096
1097 assert(size < 0xffff8);
1098
1099 while (!size || (size & 7)) {
1100 size++;
1101 pad_words++;
1102 }
1103
1104 bos[j] = ws->buffer_create(ws, 4 * size, 4096,
1105 RADEON_DOMAIN_GTT,
1106 RADEON_FLAG_CPU_ACCESS |
1107 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1108 RADEON_FLAG_READ_ONLY,
1109 RADV_BO_PRIORITY_CS);
1110 ptr = ws->buffer_map(bos[j]);
1111
1112 if (needs_preamble) {
1113 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1114 ptr += preamble_cs->cdw;
1115 }
1116
1117 memcpy(ptr, rcs->buf, 4 * rcs->cdw);
1118 ptr += rcs->cdw;
1119
1120 for (unsigned k = 0; k < pad_words; ++k)
1121 *ptr++ = pad_word;
1122
1123 ibs[j].size = size;
1124 ibs[j].ib_mc_address = radv_buffer_get_va(bos[j]);
1125 ibs[j].flags = 0;
1126 }
1127
1128 cnt++;
1129 free(new_cs_array);
1130 } else {
1131 if (preamble_cs)
1132 size += preamble_cs->cdw;
1133
1134 while (i + cnt < cs_count && 0xffff8 - size >= radv_amdgpu_cs(cs_array[i + cnt])->base.cdw) {
1135 size += radv_amdgpu_cs(cs_array[i + cnt])->base.cdw;
1136 ++cnt;
1137 }
1138
1139 while (!size || (size & 7)) {
1140 size++;
1141 pad_words++;
1142 }
1143 assert(cnt);
1144
1145 bos[0] = ws->buffer_create(ws, 4 * size, 4096,
1146 RADEON_DOMAIN_GTT,
1147 RADEON_FLAG_CPU_ACCESS |
1148 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1149 RADEON_FLAG_READ_ONLY,
1150 RADV_BO_PRIORITY_CS);
1151 ptr = ws->buffer_map(bos[0]);
1152
1153 if (preamble_cs) {
1154 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1155 ptr += preamble_cs->cdw;
1156 }
1157
1158 for (unsigned j = 0; j < cnt; ++j) {
1159 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + j]);
1160 memcpy(ptr, cs->base.buf, 4 * cs->base.cdw);
1161 ptr += cs->base.cdw;
1162
1163 }
1164
1165 for (unsigned j = 0; j < pad_words; ++j)
1166 *ptr++ = pad_word;
1167
1168 ibs[0].size = size;
1169 ibs[0].ib_mc_address = radv_buffer_get_va(bos[0]);
1170 ibs[0].flags = 0;
1171 }
1172
1173 r = radv_amdgpu_get_bo_list(cs0->ws, &cs_array[i], cnt,
1174 (struct radv_amdgpu_winsys_bo **)bos,
1175 number_of_ibs, preamble_cs,
1176 radv_bo_list,
1177 &num_handles, &handles);
1178 if (r) {
1179 fprintf(stderr, "amdgpu: buffer list creation failed "
1180 "for the sysmem submission (%d)\n", r);
1181 free(ibs);
1182 free(bos);
1183 return r;
1184 }
1185
1186 memset(&request, 0, sizeof(request));
1187
1188 request.ip_type = cs0->hw_ip;
1189 request.ring = queue_idx;
1190 request.handles = handles;
1191 request.num_handles = num_handles;
1192 request.number_of_ibs = number_of_ibs;
1193 request.ibs = ibs;
1194 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
1195
1196 sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
1197 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
1198 if (r) {
1199 if (r == -ENOMEM)
1200 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1201 else
1202 fprintf(stderr, "amdgpu: The CS has been rejected, "
1203 "see dmesg for more information.\n");
1204 }
1205
1206 free(request.handles);
1207
1208 for (unsigned j = 0; j < number_of_ibs; j++) {
1209 ws->buffer_destroy(bos[j]);
1210 }
1211
1212 free(ibs);
1213 free(bos);
1214
1215 if (r)
1216 return r;
1217
1218 i += cnt;
1219 }
1220 if (fence)
1221 radv_amdgpu_request_to_fence(ctx, fence, &request);
1222
1223 radv_assign_last_submit(ctx, &request);
1224
1225 return 0;
1226 }
1227
1228 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
1229 int queue_idx,
1230 struct radeon_cmdbuf **cs_array,
1231 unsigned cs_count,
1232 struct radeon_cmdbuf *initial_preamble_cs,
1233 struct radeon_cmdbuf *continue_preamble_cs,
1234 struct radv_winsys_sem_info *sem_info,
1235 const struct radv_winsys_bo_list *bo_list,
1236 bool can_patch,
1237 struct radeon_winsys_fence *_fence)
1238 {
1239 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
1240 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1241 int ret;
1242
1243 assert(sem_info);
1244 if (!cs->ws->use_ib_bos) {
1245 ret = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, bo_list, cs_array,
1246 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1247 } else if (can_patch) {
1248 ret = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, bo_list, cs_array,
1249 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1250 } else {
1251 ret = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, bo_list, cs_array,
1252 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1253 }
1254
1255 radv_amdgpu_signal_sems(ctx, cs->hw_ip, queue_idx, sem_info);
1256 return ret;
1257 }
1258
1259 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
1260 {
1261 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1262 void *ret = NULL;
1263
1264 if (!cs->ib_buffer)
1265 return NULL;
1266 for (unsigned i = 0; i <= cs->num_old_ib_buffers; ++i) {
1267 struct radv_amdgpu_winsys_bo *bo;
1268
1269 bo = (struct radv_amdgpu_winsys_bo*)
1270 (i == cs->num_old_ib_buffers ? cs->ib_buffer : cs->old_ib_buffers[i]);
1271 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1272 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0)
1273 return (char *)ret + (addr - bo->base.va);
1274 }
1275 }
1276 if(cs->ws->debug_all_bos) {
1277 pthread_mutex_lock(&cs->ws->global_bo_list_lock);
1278 list_for_each_entry(struct radv_amdgpu_winsys_bo, bo,
1279 &cs->ws->global_bo_list, global_list_item) {
1280 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1281 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0) {
1282 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1283 return (char *)ret + (addr - bo->base.va);
1284 }
1285 }
1286 }
1287 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1288 }
1289 return ret;
1290 }
1291
1292 static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs,
1293 FILE* file,
1294 const int *trace_ids, int trace_id_count)
1295 {
1296 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1297 void *ib = cs->base.buf;
1298 int num_dw = cs->base.cdw;
1299
1300 if (cs->ws->use_ib_bos) {
1301 ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
1302 num_dw = cs->ib.size;
1303 }
1304 assert(ib);
1305 ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB",
1306 cs->ws->info.chip_class, radv_amdgpu_winsys_get_cpu_addr, cs);
1307 }
1308
1309 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority)
1310 {
1311 switch (radv_priority) {
1312 case RADEON_CTX_PRIORITY_REALTIME:
1313 return AMDGPU_CTX_PRIORITY_VERY_HIGH;
1314 case RADEON_CTX_PRIORITY_HIGH:
1315 return AMDGPU_CTX_PRIORITY_HIGH;
1316 case RADEON_CTX_PRIORITY_MEDIUM:
1317 return AMDGPU_CTX_PRIORITY_NORMAL;
1318 case RADEON_CTX_PRIORITY_LOW:
1319 return AMDGPU_CTX_PRIORITY_LOW;
1320 default:
1321 unreachable("Invalid context priority");
1322 }
1323 }
1324
1325 static VkResult radv_amdgpu_ctx_create(struct radeon_winsys *_ws,
1326 enum radeon_ctx_priority priority,
1327 struct radeon_winsys_ctx **rctx)
1328 {
1329 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1330 struct radv_amdgpu_ctx *ctx = CALLOC_STRUCT(radv_amdgpu_ctx);
1331 uint32_t amdgpu_priority = radv_to_amdgpu_priority(priority);
1332 VkResult result;
1333 int r;
1334
1335 if (!ctx)
1336 return VK_ERROR_OUT_OF_HOST_MEMORY;
1337
1338 r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
1339 if (r && r == -EACCES) {
1340 result = VK_ERROR_NOT_PERMITTED_EXT;
1341 goto error_create;
1342 } else if (r) {
1343 fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r);
1344 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1345 goto error_create;
1346 }
1347 ctx->ws = ws;
1348
1349 assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
1350 ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
1351 RADEON_DOMAIN_GTT,
1352 RADEON_FLAG_CPU_ACCESS |
1353 RADEON_FLAG_NO_INTERPROCESS_SHARING,
1354 RADV_BO_PRIORITY_CS);
1355 if (ctx->fence_bo)
1356 ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
1357 if (ctx->fence_map)
1358 memset(ctx->fence_map, 0, 4096);
1359
1360 *rctx = (struct radeon_winsys_ctx *)ctx;
1361 return VK_SUCCESS;
1362 error_create:
1363 FREE(ctx);
1364 return result;
1365 }
1366
1367 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
1368 {
1369 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1370 ctx->ws->base.buffer_destroy(ctx->fence_bo);
1371 amdgpu_cs_ctx_free(ctx->ctx);
1372 FREE(ctx);
1373 }
1374
1375 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
1376 enum ring_type ring_type, int ring_index)
1377 {
1378 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1379 int ip_type = ring_to_hw_ip(ring_type);
1380
1381 if (ctx->last_submission[ip_type][ring_index].fence.fence) {
1382 uint32_t expired;
1383 int ret = amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index].fence,
1384 1000000000ull, 0, &expired);
1385
1386 if (ret || !expired)
1387 return false;
1388 }
1389
1390 return true;
1391 }
1392
1393 static struct radeon_winsys_sem *radv_amdgpu_create_sem(struct radeon_winsys *_ws)
1394 {
1395 struct amdgpu_cs_fence *sem = CALLOC_STRUCT(amdgpu_cs_fence);
1396 if (!sem)
1397 return NULL;
1398
1399 return (struct radeon_winsys_sem *)sem;
1400 }
1401
1402 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem *_sem)
1403 {
1404 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)_sem;
1405 FREE(sem);
1406 }
1407
1408 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
1409 uint32_t ip_type,
1410 uint32_t ring,
1411 struct radv_winsys_sem_info *sem_info)
1412 {
1413 for (unsigned i = 0; i < sem_info->signal.sem_count; i++) {
1414 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)(sem_info->signal.sem)[i];
1415
1416 if (sem->context)
1417 return -EINVAL;
1418
1419 *sem = ctx->last_submission[ip_type][ring].fence;
1420 }
1421 return 0;
1422 }
1423
1424 static struct drm_amdgpu_cs_chunk_sem *radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts *counts,
1425 struct drm_amdgpu_cs_chunk *chunk, int chunk_id)
1426 {
1427 struct drm_amdgpu_cs_chunk_sem *syncobj = malloc(sizeof(struct drm_amdgpu_cs_chunk_sem) * counts->syncobj_count);
1428 if (!syncobj)
1429 return NULL;
1430
1431 for (unsigned i = 0; i < counts->syncobj_count; i++) {
1432 struct drm_amdgpu_cs_chunk_sem *sem = &syncobj[i];
1433 sem->handle = counts->syncobj[i];
1434 }
1435
1436 chunk->chunk_id = chunk_id;
1437 chunk->length_dw = sizeof(struct drm_amdgpu_cs_chunk_sem) / 4 * counts->syncobj_count;
1438 chunk->chunk_data = (uint64_t)(uintptr_t)syncobj;
1439 return syncobj;
1440 }
1441
1442 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
1443 struct radv_amdgpu_cs_request *request,
1444 struct radv_winsys_sem_info *sem_info)
1445 {
1446 int r;
1447 int num_chunks;
1448 int size;
1449 bool user_fence;
1450 struct drm_amdgpu_cs_chunk *chunks;
1451 struct drm_amdgpu_cs_chunk_data *chunk_data;
1452 struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
1453 struct drm_amdgpu_cs_chunk_sem *wait_syncobj = NULL, *signal_syncobj = NULL;
1454 bool use_bo_list_create = ctx->ws->info.drm_minor < 27;
1455 struct drm_amdgpu_bo_list_in bo_list_in;
1456 int i;
1457 struct amdgpu_cs_fence *sem;
1458 uint32_t bo_list = 0;
1459
1460 user_fence = (request->fence_info.handle != NULL);
1461 size = request->number_of_ibs + (user_fence ? 2 : 1) + (!use_bo_list_create ? 1 : 0) + 3;
1462
1463 chunks = malloc(sizeof(chunks[0]) * size);
1464 if (!chunks)
1465 return -ENOMEM;
1466
1467 size = request->number_of_ibs + (user_fence ? 1 : 0);
1468
1469 chunk_data = malloc(sizeof(chunk_data[0]) * size);
1470 if (!chunk_data) {
1471 r = -ENOMEM;
1472 goto error_out;
1473 }
1474
1475 num_chunks = request->number_of_ibs;
1476 for (i = 0; i < request->number_of_ibs; i++) {
1477 struct amdgpu_cs_ib_info *ib;
1478 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
1479 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
1480 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1481
1482 ib = &request->ibs[i];
1483
1484 chunk_data[i].ib_data._pad = 0;
1485 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
1486 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
1487 chunk_data[i].ib_data.ip_type = request->ip_type;
1488 chunk_data[i].ib_data.ip_instance = request->ip_instance;
1489 chunk_data[i].ib_data.ring = request->ring;
1490 chunk_data[i].ib_data.flags = ib->flags;
1491 }
1492
1493 if (user_fence) {
1494 i = num_chunks++;
1495
1496 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
1497 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
1498 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1499
1500 amdgpu_cs_chunk_fence_info_to_data(&request->fence_info,
1501 &chunk_data[i]);
1502 }
1503
1504 if (sem_info->wait.syncobj_count && sem_info->cs_emit_wait) {
1505 wait_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->wait,
1506 &chunks[num_chunks],
1507 AMDGPU_CHUNK_ID_SYNCOBJ_IN);
1508 if (!wait_syncobj) {
1509 r = -ENOMEM;
1510 goto error_out;
1511 }
1512 num_chunks++;
1513
1514 if (sem_info->wait.sem_count == 0)
1515 sem_info->cs_emit_wait = false;
1516
1517 }
1518
1519 if (sem_info->wait.sem_count && sem_info->cs_emit_wait) {
1520 sem_dependencies = malloc(sizeof(sem_dependencies[0]) * sem_info->wait.sem_count);
1521 if (!sem_dependencies) {
1522 r = -ENOMEM;
1523 goto error_out;
1524 }
1525
1526 int sem_count = 0;
1527
1528 for (unsigned j = 0; j < sem_info->wait.sem_count; j++) {
1529 sem = (struct amdgpu_cs_fence *)sem_info->wait.sem[j];
1530 if (!sem->context)
1531 continue;
1532 struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
1533
1534 amdgpu_cs_chunk_fence_to_dep(sem, dep);
1535
1536 sem->context = NULL;
1537 }
1538 i = num_chunks++;
1539
1540 /* dependencies chunk */
1541 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
1542 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
1543 chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
1544
1545 sem_info->cs_emit_wait = false;
1546 }
1547
1548 if (sem_info->signal.syncobj_count && sem_info->cs_emit_signal) {
1549 signal_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->signal,
1550 &chunks[num_chunks],
1551 AMDGPU_CHUNK_ID_SYNCOBJ_OUT);
1552 if (!signal_syncobj) {
1553 r = -ENOMEM;
1554 goto error_out;
1555 }
1556 num_chunks++;
1557 }
1558
1559 if (use_bo_list_create) {
1560 /* Legacy path creating the buffer list handle and passing it
1561 * to the CS ioctl.
1562 */
1563 r = amdgpu_bo_list_create_raw(ctx->ws->dev, request->num_handles,
1564 request->handles, &bo_list);
1565 if (r) {
1566 fprintf(stderr, "amdgpu: buffer list creation failed (%d)\n", r);
1567 goto error_out;
1568 }
1569 } else {
1570 /* Standard path passing the buffer list via the CS ioctl. */
1571 bo_list_in.operation = ~0;
1572 bo_list_in.list_handle = ~0;
1573 bo_list_in.bo_number = request->num_handles;
1574 bo_list_in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
1575 bo_list_in.bo_info_ptr = (uint64_t)(uintptr_t)request->handles;
1576
1577 chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_BO_HANDLES;
1578 chunks[num_chunks].length_dw = sizeof(struct drm_amdgpu_bo_list_in) / 4;
1579 chunks[num_chunks].chunk_data = (uintptr_t)&bo_list_in;
1580 num_chunks++;
1581 }
1582
1583 r = amdgpu_cs_submit_raw2(ctx->ws->dev,
1584 ctx->ctx,
1585 bo_list,
1586 num_chunks,
1587 chunks,
1588 &request->seq_no);
1589
1590 if (bo_list)
1591 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
1592
1593 error_out:
1594 free(chunks);
1595 free(chunk_data);
1596 free(sem_dependencies);
1597 free(wait_syncobj);
1598 free(signal_syncobj);
1599 return r;
1600 }
1601
1602 static int radv_amdgpu_create_syncobj(struct radeon_winsys *_ws,
1603 uint32_t *handle)
1604 {
1605 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1606 return amdgpu_cs_create_syncobj(ws->dev, handle);
1607 }
1608
1609 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys *_ws,
1610 uint32_t handle)
1611 {
1612 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1613 amdgpu_cs_destroy_syncobj(ws->dev, handle);
1614 }
1615
1616 static void radv_amdgpu_reset_syncobj(struct radeon_winsys *_ws,
1617 uint32_t handle)
1618 {
1619 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1620 amdgpu_cs_syncobj_reset(ws->dev, &handle, 1);
1621 }
1622
1623 static void radv_amdgpu_signal_syncobj(struct radeon_winsys *_ws,
1624 uint32_t handle)
1625 {
1626 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1627 amdgpu_cs_syncobj_signal(ws->dev, &handle, 1);
1628 }
1629
1630 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys *_ws, const uint32_t *handles,
1631 uint32_t handle_count, bool wait_all, uint64_t timeout)
1632 {
1633 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1634 uint32_t tmp;
1635
1636 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1637 timeout = MIN2(timeout, INT64_MAX);
1638
1639 int ret = amdgpu_cs_syncobj_wait(ws->dev, (uint32_t*)handles, handle_count, timeout,
1640 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT |
1641 (wait_all ? DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL : 0),
1642 &tmp);
1643 if (ret == 0) {
1644 return true;
1645 } else if (ret == -ETIME) {
1646 return false;
1647 } else {
1648 fprintf(stderr, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno);
1649 return false;
1650 }
1651 }
1652
1653 static int radv_amdgpu_export_syncobj(struct radeon_winsys *_ws,
1654 uint32_t syncobj,
1655 int *fd)
1656 {
1657 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1658
1659 return amdgpu_cs_export_syncobj(ws->dev, syncobj, fd);
1660 }
1661
1662 static int radv_amdgpu_import_syncobj(struct radeon_winsys *_ws,
1663 int fd,
1664 uint32_t *syncobj)
1665 {
1666 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1667
1668 return amdgpu_cs_import_syncobj(ws->dev, fd, syncobj);
1669 }
1670
1671
1672 static int radv_amdgpu_export_syncobj_to_sync_file(struct radeon_winsys *_ws,
1673 uint32_t syncobj,
1674 int *fd)
1675 {
1676 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1677
1678 return amdgpu_cs_syncobj_export_sync_file(ws->dev, syncobj, fd);
1679 }
1680
1681 static int radv_amdgpu_import_syncobj_from_sync_file(struct radeon_winsys *_ws,
1682 uint32_t syncobj,
1683 int fd)
1684 {
1685 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1686
1687 return amdgpu_cs_syncobj_import_sync_file(ws->dev, syncobj, fd);
1688 }
1689
1690 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
1691 {
1692 ws->base.ctx_create = radv_amdgpu_ctx_create;
1693 ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
1694 ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
1695 ws->base.cs_create = radv_amdgpu_cs_create;
1696 ws->base.cs_destroy = radv_amdgpu_cs_destroy;
1697 ws->base.cs_grow = radv_amdgpu_cs_grow;
1698 ws->base.cs_finalize = radv_amdgpu_cs_finalize;
1699 ws->base.cs_reset = radv_amdgpu_cs_reset;
1700 ws->base.cs_add_buffer = radv_amdgpu_cs_add_buffer;
1701 ws->base.cs_execute_secondary = radv_amdgpu_cs_execute_secondary;
1702 ws->base.cs_submit = radv_amdgpu_winsys_cs_submit;
1703 ws->base.cs_dump = radv_amdgpu_winsys_cs_dump;
1704 ws->base.create_fence = radv_amdgpu_create_fence;
1705 ws->base.destroy_fence = radv_amdgpu_destroy_fence;
1706 ws->base.reset_fence = radv_amdgpu_reset_fence;
1707 ws->base.signal_fence = radv_amdgpu_signal_fence;
1708 ws->base.is_fence_waitable = radv_amdgpu_is_fence_waitable;
1709 ws->base.create_sem = radv_amdgpu_create_sem;
1710 ws->base.destroy_sem = radv_amdgpu_destroy_sem;
1711 ws->base.create_syncobj = radv_amdgpu_create_syncobj;
1712 ws->base.destroy_syncobj = radv_amdgpu_destroy_syncobj;
1713 ws->base.reset_syncobj = radv_amdgpu_reset_syncobj;
1714 ws->base.signal_syncobj = radv_amdgpu_signal_syncobj;
1715 ws->base.wait_syncobj = radv_amdgpu_wait_syncobj;
1716 ws->base.export_syncobj = radv_amdgpu_export_syncobj;
1717 ws->base.import_syncobj = radv_amdgpu_import_syncobj;
1718 ws->base.export_syncobj_to_sync_file = radv_amdgpu_export_syncobj_to_sync_file;
1719 ws->base.import_syncobj_from_sync_file = radv_amdgpu_import_syncobj_from_sync_file;
1720 ws->base.fence_wait = radv_amdgpu_fence_wait;
1721 ws->base.fences_wait = radv_amdgpu_fences_wait;
1722 }