2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include <amdgpu_drm.h>
33 #include "radv_radeon_winsys.h"
34 #include "radv_amdgpu_cs.h"
35 #include "radv_amdgpu_bo.h"
40 VIRTUAL_BUFFER_HASH_TABLE_SIZE
= 1024
43 struct radv_amdgpu_cs
{
44 struct radeon_cmdbuf base
;
45 struct radv_amdgpu_winsys
*ws
;
47 struct amdgpu_cs_ib_info ib
;
49 struct radeon_winsys_bo
*ib_buffer
;
51 unsigned max_num_buffers
;
53 amdgpu_bo_handle
*handles
;
55 struct radeon_winsys_bo
**old_ib_buffers
;
56 unsigned num_old_ib_buffers
;
57 unsigned max_num_old_ib_buffers
;
58 unsigned *ib_size_ptr
;
62 int buffer_hash_table
[1024];
65 unsigned num_virtual_buffers
;
66 unsigned max_num_virtual_buffers
;
67 struct radeon_winsys_bo
**virtual_buffers
;
68 int *virtual_buffer_hash_table
;
70 /* For chips that don't support chaining. */
71 struct radeon_cmdbuf
*old_cs_buffers
;
72 unsigned num_old_cs_buffers
;
75 static inline struct radv_amdgpu_cs
*
76 radv_amdgpu_cs(struct radeon_cmdbuf
*base
)
78 return (struct radv_amdgpu_cs
*)base
;
81 static int ring_to_hw_ip(enum ring_type ring
)
85 return AMDGPU_HW_IP_GFX
;
87 return AMDGPU_HW_IP_DMA
;
89 return AMDGPU_HW_IP_COMPUTE
;
91 unreachable("unsupported ring");
95 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx
*ctx
,
98 struct radv_winsys_sem_info
*sem_info
);
99 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx
*ctx
,
100 struct amdgpu_cs_request
*request
,
101 struct radv_winsys_sem_info
*sem_info
);
103 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx
*ctx
,
104 struct radv_amdgpu_fence
*fence
,
105 struct amdgpu_cs_request
*req
)
107 fence
->fence
.context
= ctx
->ctx
;
108 fence
->fence
.ip_type
= req
->ip_type
;
109 fence
->fence
.ip_instance
= req
->ip_instance
;
110 fence
->fence
.ring
= req
->ring
;
111 fence
->fence
.fence
= req
->seq_no
;
112 fence
->user_ptr
= (volatile uint64_t*)(ctx
->fence_map
+ (req
->ip_type
* MAX_RINGS_PER_TYPE
+ req
->ring
) * sizeof(uint64_t));
115 static struct radeon_winsys_fence
*radv_amdgpu_create_fence()
117 struct radv_amdgpu_fence
*fence
= calloc(1, sizeof(struct radv_amdgpu_fence
));
118 return (struct radeon_winsys_fence
*)fence
;
121 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence
*_fence
)
123 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
127 static bool radv_amdgpu_fence_wait(struct radeon_winsys
*_ws
,
128 struct radeon_winsys_fence
*_fence
,
132 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
133 unsigned flags
= absolute
? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
: 0;
135 uint32_t expired
= 0;
137 if (fence
->user_ptr
) {
138 if (*fence
->user_ptr
>= fence
->fence
.fence
)
140 if (!absolute
&& !timeout
)
144 /* Now use the libdrm query. */
145 r
= amdgpu_cs_query_fence_status(&fence
->fence
,
151 fprintf(stderr
, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
162 static bool radv_amdgpu_fences_wait(struct radeon_winsys
*_ws
,
163 struct radeon_winsys_fence
*const *_fences
,
164 uint32_t fence_count
,
168 struct amdgpu_cs_fence
*fences
= malloc(sizeof(struct amdgpu_cs_fence
) * fence_count
);
170 uint32_t expired
= 0, first
= 0;
175 for (uint32_t i
= 0; i
< fence_count
; ++i
)
176 fences
[i
] = ((struct radv_amdgpu_fence
*)_fences
[i
])->fence
;
178 /* Now use the libdrm query. */
179 r
= amdgpu_cs_wait_fences(fences
, fence_count
, wait_all
,
180 timeout
, &expired
, &first
);
184 fprintf(stderr
, "amdgpu: amdgpu_cs_wait_fences failed.\n");
194 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf
*rcs
)
196 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(rcs
);
199 cs
->ws
->base
.buffer_destroy(cs
->ib_buffer
);
203 for (unsigned i
= 0; i
< cs
->num_old_ib_buffers
; ++i
)
204 cs
->ws
->base
.buffer_destroy(cs
->old_ib_buffers
[i
]);
206 for (unsigned i
= 0; i
< cs
->num_old_cs_buffers
; ++i
) {
207 struct radeon_cmdbuf
*rcs
= &cs
->old_cs_buffers
[i
];
211 free(cs
->old_cs_buffers
);
212 free(cs
->old_ib_buffers
);
213 free(cs
->virtual_buffers
);
214 free(cs
->virtual_buffer_hash_table
);
219 static void radv_amdgpu_init_cs(struct radv_amdgpu_cs
*cs
,
220 enum ring_type ring_type
)
222 for (int i
= 0; i
< ARRAY_SIZE(cs
->buffer_hash_table
); ++i
)
223 cs
->buffer_hash_table
[i
] = -1;
225 cs
->hw_ip
= ring_to_hw_ip(ring_type
);
228 static struct radeon_cmdbuf
*
229 radv_amdgpu_cs_create(struct radeon_winsys
*ws
,
230 enum ring_type ring_type
)
232 struct radv_amdgpu_cs
*cs
;
233 uint32_t ib_size
= 20 * 1024 * 4;
234 cs
= calloc(1, sizeof(struct radv_amdgpu_cs
));
238 cs
->ws
= radv_amdgpu_winsys(ws
);
239 radv_amdgpu_init_cs(cs
, ring_type
);
241 if (cs
->ws
->use_ib_bos
) {
242 cs
->ib_buffer
= ws
->buffer_create(ws
, ib_size
, 0,
244 RADEON_FLAG_CPU_ACCESS
|
245 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
246 RADEON_FLAG_READ_ONLY
);
247 if (!cs
->ib_buffer
) {
252 cs
->ib_mapped
= ws
->buffer_map(cs
->ib_buffer
);
253 if (!cs
->ib_mapped
) {
254 ws
->buffer_destroy(cs
->ib_buffer
);
259 cs
->ib
.ib_mc_address
= radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
;
260 cs
->base
.buf
= (uint32_t *)cs
->ib_mapped
;
261 cs
->base
.max_dw
= ib_size
/ 4 - 4;
262 cs
->ib_size_ptr
= &cs
->ib
.size
;
265 ws
->cs_add_buffer(&cs
->base
, cs
->ib_buffer
);
267 cs
->base
.buf
= malloc(16384);
268 cs
->base
.max_dw
= 4096;
278 static void radv_amdgpu_cs_grow(struct radeon_cmdbuf
*_cs
, size_t min_size
)
280 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
287 if (!cs
->ws
->use_ib_bos
) {
288 const uint64_t limit_dws
= 0xffff8;
289 uint64_t ib_dws
= MAX2(cs
->base
.cdw
+ min_size
,
290 MIN2(cs
->base
.max_dw
* 2, limit_dws
));
292 /* The total ib size cannot exceed limit_dws dwords. */
293 if (ib_dws
> limit_dws
)
295 /* The maximum size in dwords has been reached,
296 * try to allocate a new one.
298 if (cs
->num_old_cs_buffers
+ 1 >= AMDGPU_CS_MAX_IBS_PER_SUBMIT
) {
299 /* TODO: Allow to submit more than 4 IBs. */
300 fprintf(stderr
, "amdgpu: Maximum number of IBs "
301 "per submit reached.\n");
308 realloc(cs
->old_cs_buffers
,
309 (cs
->num_old_cs_buffers
+ 1) * sizeof(*cs
->old_cs_buffers
));
310 if (!cs
->old_cs_buffers
) {
316 /* Store the current one for submitting it later. */
317 cs
->old_cs_buffers
[cs
->num_old_cs_buffers
].cdw
= cs
->base
.cdw
;
318 cs
->old_cs_buffers
[cs
->num_old_cs_buffers
].max_dw
= cs
->base
.max_dw
;
319 cs
->old_cs_buffers
[cs
->num_old_cs_buffers
].buf
= cs
->base
.buf
;
320 cs
->num_old_cs_buffers
++;
322 /* Reset the cs, it will be re-allocated below. */
326 /* Re-compute the number of dwords to allocate. */
327 ib_dws
= MAX2(cs
->base
.cdw
+ min_size
,
328 MIN2(cs
->base
.max_dw
* 2, limit_dws
));
329 if (ib_dws
> limit_dws
) {
330 fprintf(stderr
, "amdgpu: Too high number of "
331 "dwords to allocate\n");
337 uint32_t *new_buf
= realloc(cs
->base
.buf
, ib_dws
* 4);
339 cs
->base
.buf
= new_buf
;
340 cs
->base
.max_dw
= ib_dws
;
348 uint64_t ib_size
= MAX2(min_size
* 4 + 16, cs
->base
.max_dw
* 4 * 2);
350 /* max that fits in the chain size field. */
351 ib_size
= MIN2(ib_size
, 0xfffff);
353 while (!cs
->base
.cdw
|| (cs
->base
.cdw
& 7) != 4)
354 radeon_emit(&cs
->base
, 0xffff1000);
356 *cs
->ib_size_ptr
|= cs
->base
.cdw
+ 4;
358 if (cs
->num_old_ib_buffers
== cs
->max_num_old_ib_buffers
) {
359 cs
->max_num_old_ib_buffers
= MAX2(1, cs
->max_num_old_ib_buffers
* 2);
360 cs
->old_ib_buffers
= realloc(cs
->old_ib_buffers
,
361 cs
->max_num_old_ib_buffers
* sizeof(void*));
364 cs
->old_ib_buffers
[cs
->num_old_ib_buffers
++] = cs
->ib_buffer
;
366 cs
->ib_buffer
= cs
->ws
->base
.buffer_create(&cs
->ws
->base
, ib_size
, 0,
368 RADEON_FLAG_CPU_ACCESS
|
369 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
370 RADEON_FLAG_READ_ONLY
);
372 if (!cs
->ib_buffer
) {
375 cs
->ib_buffer
= cs
->old_ib_buffers
[--cs
->num_old_ib_buffers
];
378 cs
->ib_mapped
= cs
->ws
->base
.buffer_map(cs
->ib_buffer
);
379 if (!cs
->ib_mapped
) {
380 cs
->ws
->base
.buffer_destroy(cs
->ib_buffer
);
383 cs
->ib_buffer
= cs
->old_ib_buffers
[--cs
->num_old_ib_buffers
];
386 cs
->ws
->base
.cs_add_buffer(&cs
->base
, cs
->ib_buffer
);
388 radeon_emit(&cs
->base
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
389 radeon_emit(&cs
->base
, radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
);
390 radeon_emit(&cs
->base
, radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
>> 32);
391 radeon_emit(&cs
->base
, S_3F2_CHAIN(1) | S_3F2_VALID(1));
393 cs
->ib_size_ptr
= cs
->base
.buf
+ cs
->base
.cdw
- 1;
395 cs
->base
.buf
= (uint32_t *)cs
->ib_mapped
;
397 cs
->base
.max_dw
= ib_size
/ 4 - 4;
401 static bool radv_amdgpu_cs_finalize(struct radeon_cmdbuf
*_cs
)
403 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
405 if (cs
->ws
->use_ib_bos
) {
406 while (!cs
->base
.cdw
|| (cs
->base
.cdw
& 7) != 0)
407 radeon_emit(&cs
->base
, 0xffff1000);
409 *cs
->ib_size_ptr
|= cs
->base
.cdw
;
411 cs
->is_chained
= false;
417 static void radv_amdgpu_cs_reset(struct radeon_cmdbuf
*_cs
)
419 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
423 for (unsigned i
= 0; i
< cs
->num_buffers
; ++i
) {
424 unsigned hash
= ((uintptr_t)cs
->handles
[i
] >> 6) &
425 (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
426 cs
->buffer_hash_table
[hash
] = -1;
429 for (unsigned i
= 0; i
< cs
->num_virtual_buffers
; ++i
) {
430 unsigned hash
= ((uintptr_t)cs
->virtual_buffers
[i
] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE
- 1);
431 cs
->virtual_buffer_hash_table
[hash
] = -1;
435 cs
->num_virtual_buffers
= 0;
437 if (cs
->ws
->use_ib_bos
) {
438 cs
->ws
->base
.cs_add_buffer(&cs
->base
, cs
->ib_buffer
);
440 for (unsigned i
= 0; i
< cs
->num_old_ib_buffers
; ++i
)
441 cs
->ws
->base
.buffer_destroy(cs
->old_ib_buffers
[i
]);
443 cs
->num_old_ib_buffers
= 0;
444 cs
->ib
.ib_mc_address
= radv_amdgpu_winsys_bo(cs
->ib_buffer
)->base
.va
;
445 cs
->ib_size_ptr
= &cs
->ib
.size
;
448 for (unsigned i
= 0; i
< cs
->num_old_cs_buffers
; ++i
) {
449 struct radeon_cmdbuf
*rcs
= &cs
->old_cs_buffers
[i
];
453 free(cs
->old_cs_buffers
);
454 cs
->old_cs_buffers
= NULL
;
455 cs
->num_old_cs_buffers
= 0;
459 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs
*cs
,
462 unsigned hash
= ((uintptr_t)bo
>> 6) & (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
463 int index
= cs
->buffer_hash_table
[hash
];
468 if (cs
->handles
[index
] == bo
)
471 for (unsigned i
= 0; i
< cs
->num_buffers
; ++i
) {
472 if (cs
->handles
[i
] == bo
) {
473 cs
->buffer_hash_table
[hash
] = i
;
481 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs
*cs
,
485 int index
= radv_amdgpu_cs_find_buffer(cs
, bo
);
490 if (cs
->num_buffers
== cs
->max_num_buffers
) {
491 unsigned new_count
= MAX2(1, cs
->max_num_buffers
* 2);
492 cs
->handles
= realloc(cs
->handles
, new_count
* sizeof(amdgpu_bo_handle
));
493 cs
->max_num_buffers
= new_count
;
496 cs
->handles
[cs
->num_buffers
] = bo
;
498 hash
= ((uintptr_t)bo
>> 6) & (ARRAY_SIZE(cs
->buffer_hash_table
) - 1);
499 cs
->buffer_hash_table
[hash
] = cs
->num_buffers
;
504 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf
*_cs
,
505 struct radeon_winsys_bo
*bo
)
507 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
508 unsigned hash
= ((uintptr_t)bo
>> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE
- 1);
511 if (!cs
->virtual_buffer_hash_table
) {
512 cs
->virtual_buffer_hash_table
= malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE
* sizeof(int));
513 for (int i
= 0; i
< VIRTUAL_BUFFER_HASH_TABLE_SIZE
; ++i
)
514 cs
->virtual_buffer_hash_table
[i
] = -1;
517 if (cs
->virtual_buffer_hash_table
[hash
] >= 0) {
518 int idx
= cs
->virtual_buffer_hash_table
[hash
];
519 if (cs
->virtual_buffers
[idx
] == bo
) {
522 for (unsigned i
= 0; i
< cs
->num_virtual_buffers
; ++i
) {
523 if (cs
->virtual_buffers
[i
] == bo
) {
524 cs
->virtual_buffer_hash_table
[hash
] = i
;
530 if(cs
->max_num_virtual_buffers
<= cs
->num_virtual_buffers
) {
531 cs
->max_num_virtual_buffers
= MAX2(2, cs
->max_num_virtual_buffers
* 2);
532 cs
->virtual_buffers
= realloc(cs
->virtual_buffers
, sizeof(struct radv_amdgpu_virtual_virtual_buffer
*) * cs
->max_num_virtual_buffers
);
535 cs
->virtual_buffers
[cs
->num_virtual_buffers
] = bo
;
537 cs
->virtual_buffer_hash_table
[hash
] = cs
->num_virtual_buffers
;
538 ++cs
->num_virtual_buffers
;
542 static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf
*_cs
,
543 struct radeon_winsys_bo
*_bo
)
545 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(_cs
);
546 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(_bo
);
548 if (bo
->is_virtual
) {
549 radv_amdgpu_cs_add_virtual_buffer(_cs
, _bo
);
553 if (bo
->base
.is_local
)
556 radv_amdgpu_cs_add_buffer_internal(cs
, bo
->bo
);
559 static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf
*_parent
,
560 struct radeon_cmdbuf
*_child
)
562 struct radv_amdgpu_cs
*parent
= radv_amdgpu_cs(_parent
);
563 struct radv_amdgpu_cs
*child
= radv_amdgpu_cs(_child
);
565 for (unsigned i
= 0; i
< child
->num_buffers
; ++i
) {
566 radv_amdgpu_cs_add_buffer_internal(parent
, child
->handles
[i
]);
569 for (unsigned i
= 0; i
< child
->num_virtual_buffers
; ++i
) {
570 radv_amdgpu_cs_add_buffer(&parent
->base
, child
->virtual_buffers
[i
]);
573 if (parent
->ws
->use_ib_bos
) {
574 if (parent
->base
.cdw
+ 4 > parent
->base
.max_dw
)
575 radv_amdgpu_cs_grow(&parent
->base
, 4);
577 radeon_emit(&parent
->base
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
578 radeon_emit(&parent
->base
, child
->ib
.ib_mc_address
);
579 radeon_emit(&parent
->base
, child
->ib
.ib_mc_address
>> 32);
580 radeon_emit(&parent
->base
, child
->ib
.size
);
582 if (parent
->base
.cdw
+ child
->base
.cdw
> parent
->base
.max_dw
)
583 radv_amdgpu_cs_grow(&parent
->base
, child
->base
.cdw
);
585 memcpy(parent
->base
.buf
+ parent
->base
.cdw
, child
->base
.buf
, 4 * child
->base
.cdw
);
586 parent
->base
.cdw
+= child
->base
.cdw
;
590 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys
*ws
,
591 struct radeon_cmdbuf
**cs_array
,
593 struct radv_amdgpu_winsys_bo
**extra_bo_array
,
594 unsigned num_extra_bo
,
595 struct radeon_cmdbuf
*extra_cs
,
596 const struct radv_winsys_bo_list
*radv_bo_list
,
597 amdgpu_bo_list_handle
*bo_list
)
601 if (ws
->debug_all_bos
) {
602 struct radv_amdgpu_winsys_bo
*bo
;
603 amdgpu_bo_handle
*handles
;
606 pthread_mutex_lock(&ws
->global_bo_list_lock
);
608 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
610 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
614 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, global_list_item
) {
615 assert(num
< ws
->num_buffers
);
616 handles
[num
++] = bo
->bo
;
619 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
623 pthread_mutex_unlock(&ws
->global_bo_list_lock
);
624 } else if (count
== 1 && !num_extra_bo
&& !extra_cs
&& !radv_bo_list
&&
625 !radv_amdgpu_cs(cs_array
[0])->num_virtual_buffers
) {
626 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)cs_array
[0];
627 if (cs
->num_buffers
== 0) {
631 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_buffers
, cs
->handles
,
634 unsigned total_buffer_count
= num_extra_bo
;
635 unsigned unique_bo_count
= num_extra_bo
;
636 for (unsigned i
= 0; i
< count
; ++i
) {
637 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)cs_array
[i
];
638 total_buffer_count
+= cs
->num_buffers
;
639 for (unsigned j
= 0; j
< cs
->num_virtual_buffers
; ++j
)
640 total_buffer_count
+= radv_amdgpu_winsys_bo(cs
->virtual_buffers
[j
])->bo_count
;
644 total_buffer_count
+= ((struct radv_amdgpu_cs
*)extra_cs
)->num_buffers
;
648 total_buffer_count
+= radv_bo_list
->count
;
651 if (total_buffer_count
== 0) {
655 amdgpu_bo_handle
*handles
= malloc(sizeof(amdgpu_bo_handle
) * total_buffer_count
);
661 for (unsigned i
= 0; i
< num_extra_bo
; i
++) {
662 handles
[i
] = extra_bo_array
[i
]->bo
;
665 for (unsigned i
= 0; i
< count
+ !!extra_cs
; ++i
) {
666 struct radv_amdgpu_cs
*cs
;
669 cs
= (struct radv_amdgpu_cs
*)extra_cs
;
671 cs
= (struct radv_amdgpu_cs
*)cs_array
[i
];
673 if (!cs
->num_buffers
)
676 if (unique_bo_count
== 0) {
677 memcpy(handles
, cs
->handles
, cs
->num_buffers
* sizeof(amdgpu_bo_handle
));
678 unique_bo_count
= cs
->num_buffers
;
681 int unique_bo_so_far
= unique_bo_count
;
682 for (unsigned j
= 0; j
< cs
->num_buffers
; ++j
) {
684 for (unsigned k
= 0; k
< unique_bo_so_far
; ++k
) {
685 if (handles
[k
] == cs
->handles
[j
]) {
691 handles
[unique_bo_count
] = cs
->handles
[j
];
695 for (unsigned j
= 0; j
< cs
->num_virtual_buffers
; ++j
) {
696 struct radv_amdgpu_winsys_bo
*virtual_bo
= radv_amdgpu_winsys_bo(cs
->virtual_buffers
[j
]);
697 for(unsigned k
= 0; k
< virtual_bo
->bo_count
; ++k
) {
698 struct radv_amdgpu_winsys_bo
*bo
= virtual_bo
->bos
[k
];
700 for (unsigned m
= 0; m
< unique_bo_count
; ++m
) {
701 if (handles
[m
] == bo
->bo
) {
707 handles
[unique_bo_count
] = bo
->bo
;
715 unsigned unique_bo_so_far
= unique_bo_count
;
716 for (unsigned i
= 0; i
< radv_bo_list
->count
; ++i
) {
717 struct radv_amdgpu_winsys_bo
*bo
= radv_amdgpu_winsys_bo(radv_bo_list
->bos
[i
]);
719 for (unsigned j
= 0; j
< unique_bo_so_far
; ++j
) {
720 if (bo
->bo
== handles
[j
]) {
726 handles
[unique_bo_count
] = bo
->bo
;
732 if (unique_bo_count
> 0) {
733 r
= amdgpu_bo_list_create(ws
->dev
, unique_bo_count
, handles
,
745 static struct amdgpu_cs_fence_info
radv_set_cs_fence(struct radv_amdgpu_ctx
*ctx
, int ip_type
, int ring
)
747 struct amdgpu_cs_fence_info ret
= {0};
748 if (ctx
->fence_map
) {
749 ret
.handle
= radv_amdgpu_winsys_bo(ctx
->fence_bo
)->bo
;
750 ret
.offset
= (ip_type
* MAX_RINGS_PER_TYPE
+ ring
) * sizeof(uint64_t);
755 static void radv_assign_last_submit(struct radv_amdgpu_ctx
*ctx
,
756 struct amdgpu_cs_request
*request
)
758 radv_amdgpu_request_to_fence(ctx
,
759 &ctx
->last_submission
[request
->ip_type
][request
->ring
],
763 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx
*_ctx
,
765 struct radv_winsys_sem_info
*sem_info
,
766 const struct radv_winsys_bo_list
*radv_bo_list
,
767 struct radeon_cmdbuf
**cs_array
,
769 struct radeon_cmdbuf
*initial_preamble_cs
,
770 struct radeon_cmdbuf
*continue_preamble_cs
,
771 struct radeon_winsys_fence
*_fence
)
774 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
775 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
776 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[0]);
777 amdgpu_bo_list_handle bo_list
;
778 struct amdgpu_cs_request request
= {0};
779 struct amdgpu_cs_ib_info ibs
[2];
781 for (unsigned i
= cs_count
; i
--;) {
782 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
]);
784 if (cs
->is_chained
) {
785 *cs
->ib_size_ptr
-= 4;
786 cs
->is_chained
= false;
789 if (i
+ 1 < cs_count
) {
790 struct radv_amdgpu_cs
*next
= radv_amdgpu_cs(cs_array
[i
+ 1]);
791 assert(cs
->base
.cdw
+ 4 <= cs
->base
.max_dw
);
793 cs
->is_chained
= true;
794 *cs
->ib_size_ptr
+= 4;
796 cs
->base
.buf
[cs
->base
.cdw
+ 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0);
797 cs
->base
.buf
[cs
->base
.cdw
+ 1] = next
->ib
.ib_mc_address
;
798 cs
->base
.buf
[cs
->base
.cdw
+ 2] = next
->ib
.ib_mc_address
>> 32;
799 cs
->base
.buf
[cs
->base
.cdw
+ 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next
->ib
.size
;
803 r
= radv_amdgpu_create_bo_list(cs0
->ws
, cs_array
, cs_count
, NULL
, 0, initial_preamble_cs
,
804 radv_bo_list
, &bo_list
);
806 fprintf(stderr
, "amdgpu: buffer list creation failed for the "
807 "chained submission(%d)\n", r
);
811 request
.ip_type
= cs0
->hw_ip
;
812 request
.ring
= queue_idx
;
813 request
.number_of_ibs
= 1;
814 request
.ibs
= &cs0
->ib
;
815 request
.resources
= bo_list
;
816 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
818 if (initial_preamble_cs
) {
820 request
.number_of_ibs
= 2;
822 ibs
[0] = ((struct radv_amdgpu_cs
*)initial_preamble_cs
)->ib
;
825 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
828 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
830 fprintf(stderr
, "amdgpu: The CS has been rejected, "
831 "see dmesg for more information.\n");
835 amdgpu_bo_list_destroy(bo_list
);
838 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
840 radv_assign_last_submit(ctx
, &request
);
845 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx
*_ctx
,
847 struct radv_winsys_sem_info
*sem_info
,
848 const struct radv_winsys_bo_list
*radv_bo_list
,
849 struct radeon_cmdbuf
**cs_array
,
851 struct radeon_cmdbuf
*initial_preamble_cs
,
852 struct radeon_cmdbuf
*continue_preamble_cs
,
853 struct radeon_winsys_fence
*_fence
)
856 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
857 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
858 amdgpu_bo_list_handle bo_list
;
859 struct amdgpu_cs_request request
;
860 bool emit_signal_sem
= sem_info
->cs_emit_signal
;
863 for (unsigned i
= 0; i
< cs_count
;) {
864 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[i
]);
865 struct amdgpu_cs_ib_info ibs
[AMDGPU_CS_MAX_IBS_PER_SUBMIT
];
866 struct radeon_cmdbuf
*preamble_cs
= i
? continue_preamble_cs
: initial_preamble_cs
;
867 unsigned cnt
= MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT
- !!preamble_cs
,
870 memset(&request
, 0, sizeof(request
));
872 r
= radv_amdgpu_create_bo_list(cs0
->ws
, &cs_array
[i
], cnt
, NULL
, 0,
873 preamble_cs
, radv_bo_list
, &bo_list
);
875 fprintf(stderr
, "amdgpu: buffer list creation failed "
876 "for the fallback submission (%d)\n", r
);
880 request
.ip_type
= cs0
->hw_ip
;
881 request
.ring
= queue_idx
;
882 request
.resources
= bo_list
;
883 request
.number_of_ibs
= cnt
+ !!preamble_cs
;
885 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
888 ibs
[0] = radv_amdgpu_cs(preamble_cs
)->ib
;
891 for (unsigned j
= 0; j
< cnt
; ++j
) {
892 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
+ j
]);
893 ibs
[j
+ !!preamble_cs
] = cs
->ib
;
895 if (cs
->is_chained
) {
896 *cs
->ib_size_ptr
-= 4;
897 cs
->is_chained
= false;
901 sem_info
->cs_emit_signal
= (i
== cs_count
- cnt
) ? emit_signal_sem
: false;
902 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
905 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
907 fprintf(stderr
, "amdgpu: The CS has been rejected, "
908 "see dmesg for more information.\n");
912 amdgpu_bo_list_destroy(bo_list
);
920 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
922 radv_assign_last_submit(ctx
, &request
);
927 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx
*_ctx
,
929 struct radv_winsys_sem_info
*sem_info
,
930 const struct radv_winsys_bo_list
*radv_bo_list
,
931 struct radeon_cmdbuf
**cs_array
,
933 struct radeon_cmdbuf
*initial_preamble_cs
,
934 struct radeon_cmdbuf
*continue_preamble_cs
,
935 struct radeon_winsys_fence
*_fence
)
938 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
939 struct radv_amdgpu_fence
*fence
= (struct radv_amdgpu_fence
*)_fence
;
940 struct radv_amdgpu_cs
*cs0
= radv_amdgpu_cs(cs_array
[0]);
941 struct radeon_winsys
*ws
= (struct radeon_winsys
*)cs0
->ws
;
942 amdgpu_bo_list_handle bo_list
;
943 struct amdgpu_cs_request request
;
944 uint32_t pad_word
= 0xffff1000U
;
945 bool emit_signal_sem
= sem_info
->cs_emit_signal
;
947 if (radv_amdgpu_winsys(ws
)->info
.chip_class
== SI
)
948 pad_word
= 0x80000000;
952 for (unsigned i
= 0; i
< cs_count
;) {
953 struct amdgpu_cs_ib_info ibs
[AMDGPU_CS_MAX_IBS_PER_SUBMIT
] = {0};
954 unsigned number_of_ibs
= 1;
955 struct radeon_winsys_bo
*bos
[AMDGPU_CS_MAX_IBS_PER_SUBMIT
] = {0};
956 struct radeon_cmdbuf
*preamble_cs
= i
? continue_preamble_cs
: initial_preamble_cs
;
957 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
]);
961 unsigned pad_words
= 0;
963 if (cs
->num_old_cs_buffers
> 0) {
964 /* Special path when the maximum size in dwords has
965 * been reached because we need to handle more than one
968 unsigned new_cs_count
= cs
->num_old_cs_buffers
+ 1;
969 struct radeon_cmdbuf
*new_cs_array
[AMDGPU_CS_MAX_IBS_PER_SUBMIT
];
972 for (unsigned j
= 0; j
< cs
->num_old_cs_buffers
; j
++)
973 new_cs_array
[idx
++] = &cs
->old_cs_buffers
[j
];
974 new_cs_array
[idx
++] = cs_array
[i
];
976 for (unsigned j
= 0; j
< new_cs_count
; j
++) {
977 struct radeon_cmdbuf
*rcs
= new_cs_array
[j
];
978 bool needs_preamble
= preamble_cs
&& j
== 0;
982 size
+= preamble_cs
->cdw
;
985 assert(size
< 0xffff8);
987 while (!size
|| (size
& 7)) {
992 bos
[j
] = ws
->buffer_create(ws
, 4 * size
, 4096,
994 RADEON_FLAG_CPU_ACCESS
|
995 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
996 RADEON_FLAG_READ_ONLY
);
997 ptr
= ws
->buffer_map(bos
[j
]);
999 if (needs_preamble
) {
1000 memcpy(ptr
, preamble_cs
->buf
, preamble_cs
->cdw
* 4);
1001 ptr
+= preamble_cs
->cdw
;
1004 memcpy(ptr
, rcs
->buf
, 4 * rcs
->cdw
);
1007 for (unsigned k
= 0; k
< pad_words
; ++k
)
1011 ibs
[j
].ib_mc_address
= radv_buffer_get_va(bos
[j
]);
1014 number_of_ibs
= new_cs_count
;
1018 size
+= preamble_cs
->cdw
;
1020 while (i
+ cnt
< cs_count
&& 0xffff8 - size
>= radv_amdgpu_cs(cs_array
[i
+ cnt
])->base
.cdw
) {
1021 size
+= radv_amdgpu_cs(cs_array
[i
+ cnt
])->base
.cdw
;
1025 while (!size
|| (size
& 7)) {
1031 bos
[0] = ws
->buffer_create(ws
, 4 * size
, 4096,
1033 RADEON_FLAG_CPU_ACCESS
|
1034 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
1035 RADEON_FLAG_READ_ONLY
);
1036 ptr
= ws
->buffer_map(bos
[0]);
1039 memcpy(ptr
, preamble_cs
->buf
, preamble_cs
->cdw
* 4);
1040 ptr
+= preamble_cs
->cdw
;
1043 for (unsigned j
= 0; j
< cnt
; ++j
) {
1044 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[i
+ j
]);
1045 memcpy(ptr
, cs
->base
.buf
, 4 * cs
->base
.cdw
);
1046 ptr
+= cs
->base
.cdw
;
1050 for (unsigned j
= 0; j
< pad_words
; ++j
)
1054 ibs
[0].ib_mc_address
= radv_buffer_get_va(bos
[0]);
1057 r
= radv_amdgpu_create_bo_list(cs0
->ws
, &cs_array
[i
], cnt
,
1058 (struct radv_amdgpu_winsys_bo
**)bos
,
1059 number_of_ibs
, preamble_cs
,
1060 radv_bo_list
, &bo_list
);
1062 fprintf(stderr
, "amdgpu: buffer list creation failed "
1063 "for the sysmem submission (%d)\n", r
);
1067 memset(&request
, 0, sizeof(request
));
1069 request
.ip_type
= cs0
->hw_ip
;
1070 request
.ring
= queue_idx
;
1071 request
.resources
= bo_list
;
1072 request
.number_of_ibs
= number_of_ibs
;
1074 request
.fence_info
= radv_set_cs_fence(ctx
, cs0
->hw_ip
, queue_idx
);
1076 sem_info
->cs_emit_signal
= (i
== cs_count
- cnt
) ? emit_signal_sem
: false;
1077 r
= radv_amdgpu_cs_submit(ctx
, &request
, sem_info
);
1080 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1082 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1083 "see dmesg for more information.\n");
1087 amdgpu_bo_list_destroy(bo_list
);
1089 for (unsigned j
= 0; j
< number_of_ibs
; j
++) {
1090 ws
->buffer_destroy(bos
[j
]);
1098 radv_amdgpu_request_to_fence(ctx
, fence
, &request
);
1100 radv_assign_last_submit(ctx
, &request
);
1105 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx
*_ctx
,
1107 struct radeon_cmdbuf
**cs_array
,
1109 struct radeon_cmdbuf
*initial_preamble_cs
,
1110 struct radeon_cmdbuf
*continue_preamble_cs
,
1111 struct radv_winsys_sem_info
*sem_info
,
1112 const struct radv_winsys_bo_list
*bo_list
,
1114 struct radeon_winsys_fence
*_fence
)
1116 struct radv_amdgpu_cs
*cs
= radv_amdgpu_cs(cs_array
[0]);
1117 struct radv_amdgpu_ctx
*ctx
= radv_amdgpu_ctx(_ctx
);
1121 if (!cs
->ws
->use_ib_bos
) {
1122 ret
= radv_amdgpu_winsys_cs_submit_sysmem(_ctx
, queue_idx
, sem_info
, bo_list
, cs_array
,
1123 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
1124 } else if (can_patch
&& cs_count
> AMDGPU_CS_MAX_IBS_PER_SUBMIT
&& cs
->ws
->batchchain
) {
1125 ret
= radv_amdgpu_winsys_cs_submit_chained(_ctx
, queue_idx
, sem_info
, bo_list
, cs_array
,
1126 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
1128 ret
= radv_amdgpu_winsys_cs_submit_fallback(_ctx
, queue_idx
, sem_info
, bo_list
, cs_array
,
1129 cs_count
, initial_preamble_cs
, continue_preamble_cs
, _fence
);
1132 radv_amdgpu_signal_sems(ctx
, cs
->hw_ip
, queue_idx
, sem_info
);
1136 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs
, uint64_t addr
)
1138 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)_cs
;
1143 for (unsigned i
= 0; i
<= cs
->num_old_ib_buffers
; ++i
) {
1144 struct radv_amdgpu_winsys_bo
*bo
;
1146 bo
= (struct radv_amdgpu_winsys_bo
*)
1147 (i
== cs
->num_old_ib_buffers
? cs
->ib_buffer
: cs
->old_ib_buffers
[i
]);
1148 if (addr
>= bo
->base
.va
&& addr
- bo
->base
.va
< bo
->size
) {
1149 if (amdgpu_bo_cpu_map(bo
->bo
, &ret
) == 0)
1150 return (char *)ret
+ (addr
- bo
->base
.va
);
1153 if(cs
->ws
->debug_all_bos
) {
1154 pthread_mutex_lock(&cs
->ws
->global_bo_list_lock
);
1155 list_for_each_entry(struct radv_amdgpu_winsys_bo
, bo
,
1156 &cs
->ws
->global_bo_list
, global_list_item
) {
1157 if (addr
>= bo
->base
.va
&& addr
- bo
->base
.va
< bo
->size
) {
1158 if (amdgpu_bo_cpu_map(bo
->bo
, &ret
) == 0) {
1159 pthread_mutex_unlock(&cs
->ws
->global_bo_list_lock
);
1160 return (char *)ret
+ (addr
- bo
->base
.va
);
1164 pthread_mutex_unlock(&cs
->ws
->global_bo_list_lock
);
1169 static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf
*_cs
,
1171 const int *trace_ids
, int trace_id_count
)
1173 struct radv_amdgpu_cs
*cs
= (struct radv_amdgpu_cs
*)_cs
;
1174 void *ib
= cs
->base
.buf
;
1175 int num_dw
= cs
->base
.cdw
;
1177 if (cs
->ws
->use_ib_bos
) {
1178 ib
= radv_amdgpu_winsys_get_cpu_addr(cs
, cs
->ib
.ib_mc_address
);
1179 num_dw
= cs
->ib
.size
;
1182 ac_parse_ib(file
, ib
, num_dw
, trace_ids
, trace_id_count
, "main IB",
1183 cs
->ws
->info
.chip_class
, radv_amdgpu_winsys_get_cpu_addr
, cs
);
1186 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority
)
1188 switch (radv_priority
) {
1189 case RADEON_CTX_PRIORITY_REALTIME
:
1190 return AMDGPU_CTX_PRIORITY_VERY_HIGH
;
1191 case RADEON_CTX_PRIORITY_HIGH
:
1192 return AMDGPU_CTX_PRIORITY_HIGH
;
1193 case RADEON_CTX_PRIORITY_MEDIUM
:
1194 return AMDGPU_CTX_PRIORITY_NORMAL
;
1195 case RADEON_CTX_PRIORITY_LOW
:
1196 return AMDGPU_CTX_PRIORITY_LOW
;
1198 unreachable("Invalid context priority");
1202 static struct radeon_winsys_ctx
*radv_amdgpu_ctx_create(struct radeon_winsys
*_ws
,
1203 enum radeon_ctx_priority priority
)
1205 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1206 struct radv_amdgpu_ctx
*ctx
= CALLOC_STRUCT(radv_amdgpu_ctx
);
1207 uint32_t amdgpu_priority
= radv_to_amdgpu_priority(priority
);
1213 r
= amdgpu_cs_ctx_create2(ws
->dev
, amdgpu_priority
, &ctx
->ctx
);
1215 fprintf(stderr
, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r
);
1220 assert(AMDGPU_HW_IP_NUM
* MAX_RINGS_PER_TYPE
* sizeof(uint64_t) <= 4096);
1221 ctx
->fence_bo
= ws
->base
.buffer_create(&ws
->base
, 4096, 8,
1223 RADEON_FLAG_CPU_ACCESS
|
1224 RADEON_FLAG_NO_INTERPROCESS_SHARING
);
1226 ctx
->fence_map
= (uint64_t*)ws
->base
.buffer_map(ctx
->fence_bo
);
1228 memset(ctx
->fence_map
, 0, 4096);
1229 return (struct radeon_winsys_ctx
*)ctx
;
1235 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
1237 struct radv_amdgpu_ctx
*ctx
= (struct radv_amdgpu_ctx
*)rwctx
;
1238 ctx
->ws
->base
.buffer_destroy(ctx
->fence_bo
);
1239 amdgpu_cs_ctx_free(ctx
->ctx
);
1243 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx
*rwctx
,
1244 enum ring_type ring_type
, int ring_index
)
1246 struct radv_amdgpu_ctx
*ctx
= (struct radv_amdgpu_ctx
*)rwctx
;
1247 int ip_type
= ring_to_hw_ip(ring_type
);
1249 if (ctx
->last_submission
[ip_type
][ring_index
].fence
.fence
) {
1251 int ret
= amdgpu_cs_query_fence_status(&ctx
->last_submission
[ip_type
][ring_index
].fence
,
1252 1000000000ull, 0, &expired
);
1254 if (ret
|| !expired
)
1261 static struct radeon_winsys_sem
*radv_amdgpu_create_sem(struct radeon_winsys
*_ws
)
1263 struct amdgpu_cs_fence
*sem
= CALLOC_STRUCT(amdgpu_cs_fence
);
1267 return (struct radeon_winsys_sem
*)sem
;
1270 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem
*_sem
)
1272 struct amdgpu_cs_fence
*sem
= (struct amdgpu_cs_fence
*)_sem
;
1276 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx
*ctx
,
1279 struct radv_winsys_sem_info
*sem_info
)
1281 for (unsigned i
= 0; i
< sem_info
->signal
.sem_count
; i
++) {
1282 struct amdgpu_cs_fence
*sem
= (struct amdgpu_cs_fence
*)(sem_info
->signal
.sem
)[i
];
1287 *sem
= ctx
->last_submission
[ip_type
][ring
].fence
;
1292 static struct drm_amdgpu_cs_chunk_sem
*radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts
*counts
,
1293 struct drm_amdgpu_cs_chunk
*chunk
, int chunk_id
)
1295 struct drm_amdgpu_cs_chunk_sem
*syncobj
= malloc(sizeof(struct drm_amdgpu_cs_chunk_sem
) * counts
->syncobj_count
);
1299 for (unsigned i
= 0; i
< counts
->syncobj_count
; i
++) {
1300 struct drm_amdgpu_cs_chunk_sem
*sem
= &syncobj
[i
];
1301 sem
->handle
= counts
->syncobj
[i
];
1304 chunk
->chunk_id
= chunk_id
;
1305 chunk
->length_dw
= sizeof(struct drm_amdgpu_cs_chunk_sem
) / 4 * counts
->syncobj_count
;
1306 chunk
->chunk_data
= (uint64_t)(uintptr_t)syncobj
;
1310 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx
*ctx
,
1311 struct amdgpu_cs_request
*request
,
1312 struct radv_winsys_sem_info
*sem_info
)
1318 struct drm_amdgpu_cs_chunk
*chunks
;
1319 struct drm_amdgpu_cs_chunk_data
*chunk_data
;
1320 struct drm_amdgpu_cs_chunk_dep
*sem_dependencies
= NULL
;
1321 struct drm_amdgpu_cs_chunk_sem
*wait_syncobj
= NULL
, *signal_syncobj
= NULL
;
1323 struct amdgpu_cs_fence
*sem
;
1325 user_fence
= (request
->fence_info
.handle
!= NULL
);
1326 size
= request
->number_of_ibs
+ (user_fence
? 2 : 1) + 3;
1328 chunks
= alloca(sizeof(struct drm_amdgpu_cs_chunk
) * size
);
1330 size
= request
->number_of_ibs
+ (user_fence
? 1 : 0);
1332 chunk_data
= alloca(sizeof(struct drm_amdgpu_cs_chunk_data
) * size
);
1334 num_chunks
= request
->number_of_ibs
;
1335 for (i
= 0; i
< request
->number_of_ibs
; i
++) {
1336 struct amdgpu_cs_ib_info
*ib
;
1337 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1338 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1339 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)&chunk_data
[i
];
1341 ib
= &request
->ibs
[i
];
1343 chunk_data
[i
].ib_data
._pad
= 0;
1344 chunk_data
[i
].ib_data
.va_start
= ib
->ib_mc_address
;
1345 chunk_data
[i
].ib_data
.ib_bytes
= ib
->size
* 4;
1346 chunk_data
[i
].ib_data
.ip_type
= request
->ip_type
;
1347 chunk_data
[i
].ib_data
.ip_instance
= request
->ip_instance
;
1348 chunk_data
[i
].ib_data
.ring
= request
->ring
;
1349 chunk_data
[i
].ib_data
.flags
= ib
->flags
;
1355 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1356 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1357 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)&chunk_data
[i
];
1359 amdgpu_cs_chunk_fence_info_to_data(&request
->fence_info
,
1363 if (sem_info
->wait
.syncobj_count
&& sem_info
->cs_emit_wait
) {
1364 wait_syncobj
= radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info
->wait
,
1365 &chunks
[num_chunks
],
1366 AMDGPU_CHUNK_ID_SYNCOBJ_IN
);
1367 if (!wait_syncobj
) {
1373 if (sem_info
->wait
.sem_count
== 0)
1374 sem_info
->cs_emit_wait
= false;
1378 if (sem_info
->wait
.sem_count
&& sem_info
->cs_emit_wait
) {
1379 sem_dependencies
= malloc(sizeof(struct drm_amdgpu_cs_chunk_dep
) * sem_info
->wait
.sem_count
);
1380 if (!sem_dependencies
) {
1385 for (unsigned j
= 0; j
< sem_info
->wait
.sem_count
; j
++) {
1386 sem
= (struct amdgpu_cs_fence
*)sem_info
->wait
.sem
[j
];
1389 struct drm_amdgpu_cs_chunk_dep
*dep
= &sem_dependencies
[sem_count
++];
1391 amdgpu_cs_chunk_fence_to_dep(sem
, dep
);
1393 sem
->context
= NULL
;
1397 /* dependencies chunk */
1398 chunks
[i
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1399 chunks
[i
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_dep
) / 4 * sem_count
;
1400 chunks
[i
].chunk_data
= (uint64_t)(uintptr_t)sem_dependencies
;
1402 sem_info
->cs_emit_wait
= false;
1405 if (sem_info
->signal
.syncobj_count
&& sem_info
->cs_emit_signal
) {
1406 signal_syncobj
= radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info
->signal
,
1407 &chunks
[num_chunks
],
1408 AMDGPU_CHUNK_ID_SYNCOBJ_OUT
);
1409 if (!signal_syncobj
) {
1416 r
= amdgpu_cs_submit_raw(ctx
->ws
->dev
,
1423 free(sem_dependencies
);
1425 free(signal_syncobj
);
1429 static int radv_amdgpu_create_syncobj(struct radeon_winsys
*_ws
,
1432 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1433 return amdgpu_cs_create_syncobj(ws
->dev
, handle
);
1436 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys
*_ws
,
1439 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1440 amdgpu_cs_destroy_syncobj(ws
->dev
, handle
);
1443 static void radv_amdgpu_reset_syncobj(struct radeon_winsys
*_ws
,
1446 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1447 amdgpu_cs_syncobj_reset(ws
->dev
, &handle
, 1);
1450 static void radv_amdgpu_signal_syncobj(struct radeon_winsys
*_ws
,
1453 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1454 amdgpu_cs_syncobj_signal(ws
->dev
, &handle
, 1);
1457 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys
*_ws
, const uint32_t *handles
,
1458 uint32_t handle_count
, bool wait_all
, uint64_t timeout
)
1460 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1463 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1464 timeout
= MIN2(timeout
, INT64_MAX
);
1466 int ret
= amdgpu_cs_syncobj_wait(ws
->dev
, (uint32_t*)handles
, handle_count
, timeout
,
1467 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT
|
1468 (wait_all
? DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL
: 0),
1472 } else if (ret
== -1 && errno
== ETIME
) {
1475 fprintf(stderr
, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno
);
1480 static int radv_amdgpu_export_syncobj(struct radeon_winsys
*_ws
,
1484 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1486 return amdgpu_cs_export_syncobj(ws
->dev
, syncobj
, fd
);
1489 static int radv_amdgpu_import_syncobj(struct radeon_winsys
*_ws
,
1493 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1495 return amdgpu_cs_import_syncobj(ws
->dev
, fd
, syncobj
);
1499 static int radv_amdgpu_export_syncobj_to_sync_file(struct radeon_winsys
*_ws
,
1503 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1505 return amdgpu_cs_syncobj_export_sync_file(ws
->dev
, syncobj
, fd
);
1508 static int radv_amdgpu_import_syncobj_from_sync_file(struct radeon_winsys
*_ws
,
1512 struct radv_amdgpu_winsys
*ws
= radv_amdgpu_winsys(_ws
);
1514 return amdgpu_cs_syncobj_import_sync_file(ws
->dev
, syncobj
, fd
);
1517 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys
*ws
)
1519 ws
->base
.ctx_create
= radv_amdgpu_ctx_create
;
1520 ws
->base
.ctx_destroy
= radv_amdgpu_ctx_destroy
;
1521 ws
->base
.ctx_wait_idle
= radv_amdgpu_ctx_wait_idle
;
1522 ws
->base
.cs_create
= radv_amdgpu_cs_create
;
1523 ws
->base
.cs_destroy
= radv_amdgpu_cs_destroy
;
1524 ws
->base
.cs_grow
= radv_amdgpu_cs_grow
;
1525 ws
->base
.cs_finalize
= radv_amdgpu_cs_finalize
;
1526 ws
->base
.cs_reset
= radv_amdgpu_cs_reset
;
1527 ws
->base
.cs_add_buffer
= radv_amdgpu_cs_add_buffer
;
1528 ws
->base
.cs_execute_secondary
= radv_amdgpu_cs_execute_secondary
;
1529 ws
->base
.cs_submit
= radv_amdgpu_winsys_cs_submit
;
1530 ws
->base
.cs_dump
= radv_amdgpu_winsys_cs_dump
;
1531 ws
->base
.create_fence
= radv_amdgpu_create_fence
;
1532 ws
->base
.destroy_fence
= radv_amdgpu_destroy_fence
;
1533 ws
->base
.create_sem
= radv_amdgpu_create_sem
;
1534 ws
->base
.destroy_sem
= radv_amdgpu_destroy_sem
;
1535 ws
->base
.create_syncobj
= radv_amdgpu_create_syncobj
;
1536 ws
->base
.destroy_syncobj
= radv_amdgpu_destroy_syncobj
;
1537 ws
->base
.reset_syncobj
= radv_amdgpu_reset_syncobj
;
1538 ws
->base
.signal_syncobj
= radv_amdgpu_signal_syncobj
;
1539 ws
->base
.wait_syncobj
= radv_amdgpu_wait_syncobj
;
1540 ws
->base
.export_syncobj
= radv_amdgpu_export_syncobj
;
1541 ws
->base
.import_syncobj
= radv_amdgpu_import_syncobj
;
1542 ws
->base
.export_syncobj_to_sync_file
= radv_amdgpu_export_syncobj_to_sync_file
;
1543 ws
->base
.import_syncobj_from_sync_file
= radv_amdgpu_import_syncobj_from_sync_file
;
1544 ws
->base
.fence_wait
= radv_amdgpu_fence_wait
;
1545 ws
->base
.fences_wait
= radv_amdgpu_fences_wait
;